csp.dts 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /dts-v1/;
  3. / {
  4. compatible = "cdns,xtensa-xtfpga";
  5. #address-cells = <1>;
  6. #size-cells = <1>;
  7. interrupt-parent = <&pic>;
  8. chosen {
  9. bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
  10. };
  11. memory@0 {
  12. device_type = "memory";
  13. reg = <0x00000000 0x40000000>;
  14. };
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu@0 {
  19. compatible = "cdns,xtensa-cpu";
  20. reg = <0>;
  21. };
  22. };
  23. pic: pic {
  24. compatible = "cdns,xtensa-pic";
  25. #interrupt-cells = <2>;
  26. interrupt-controller;
  27. };
  28. clocks {
  29. osc: main-oscillator {
  30. #clock-cells = <0>;
  31. compatible = "fixed-clock";
  32. };
  33. };
  34. soc {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. compatible = "simple-bus";
  38. ranges = <0x00000000 0xf0000000 0x10000000>;
  39. uart0: serial@0d000000 {
  40. compatible = "xlnx,xuartps", "cdns,uart-r1p8";
  41. clocks = <&osc>, <&osc>;
  42. clock-names = "uart_clk", "pclk";
  43. reg = <0x0d000000 0x1000>;
  44. interrupts = <0 1>;
  45. };
  46. };
  47. };