smp_64.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* smp.c: Sparc64 SMP support.
  3. *
  4. * Copyright (C) 1997, 2007, 2008 David S. Miller ([email protected])
  5. */
  6. #include <linux/export.h>
  7. #include <linux/kernel.h>
  8. #include <linux/sched/mm.h>
  9. #include <linux/sched/hotplug.h>
  10. #include <linux/mm.h>
  11. #include <linux/pagemap.h>
  12. #include <linux/threads.h>
  13. #include <linux/smp.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/kernel_stat.h>
  16. #include <linux/delay.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/fs.h>
  20. #include <linux/seq_file.h>
  21. #include <linux/cache.h>
  22. #include <linux/jiffies.h>
  23. #include <linux/profile.h>
  24. #include <linux/memblock.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/ftrace.h>
  27. #include <linux/cpu.h>
  28. #include <linux/slab.h>
  29. #include <linux/kgdb.h>
  30. #include <asm/head.h>
  31. #include <asm/ptrace.h>
  32. #include <linux/atomic.h>
  33. #include <asm/tlbflush.h>
  34. #include <asm/mmu_context.h>
  35. #include <asm/cpudata.h>
  36. #include <asm/hvtramp.h>
  37. #include <asm/io.h>
  38. #include <asm/timer.h>
  39. #include <asm/setup.h>
  40. #include <asm/irq.h>
  41. #include <asm/irq_regs.h>
  42. #include <asm/page.h>
  43. #include <asm/oplib.h>
  44. #include <linux/uaccess.h>
  45. #include <asm/starfire.h>
  46. #include <asm/tlb.h>
  47. #include <asm/pgalloc.h>
  48. #include <asm/sections.h>
  49. #include <asm/prom.h>
  50. #include <asm/mdesc.h>
  51. #include <asm/ldc.h>
  52. #include <asm/hypervisor.h>
  53. #include <asm/pcr.h>
  54. #include "cpumap.h"
  55. #include "kernel.h"
  56. DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  57. cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  58. { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  59. cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = {
  60. [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  61. cpumask_t cpu_core_sib_cache_map[NR_CPUS] __read_mostly = {
  62. [0 ... NR_CPUS - 1] = CPU_MASK_NONE };
  63. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  64. EXPORT_SYMBOL(cpu_core_map);
  65. EXPORT_SYMBOL(cpu_core_sib_map);
  66. EXPORT_SYMBOL(cpu_core_sib_cache_map);
  67. static cpumask_t smp_commenced_mask;
  68. static DEFINE_PER_CPU(bool, poke);
  69. static bool cpu_poke;
  70. void smp_info(struct seq_file *m)
  71. {
  72. int i;
  73. seq_printf(m, "State:\n");
  74. for_each_online_cpu(i)
  75. seq_printf(m, "CPU%d:\t\tonline\n", i);
  76. }
  77. void smp_bogo(struct seq_file *m)
  78. {
  79. int i;
  80. for_each_online_cpu(i)
  81. seq_printf(m,
  82. "Cpu%dClkTck\t: %016lx\n",
  83. i, cpu_data(i).clock_tick);
  84. }
  85. extern void setup_sparc64_timer(void);
  86. static volatile unsigned long callin_flag = 0;
  87. void smp_callin(void)
  88. {
  89. int cpuid = hard_smp_processor_id();
  90. __local_per_cpu_offset = __per_cpu_offset(cpuid);
  91. if (tlb_type == hypervisor)
  92. sun4v_ktsb_register();
  93. __flush_tlb_all();
  94. setup_sparc64_timer();
  95. if (cheetah_pcache_forced_on)
  96. cheetah_enable_pcache();
  97. callin_flag = 1;
  98. __asm__ __volatile__("membar #Sync\n\t"
  99. "flush %%g6" : : : "memory");
  100. /* Clear this or we will die instantly when we
  101. * schedule back to this idler...
  102. */
  103. current_thread_info()->new_child = 0;
  104. /* Attach to the address space of init_task. */
  105. mmgrab(&init_mm);
  106. current->active_mm = &init_mm;
  107. /* inform the notifiers about the new cpu */
  108. notify_cpu_starting(cpuid);
  109. while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
  110. rmb();
  111. set_cpu_online(cpuid, true);
  112. local_irq_enable();
  113. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  114. }
  115. void cpu_panic(void)
  116. {
  117. printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
  118. panic("SMP bolixed\n");
  119. }
  120. /* This tick register synchronization scheme is taken entirely from
  121. * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
  122. *
  123. * The only change I've made is to rework it so that the master
  124. * initiates the synchonization instead of the slave. -DaveM
  125. */
  126. #define MASTER 0
  127. #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
  128. #define NUM_ROUNDS 64 /* magic value */
  129. #define NUM_ITERS 5 /* likewise */
  130. static DEFINE_RAW_SPINLOCK(itc_sync_lock);
  131. static unsigned long go[SLAVE + 1];
  132. #define DEBUG_TICK_SYNC 0
  133. static inline long get_delta (long *rt, long *master)
  134. {
  135. unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
  136. unsigned long tcenter, t0, t1, tm;
  137. unsigned long i;
  138. for (i = 0; i < NUM_ITERS; i++) {
  139. t0 = tick_ops->get_tick();
  140. go[MASTER] = 1;
  141. membar_safe("#StoreLoad");
  142. while (!(tm = go[SLAVE]))
  143. rmb();
  144. go[SLAVE] = 0;
  145. wmb();
  146. t1 = tick_ops->get_tick();
  147. if (t1 - t0 < best_t1 - best_t0)
  148. best_t0 = t0, best_t1 = t1, best_tm = tm;
  149. }
  150. *rt = best_t1 - best_t0;
  151. *master = best_tm - best_t0;
  152. /* average best_t0 and best_t1 without overflow: */
  153. tcenter = (best_t0/2 + best_t1/2);
  154. if (best_t0 % 2 + best_t1 % 2 == 2)
  155. tcenter++;
  156. return tcenter - best_tm;
  157. }
  158. void smp_synchronize_tick_client(void)
  159. {
  160. long i, delta, adj, adjust_latency = 0, done = 0;
  161. unsigned long flags, rt, master_time_stamp;
  162. #if DEBUG_TICK_SYNC
  163. struct {
  164. long rt; /* roundtrip time */
  165. long master; /* master's timestamp */
  166. long diff; /* difference between midpoint and master's timestamp */
  167. long lat; /* estimate of itc adjustment latency */
  168. } t[NUM_ROUNDS];
  169. #endif
  170. go[MASTER] = 1;
  171. while (go[MASTER])
  172. rmb();
  173. local_irq_save(flags);
  174. {
  175. for (i = 0; i < NUM_ROUNDS; i++) {
  176. delta = get_delta(&rt, &master_time_stamp);
  177. if (delta == 0)
  178. done = 1; /* let's lock on to this... */
  179. if (!done) {
  180. if (i > 0) {
  181. adjust_latency += -delta;
  182. adj = -delta + adjust_latency/4;
  183. } else
  184. adj = -delta;
  185. tick_ops->add_tick(adj);
  186. }
  187. #if DEBUG_TICK_SYNC
  188. t[i].rt = rt;
  189. t[i].master = master_time_stamp;
  190. t[i].diff = delta;
  191. t[i].lat = adjust_latency/4;
  192. #endif
  193. }
  194. }
  195. local_irq_restore(flags);
  196. #if DEBUG_TICK_SYNC
  197. for (i = 0; i < NUM_ROUNDS; i++)
  198. printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
  199. t[i].rt, t[i].master, t[i].diff, t[i].lat);
  200. #endif
  201. printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
  202. "(last diff %ld cycles, maxerr %lu cycles)\n",
  203. smp_processor_id(), delta, rt);
  204. }
  205. static void smp_start_sync_tick_client(int cpu);
  206. static void smp_synchronize_one_tick(int cpu)
  207. {
  208. unsigned long flags, i;
  209. go[MASTER] = 0;
  210. smp_start_sync_tick_client(cpu);
  211. /* wait for client to be ready */
  212. while (!go[MASTER])
  213. rmb();
  214. /* now let the client proceed into his loop */
  215. go[MASTER] = 0;
  216. membar_safe("#StoreLoad");
  217. raw_spin_lock_irqsave(&itc_sync_lock, flags);
  218. {
  219. for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
  220. while (!go[MASTER])
  221. rmb();
  222. go[MASTER] = 0;
  223. wmb();
  224. go[SLAVE] = tick_ops->get_tick();
  225. membar_safe("#StoreLoad");
  226. }
  227. }
  228. raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
  229. }
  230. #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
  231. static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
  232. void **descrp)
  233. {
  234. extern unsigned long sparc64_ttable_tl0;
  235. extern unsigned long kern_locked_tte_data;
  236. struct hvtramp_descr *hdesc;
  237. unsigned long trampoline_ra;
  238. struct trap_per_cpu *tb;
  239. u64 tte_vaddr, tte_data;
  240. unsigned long hv_err;
  241. int i;
  242. hdesc = kzalloc(sizeof(*hdesc) +
  243. (sizeof(struct hvtramp_mapping) *
  244. num_kernel_image_mappings - 1),
  245. GFP_KERNEL);
  246. if (!hdesc) {
  247. printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
  248. "hvtramp_descr.\n");
  249. return;
  250. }
  251. *descrp = hdesc;
  252. hdesc->cpu = cpu;
  253. hdesc->num_mappings = num_kernel_image_mappings;
  254. tb = &trap_block[cpu];
  255. hdesc->fault_info_va = (unsigned long) &tb->fault_info;
  256. hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
  257. hdesc->thread_reg = thread_reg;
  258. tte_vaddr = (unsigned long) KERNBASE;
  259. tte_data = kern_locked_tte_data;
  260. for (i = 0; i < hdesc->num_mappings; i++) {
  261. hdesc->maps[i].vaddr = tte_vaddr;
  262. hdesc->maps[i].tte = tte_data;
  263. tte_vaddr += 0x400000;
  264. tte_data += 0x400000;
  265. }
  266. trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
  267. hv_err = sun4v_cpu_start(cpu, trampoline_ra,
  268. kimage_addr_to_ra(&sparc64_ttable_tl0),
  269. __pa(hdesc));
  270. if (hv_err)
  271. printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
  272. "gives error %lu\n", hv_err);
  273. }
  274. #endif
  275. extern unsigned long sparc64_cpu_startup;
  276. /* The OBP cpu startup callback truncates the 3rd arg cookie to
  277. * 32-bits (I think) so to be safe we have it read the pointer
  278. * contained here so we work on >4GB machines. -DaveM
  279. */
  280. static struct thread_info *cpu_new_thread = NULL;
  281. static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
  282. {
  283. unsigned long entry =
  284. (unsigned long)(&sparc64_cpu_startup);
  285. unsigned long cookie =
  286. (unsigned long)(&cpu_new_thread);
  287. void *descr = NULL;
  288. int timeout, ret;
  289. callin_flag = 0;
  290. cpu_new_thread = task_thread_info(idle);
  291. if (tlb_type == hypervisor) {
  292. #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
  293. if (ldom_domaining_enabled)
  294. ldom_startcpu_cpuid(cpu,
  295. (unsigned long) cpu_new_thread,
  296. &descr);
  297. else
  298. #endif
  299. prom_startcpu_cpuid(cpu, entry, cookie);
  300. } else {
  301. struct device_node *dp = of_find_node_by_cpuid(cpu);
  302. prom_startcpu(dp->phandle, entry, cookie);
  303. }
  304. for (timeout = 0; timeout < 50000; timeout++) {
  305. if (callin_flag)
  306. break;
  307. udelay(100);
  308. }
  309. if (callin_flag) {
  310. ret = 0;
  311. } else {
  312. printk("Processor %d is stuck.\n", cpu);
  313. ret = -ENODEV;
  314. }
  315. cpu_new_thread = NULL;
  316. kfree(descr);
  317. return ret;
  318. }
  319. static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
  320. {
  321. u64 result, target;
  322. int stuck, tmp;
  323. if (this_is_starfire) {
  324. /* map to real upaid */
  325. cpu = (((cpu & 0x3c) << 1) |
  326. ((cpu & 0x40) >> 4) |
  327. (cpu & 0x3));
  328. }
  329. target = (cpu << 14) | 0x70;
  330. again:
  331. /* Ok, this is the real Spitfire Errata #54.
  332. * One must read back from a UDB internal register
  333. * after writes to the UDB interrupt dispatch, but
  334. * before the membar Sync for that write.
  335. * So we use the high UDB control register (ASI 0x7f,
  336. * ADDR 0x20) for the dummy read. -DaveM
  337. */
  338. tmp = 0x40;
  339. __asm__ __volatile__(
  340. "wrpr %1, %2, %%pstate\n\t"
  341. "stxa %4, [%0] %3\n\t"
  342. "stxa %5, [%0+%8] %3\n\t"
  343. "add %0, %8, %0\n\t"
  344. "stxa %6, [%0+%8] %3\n\t"
  345. "membar #Sync\n\t"
  346. "stxa %%g0, [%7] %3\n\t"
  347. "membar #Sync\n\t"
  348. "mov 0x20, %%g1\n\t"
  349. "ldxa [%%g1] 0x7f, %%g0\n\t"
  350. "membar #Sync"
  351. : "=r" (tmp)
  352. : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
  353. "r" (data0), "r" (data1), "r" (data2), "r" (target),
  354. "r" (0x10), "0" (tmp)
  355. : "g1");
  356. /* NOTE: PSTATE_IE is still clear. */
  357. stuck = 100000;
  358. do {
  359. __asm__ __volatile__("ldxa [%%g0] %1, %0"
  360. : "=r" (result)
  361. : "i" (ASI_INTR_DISPATCH_STAT));
  362. if (result == 0) {
  363. __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
  364. : : "r" (pstate));
  365. return;
  366. }
  367. stuck -= 1;
  368. if (stuck == 0)
  369. break;
  370. } while (result & 0x1);
  371. __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
  372. : : "r" (pstate));
  373. if (stuck == 0) {
  374. printk("CPU[%d]: mondo stuckage result[%016llx]\n",
  375. smp_processor_id(), result);
  376. } else {
  377. udelay(2);
  378. goto again;
  379. }
  380. }
  381. static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
  382. {
  383. u64 *mondo, data0, data1, data2;
  384. u16 *cpu_list;
  385. u64 pstate;
  386. int i;
  387. __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
  388. cpu_list = __va(tb->cpu_list_pa);
  389. mondo = __va(tb->cpu_mondo_block_pa);
  390. data0 = mondo[0];
  391. data1 = mondo[1];
  392. data2 = mondo[2];
  393. for (i = 0; i < cnt; i++)
  394. spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
  395. }
  396. /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
  397. * packet, but we have no use for that. However we do take advantage of
  398. * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
  399. */
  400. static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
  401. {
  402. int nack_busy_id, is_jbus, need_more;
  403. u64 *mondo, pstate, ver, busy_mask;
  404. u16 *cpu_list;
  405. cpu_list = __va(tb->cpu_list_pa);
  406. mondo = __va(tb->cpu_mondo_block_pa);
  407. /* Unfortunately, someone at Sun had the brilliant idea to make the
  408. * busy/nack fields hard-coded by ITID number for this Ultra-III
  409. * derivative processor.
  410. */
  411. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  412. is_jbus = ((ver >> 32) == __JALAPENO_ID ||
  413. (ver >> 32) == __SERRANO_ID);
  414. __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
  415. retry:
  416. need_more = 0;
  417. __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
  418. : : "r" (pstate), "i" (PSTATE_IE));
  419. /* Setup the dispatch data registers. */
  420. __asm__ __volatile__("stxa %0, [%3] %6\n\t"
  421. "stxa %1, [%4] %6\n\t"
  422. "stxa %2, [%5] %6\n\t"
  423. "membar #Sync\n\t"
  424. : /* no outputs */
  425. : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
  426. "r" (0x40), "r" (0x50), "r" (0x60),
  427. "i" (ASI_INTR_W));
  428. nack_busy_id = 0;
  429. busy_mask = 0;
  430. {
  431. int i;
  432. for (i = 0; i < cnt; i++) {
  433. u64 target, nr;
  434. nr = cpu_list[i];
  435. if (nr == 0xffff)
  436. continue;
  437. target = (nr << 14) | 0x70;
  438. if (is_jbus) {
  439. busy_mask |= (0x1UL << (nr * 2));
  440. } else {
  441. target |= (nack_busy_id << 24);
  442. busy_mask |= (0x1UL <<
  443. (nack_busy_id * 2));
  444. }
  445. __asm__ __volatile__(
  446. "stxa %%g0, [%0] %1\n\t"
  447. "membar #Sync\n\t"
  448. : /* no outputs */
  449. : "r" (target), "i" (ASI_INTR_W));
  450. nack_busy_id++;
  451. if (nack_busy_id == 32) {
  452. need_more = 1;
  453. break;
  454. }
  455. }
  456. }
  457. /* Now, poll for completion. */
  458. {
  459. u64 dispatch_stat, nack_mask;
  460. long stuck;
  461. stuck = 100000 * nack_busy_id;
  462. nack_mask = busy_mask << 1;
  463. do {
  464. __asm__ __volatile__("ldxa [%%g0] %1, %0"
  465. : "=r" (dispatch_stat)
  466. : "i" (ASI_INTR_DISPATCH_STAT));
  467. if (!(dispatch_stat & (busy_mask | nack_mask))) {
  468. __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
  469. : : "r" (pstate));
  470. if (unlikely(need_more)) {
  471. int i, this_cnt = 0;
  472. for (i = 0; i < cnt; i++) {
  473. if (cpu_list[i] == 0xffff)
  474. continue;
  475. cpu_list[i] = 0xffff;
  476. this_cnt++;
  477. if (this_cnt == 32)
  478. break;
  479. }
  480. goto retry;
  481. }
  482. return;
  483. }
  484. if (!--stuck)
  485. break;
  486. } while (dispatch_stat & busy_mask);
  487. __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
  488. : : "r" (pstate));
  489. if (dispatch_stat & busy_mask) {
  490. /* Busy bits will not clear, continue instead
  491. * of freezing up on this cpu.
  492. */
  493. printk("CPU[%d]: mondo stuckage result[%016llx]\n",
  494. smp_processor_id(), dispatch_stat);
  495. } else {
  496. int i, this_busy_nack = 0;
  497. /* Delay some random time with interrupts enabled
  498. * to prevent deadlock.
  499. */
  500. udelay(2 * nack_busy_id);
  501. /* Clear out the mask bits for cpus which did not
  502. * NACK us.
  503. */
  504. for (i = 0; i < cnt; i++) {
  505. u64 check_mask, nr;
  506. nr = cpu_list[i];
  507. if (nr == 0xffff)
  508. continue;
  509. if (is_jbus)
  510. check_mask = (0x2UL << (2*nr));
  511. else
  512. check_mask = (0x2UL <<
  513. this_busy_nack);
  514. if ((dispatch_stat & check_mask) == 0)
  515. cpu_list[i] = 0xffff;
  516. this_busy_nack += 2;
  517. if (this_busy_nack == 64)
  518. break;
  519. }
  520. goto retry;
  521. }
  522. }
  523. }
  524. #define CPU_MONDO_COUNTER(cpuid) (cpu_mondo_counter[cpuid])
  525. #define MONDO_USEC_WAIT_MIN 2
  526. #define MONDO_USEC_WAIT_MAX 100
  527. #define MONDO_RETRY_LIMIT 500000
  528. /* Multi-cpu list version.
  529. *
  530. * Deliver xcalls to 'cnt' number of cpus in 'cpu_list'.
  531. * Sometimes not all cpus receive the mondo, requiring us to re-send
  532. * the mondo until all cpus have received, or cpus are truly stuck
  533. * unable to receive mondo, and we timeout.
  534. * Occasionally a target cpu strand is borrowed briefly by hypervisor to
  535. * perform guest service, such as PCIe error handling. Consider the
  536. * service time, 1 second overall wait is reasonable for 1 cpu.
  537. * Here two in-between mondo check wait time are defined: 2 usec for
  538. * single cpu quick turn around and up to 100usec for large cpu count.
  539. * Deliver mondo to large number of cpus could take longer, we adjusts
  540. * the retry count as long as target cpus are making forward progress.
  541. */
  542. static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
  543. {
  544. int this_cpu, tot_cpus, prev_sent, i, rem;
  545. int usec_wait, retries, tot_retries;
  546. u16 first_cpu = 0xffff;
  547. unsigned long xc_rcvd = 0;
  548. unsigned long status;
  549. int ecpuerror_id = 0;
  550. int enocpu_id = 0;
  551. u16 *cpu_list;
  552. u16 cpu;
  553. this_cpu = smp_processor_id();
  554. cpu_list = __va(tb->cpu_list_pa);
  555. usec_wait = cnt * MONDO_USEC_WAIT_MIN;
  556. if (usec_wait > MONDO_USEC_WAIT_MAX)
  557. usec_wait = MONDO_USEC_WAIT_MAX;
  558. retries = tot_retries = 0;
  559. tot_cpus = cnt;
  560. prev_sent = 0;
  561. do {
  562. int n_sent, mondo_delivered, target_cpu_busy;
  563. status = sun4v_cpu_mondo_send(cnt,
  564. tb->cpu_list_pa,
  565. tb->cpu_mondo_block_pa);
  566. /* HV_EOK means all cpus received the xcall, we're done. */
  567. if (likely(status == HV_EOK))
  568. goto xcall_done;
  569. /* If not these non-fatal errors, panic */
  570. if (unlikely((status != HV_EWOULDBLOCK) &&
  571. (status != HV_ECPUERROR) &&
  572. (status != HV_ENOCPU)))
  573. goto fatal_errors;
  574. /* First, see if we made any forward progress.
  575. *
  576. * Go through the cpu_list, count the target cpus that have
  577. * received our mondo (n_sent), and those that did not (rem).
  578. * Re-pack cpu_list with the cpus remain to be retried in the
  579. * front - this simplifies tracking the truly stalled cpus.
  580. *
  581. * The hypervisor indicates successful sends by setting
  582. * cpu list entries to the value 0xffff.
  583. *
  584. * EWOULDBLOCK means some target cpus did not receive the
  585. * mondo and retry usually helps.
  586. *
  587. * ECPUERROR means at least one target cpu is in error state,
  588. * it's usually safe to skip the faulty cpu and retry.
  589. *
  590. * ENOCPU means one of the target cpu doesn't belong to the
  591. * domain, perhaps offlined which is unexpected, but not
  592. * fatal and it's okay to skip the offlined cpu.
  593. */
  594. rem = 0;
  595. n_sent = 0;
  596. for (i = 0; i < cnt; i++) {
  597. cpu = cpu_list[i];
  598. if (likely(cpu == 0xffff)) {
  599. n_sent++;
  600. } else if ((status == HV_ECPUERROR) &&
  601. (sun4v_cpu_state(cpu) == HV_CPU_STATE_ERROR)) {
  602. ecpuerror_id = cpu + 1;
  603. } else if (status == HV_ENOCPU && !cpu_online(cpu)) {
  604. enocpu_id = cpu + 1;
  605. } else {
  606. cpu_list[rem++] = cpu;
  607. }
  608. }
  609. /* No cpu remained, we're done. */
  610. if (rem == 0)
  611. break;
  612. /* Otherwise, update the cpu count for retry. */
  613. cnt = rem;
  614. /* Record the overall number of mondos received by the
  615. * first of the remaining cpus.
  616. */
  617. if (first_cpu != cpu_list[0]) {
  618. first_cpu = cpu_list[0];
  619. xc_rcvd = CPU_MONDO_COUNTER(first_cpu);
  620. }
  621. /* Was any mondo delivered successfully? */
  622. mondo_delivered = (n_sent > prev_sent);
  623. prev_sent = n_sent;
  624. /* or, was any target cpu busy processing other mondos? */
  625. target_cpu_busy = (xc_rcvd < CPU_MONDO_COUNTER(first_cpu));
  626. xc_rcvd = CPU_MONDO_COUNTER(first_cpu);
  627. /* Retry count is for no progress. If we're making progress,
  628. * reset the retry count.
  629. */
  630. if (likely(mondo_delivered || target_cpu_busy)) {
  631. tot_retries += retries;
  632. retries = 0;
  633. } else if (unlikely(retries > MONDO_RETRY_LIMIT)) {
  634. goto fatal_mondo_timeout;
  635. }
  636. /* Delay a little bit to let other cpus catch up on
  637. * their cpu mondo queue work.
  638. */
  639. if (!mondo_delivered)
  640. udelay(usec_wait);
  641. retries++;
  642. } while (1);
  643. xcall_done:
  644. if (unlikely(ecpuerror_id > 0)) {
  645. pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) was in error state\n",
  646. this_cpu, ecpuerror_id - 1);
  647. } else if (unlikely(enocpu_id > 0)) {
  648. pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) does not belong to the domain\n",
  649. this_cpu, enocpu_id - 1);
  650. }
  651. return;
  652. fatal_errors:
  653. /* fatal errors include bad alignment, etc */
  654. pr_crit("CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) mondo_block_pa(%lx)\n",
  655. this_cpu, tot_cpus, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
  656. panic("Unexpected SUN4V mondo error %lu\n", status);
  657. fatal_mondo_timeout:
  658. /* some cpus being non-responsive to the cpu mondo */
  659. pr_crit("CPU[%d]: SUN4V mondo timeout, cpu(%d) made no forward progress after %d retries. Total target cpus(%d).\n",
  660. this_cpu, first_cpu, (tot_retries + retries), tot_cpus);
  661. panic("SUN4V mondo timeout panic\n");
  662. }
  663. static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
  664. static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
  665. {
  666. struct trap_per_cpu *tb;
  667. int this_cpu, i, cnt;
  668. unsigned long flags;
  669. u16 *cpu_list;
  670. u64 *mondo;
  671. /* We have to do this whole thing with interrupts fully disabled.
  672. * Otherwise if we send an xcall from interrupt context it will
  673. * corrupt both our mondo block and cpu list state.
  674. *
  675. * One consequence of this is that we cannot use timeout mechanisms
  676. * that depend upon interrupts being delivered locally. So, for
  677. * example, we cannot sample jiffies and expect it to advance.
  678. *
  679. * Fortunately, udelay() uses %stick/%tick so we can use that.
  680. */
  681. local_irq_save(flags);
  682. this_cpu = smp_processor_id();
  683. tb = &trap_block[this_cpu];
  684. mondo = __va(tb->cpu_mondo_block_pa);
  685. mondo[0] = data0;
  686. mondo[1] = data1;
  687. mondo[2] = data2;
  688. wmb();
  689. cpu_list = __va(tb->cpu_list_pa);
  690. /* Setup the initial cpu list. */
  691. cnt = 0;
  692. for_each_cpu(i, mask) {
  693. if (i == this_cpu || !cpu_online(i))
  694. continue;
  695. cpu_list[cnt++] = i;
  696. }
  697. if (cnt)
  698. xcall_deliver_impl(tb, cnt);
  699. local_irq_restore(flags);
  700. }
  701. /* Send cross call to all processors mentioned in MASK_P
  702. * except self. Really, there are only two cases currently,
  703. * "cpu_online_mask" and "mm_cpumask(mm)".
  704. */
  705. static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
  706. {
  707. u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
  708. xcall_deliver(data0, data1, data2, mask);
  709. }
  710. /* Send cross call to all processors except self. */
  711. static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
  712. {
  713. smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
  714. }
  715. extern unsigned long xcall_sync_tick;
  716. static void smp_start_sync_tick_client(int cpu)
  717. {
  718. xcall_deliver((u64) &xcall_sync_tick, 0, 0,
  719. cpumask_of(cpu));
  720. }
  721. extern unsigned long xcall_call_function;
  722. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  723. {
  724. xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
  725. }
  726. extern unsigned long xcall_call_function_single;
  727. void arch_send_call_function_single_ipi(int cpu)
  728. {
  729. xcall_deliver((u64) &xcall_call_function_single, 0, 0,
  730. cpumask_of(cpu));
  731. }
  732. void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
  733. {
  734. clear_softint(1 << irq);
  735. irq_enter();
  736. generic_smp_call_function_interrupt();
  737. irq_exit();
  738. }
  739. void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
  740. {
  741. clear_softint(1 << irq);
  742. irq_enter();
  743. generic_smp_call_function_single_interrupt();
  744. irq_exit();
  745. }
  746. static void tsb_sync(void *info)
  747. {
  748. struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
  749. struct mm_struct *mm = info;
  750. /* It is not valid to test "current->active_mm == mm" here.
  751. *
  752. * The value of "current" is not changed atomically with
  753. * switch_mm(). But that's OK, we just need to check the
  754. * current cpu's trap block PGD physical address.
  755. */
  756. if (tp->pgd_paddr == __pa(mm->pgd))
  757. tsb_context_switch(mm);
  758. }
  759. void smp_tsb_sync(struct mm_struct *mm)
  760. {
  761. smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
  762. }
  763. extern unsigned long xcall_flush_tlb_mm;
  764. extern unsigned long xcall_flush_tlb_page;
  765. extern unsigned long xcall_flush_tlb_kernel_range;
  766. extern unsigned long xcall_fetch_glob_regs;
  767. extern unsigned long xcall_fetch_glob_pmu;
  768. extern unsigned long xcall_fetch_glob_pmu_n4;
  769. extern unsigned long xcall_receive_signal;
  770. extern unsigned long xcall_new_mmu_context_version;
  771. #ifdef CONFIG_KGDB
  772. extern unsigned long xcall_kgdb_capture;
  773. #endif
  774. #ifdef DCACHE_ALIASING_POSSIBLE
  775. extern unsigned long xcall_flush_dcache_page_cheetah;
  776. #endif
  777. extern unsigned long xcall_flush_dcache_page_spitfire;
  778. static inline void __local_flush_dcache_page(struct page *page)
  779. {
  780. #ifdef DCACHE_ALIASING_POSSIBLE
  781. __flush_dcache_page(page_address(page),
  782. ((tlb_type == spitfire) &&
  783. page_mapping_file(page) != NULL));
  784. #else
  785. if (page_mapping_file(page) != NULL &&
  786. tlb_type == spitfire)
  787. __flush_icache_page(__pa(page_address(page)));
  788. #endif
  789. }
  790. void smp_flush_dcache_page_impl(struct page *page, int cpu)
  791. {
  792. int this_cpu;
  793. if (tlb_type == hypervisor)
  794. return;
  795. #ifdef CONFIG_DEBUG_DCFLUSH
  796. atomic_inc(&dcpage_flushes);
  797. #endif
  798. this_cpu = get_cpu();
  799. if (cpu == this_cpu) {
  800. __local_flush_dcache_page(page);
  801. } else if (cpu_online(cpu)) {
  802. void *pg_addr = page_address(page);
  803. u64 data0 = 0;
  804. if (tlb_type == spitfire) {
  805. data0 = ((u64)&xcall_flush_dcache_page_spitfire);
  806. if (page_mapping_file(page) != NULL)
  807. data0 |= ((u64)1 << 32);
  808. } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  809. #ifdef DCACHE_ALIASING_POSSIBLE
  810. data0 = ((u64)&xcall_flush_dcache_page_cheetah);
  811. #endif
  812. }
  813. if (data0) {
  814. xcall_deliver(data0, __pa(pg_addr),
  815. (u64) pg_addr, cpumask_of(cpu));
  816. #ifdef CONFIG_DEBUG_DCFLUSH
  817. atomic_inc(&dcpage_flushes_xcall);
  818. #endif
  819. }
  820. }
  821. put_cpu();
  822. }
  823. void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
  824. {
  825. void *pg_addr;
  826. u64 data0;
  827. if (tlb_type == hypervisor)
  828. return;
  829. preempt_disable();
  830. #ifdef CONFIG_DEBUG_DCFLUSH
  831. atomic_inc(&dcpage_flushes);
  832. #endif
  833. data0 = 0;
  834. pg_addr = page_address(page);
  835. if (tlb_type == spitfire) {
  836. data0 = ((u64)&xcall_flush_dcache_page_spitfire);
  837. if (page_mapping_file(page) != NULL)
  838. data0 |= ((u64)1 << 32);
  839. } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  840. #ifdef DCACHE_ALIASING_POSSIBLE
  841. data0 = ((u64)&xcall_flush_dcache_page_cheetah);
  842. #endif
  843. }
  844. if (data0) {
  845. xcall_deliver(data0, __pa(pg_addr),
  846. (u64) pg_addr, cpu_online_mask);
  847. #ifdef CONFIG_DEBUG_DCFLUSH
  848. atomic_inc(&dcpage_flushes_xcall);
  849. #endif
  850. }
  851. __local_flush_dcache_page(page);
  852. preempt_enable();
  853. }
  854. #ifdef CONFIG_KGDB
  855. void kgdb_roundup_cpus(void)
  856. {
  857. smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
  858. }
  859. #endif
  860. void smp_fetch_global_regs(void)
  861. {
  862. smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
  863. }
  864. void smp_fetch_global_pmu(void)
  865. {
  866. if (tlb_type == hypervisor &&
  867. sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
  868. smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
  869. else
  870. smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
  871. }
  872. /* We know that the window frames of the user have been flushed
  873. * to the stack before we get here because all callers of us
  874. * are flush_tlb_*() routines, and these run after flush_cache_*()
  875. * which performs the flushw.
  876. *
  877. * mm->cpu_vm_mask is a bit mask of which cpus an address
  878. * space has (potentially) executed on, this is the heuristic
  879. * we use to limit cross calls.
  880. */
  881. /* This currently is only used by the hugetlb arch pre-fault
  882. * hook on UltraSPARC-III+ and later when changing the pagesize
  883. * bits of the context register for an address space.
  884. */
  885. void smp_flush_tlb_mm(struct mm_struct *mm)
  886. {
  887. u32 ctx = CTX_HWBITS(mm->context);
  888. get_cpu();
  889. smp_cross_call_masked(&xcall_flush_tlb_mm,
  890. ctx, 0, 0,
  891. mm_cpumask(mm));
  892. __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
  893. put_cpu();
  894. }
  895. struct tlb_pending_info {
  896. unsigned long ctx;
  897. unsigned long nr;
  898. unsigned long *vaddrs;
  899. };
  900. static void tlb_pending_func(void *info)
  901. {
  902. struct tlb_pending_info *t = info;
  903. __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
  904. }
  905. void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
  906. {
  907. u32 ctx = CTX_HWBITS(mm->context);
  908. struct tlb_pending_info info;
  909. get_cpu();
  910. info.ctx = ctx;
  911. info.nr = nr;
  912. info.vaddrs = vaddrs;
  913. smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
  914. &info, 1);
  915. __flush_tlb_pending(ctx, nr, vaddrs);
  916. put_cpu();
  917. }
  918. void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
  919. {
  920. unsigned long context = CTX_HWBITS(mm->context);
  921. get_cpu();
  922. smp_cross_call_masked(&xcall_flush_tlb_page,
  923. context, vaddr, 0,
  924. mm_cpumask(mm));
  925. __flush_tlb_page(context, vaddr);
  926. put_cpu();
  927. }
  928. void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
  929. {
  930. start &= PAGE_MASK;
  931. end = PAGE_ALIGN(end);
  932. if (start != end) {
  933. smp_cross_call(&xcall_flush_tlb_kernel_range,
  934. 0, start, end);
  935. __flush_tlb_kernel_range(start, end);
  936. }
  937. }
  938. /* CPU capture. */
  939. /* #define CAPTURE_DEBUG */
  940. extern unsigned long xcall_capture;
  941. static atomic_t smp_capture_depth = ATOMIC_INIT(0);
  942. static atomic_t smp_capture_registry = ATOMIC_INIT(0);
  943. static unsigned long penguins_are_doing_time;
  944. void smp_capture(void)
  945. {
  946. int result = atomic_add_return(1, &smp_capture_depth);
  947. if (result == 1) {
  948. int ncpus = num_online_cpus();
  949. #ifdef CAPTURE_DEBUG
  950. printk("CPU[%d]: Sending penguins to jail...",
  951. smp_processor_id());
  952. #endif
  953. penguins_are_doing_time = 1;
  954. atomic_inc(&smp_capture_registry);
  955. smp_cross_call(&xcall_capture, 0, 0, 0);
  956. while (atomic_read(&smp_capture_registry) != ncpus)
  957. rmb();
  958. #ifdef CAPTURE_DEBUG
  959. printk("done\n");
  960. #endif
  961. }
  962. }
  963. void smp_release(void)
  964. {
  965. if (atomic_dec_and_test(&smp_capture_depth)) {
  966. #ifdef CAPTURE_DEBUG
  967. printk("CPU[%d]: Giving pardon to "
  968. "imprisoned penguins\n",
  969. smp_processor_id());
  970. #endif
  971. penguins_are_doing_time = 0;
  972. membar_safe("#StoreLoad");
  973. atomic_dec(&smp_capture_registry);
  974. }
  975. }
  976. /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
  977. * set, so they can service tlb flush xcalls...
  978. */
  979. extern void prom_world(int);
  980. void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
  981. {
  982. clear_softint(1 << irq);
  983. preempt_disable();
  984. __asm__ __volatile__("flushw");
  985. prom_world(1);
  986. atomic_inc(&smp_capture_registry);
  987. membar_safe("#StoreLoad");
  988. while (penguins_are_doing_time)
  989. rmb();
  990. atomic_dec(&smp_capture_registry);
  991. prom_world(0);
  992. preempt_enable();
  993. }
  994. void __init smp_prepare_cpus(unsigned int max_cpus)
  995. {
  996. }
  997. void smp_prepare_boot_cpu(void)
  998. {
  999. }
  1000. void __init smp_setup_processor_id(void)
  1001. {
  1002. if (tlb_type == spitfire)
  1003. xcall_deliver_impl = spitfire_xcall_deliver;
  1004. else if (tlb_type == cheetah || tlb_type == cheetah_plus)
  1005. xcall_deliver_impl = cheetah_xcall_deliver;
  1006. else
  1007. xcall_deliver_impl = hypervisor_xcall_deliver;
  1008. }
  1009. void __init smp_fill_in_cpu_possible_map(void)
  1010. {
  1011. int possible_cpus = num_possible_cpus();
  1012. int i;
  1013. if (possible_cpus > nr_cpu_ids)
  1014. possible_cpus = nr_cpu_ids;
  1015. for (i = 0; i < possible_cpus; i++)
  1016. set_cpu_possible(i, true);
  1017. for (; i < NR_CPUS; i++)
  1018. set_cpu_possible(i, false);
  1019. }
  1020. void smp_fill_in_sib_core_maps(void)
  1021. {
  1022. unsigned int i;
  1023. for_each_present_cpu(i) {
  1024. unsigned int j;
  1025. cpumask_clear(&cpu_core_map[i]);
  1026. if (cpu_data(i).core_id == 0) {
  1027. cpumask_set_cpu(i, &cpu_core_map[i]);
  1028. continue;
  1029. }
  1030. for_each_present_cpu(j) {
  1031. if (cpu_data(i).core_id ==
  1032. cpu_data(j).core_id)
  1033. cpumask_set_cpu(j, &cpu_core_map[i]);
  1034. }
  1035. }
  1036. for_each_present_cpu(i) {
  1037. unsigned int j;
  1038. for_each_present_cpu(j) {
  1039. if (cpu_data(i).max_cache_id ==
  1040. cpu_data(j).max_cache_id)
  1041. cpumask_set_cpu(j, &cpu_core_sib_cache_map[i]);
  1042. if (cpu_data(i).sock_id == cpu_data(j).sock_id)
  1043. cpumask_set_cpu(j, &cpu_core_sib_map[i]);
  1044. }
  1045. }
  1046. for_each_present_cpu(i) {
  1047. unsigned int j;
  1048. cpumask_clear(&per_cpu(cpu_sibling_map, i));
  1049. if (cpu_data(i).proc_id == -1) {
  1050. cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
  1051. continue;
  1052. }
  1053. for_each_present_cpu(j) {
  1054. if (cpu_data(i).proc_id ==
  1055. cpu_data(j).proc_id)
  1056. cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
  1057. }
  1058. }
  1059. }
  1060. int __cpu_up(unsigned int cpu, struct task_struct *tidle)
  1061. {
  1062. int ret = smp_boot_one_cpu(cpu, tidle);
  1063. if (!ret) {
  1064. cpumask_set_cpu(cpu, &smp_commenced_mask);
  1065. while (!cpu_online(cpu))
  1066. mb();
  1067. if (!cpu_online(cpu)) {
  1068. ret = -ENODEV;
  1069. } else {
  1070. /* On SUN4V, writes to %tick and %stick are
  1071. * not allowed.
  1072. */
  1073. if (tlb_type != hypervisor)
  1074. smp_synchronize_one_tick(cpu);
  1075. }
  1076. }
  1077. return ret;
  1078. }
  1079. #ifdef CONFIG_HOTPLUG_CPU
  1080. void cpu_play_dead(void)
  1081. {
  1082. int cpu = smp_processor_id();
  1083. unsigned long pstate;
  1084. idle_task_exit();
  1085. if (tlb_type == hypervisor) {
  1086. struct trap_per_cpu *tb = &trap_block[cpu];
  1087. sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
  1088. tb->cpu_mondo_pa, 0);
  1089. sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
  1090. tb->dev_mondo_pa, 0);
  1091. sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
  1092. tb->resum_mondo_pa, 0);
  1093. sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
  1094. tb->nonresum_mondo_pa, 0);
  1095. }
  1096. cpumask_clear_cpu(cpu, &smp_commenced_mask);
  1097. membar_safe("#Sync");
  1098. local_irq_disable();
  1099. __asm__ __volatile__(
  1100. "rdpr %%pstate, %0\n\t"
  1101. "wrpr %0, %1, %%pstate"
  1102. : "=r" (pstate)
  1103. : "i" (PSTATE_IE));
  1104. while (1)
  1105. barrier();
  1106. }
  1107. int __cpu_disable(void)
  1108. {
  1109. int cpu = smp_processor_id();
  1110. cpuinfo_sparc *c;
  1111. int i;
  1112. for_each_cpu(i, &cpu_core_map[cpu])
  1113. cpumask_clear_cpu(cpu, &cpu_core_map[i]);
  1114. cpumask_clear(&cpu_core_map[cpu]);
  1115. for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
  1116. cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
  1117. cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
  1118. c = &cpu_data(cpu);
  1119. c->core_id = 0;
  1120. c->proc_id = -1;
  1121. smp_wmb();
  1122. /* Make sure no interrupts point to this cpu. */
  1123. fixup_irqs();
  1124. local_irq_enable();
  1125. mdelay(1);
  1126. local_irq_disable();
  1127. set_cpu_online(cpu, false);
  1128. cpu_map_rebuild();
  1129. return 0;
  1130. }
  1131. void __cpu_die(unsigned int cpu)
  1132. {
  1133. int i;
  1134. for (i = 0; i < 100; i++) {
  1135. smp_rmb();
  1136. if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
  1137. break;
  1138. msleep(100);
  1139. }
  1140. if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
  1141. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  1142. } else {
  1143. #if defined(CONFIG_SUN_LDOMS)
  1144. unsigned long hv_err;
  1145. int limit = 100;
  1146. do {
  1147. hv_err = sun4v_cpu_stop(cpu);
  1148. if (hv_err == HV_EOK) {
  1149. set_cpu_present(cpu, false);
  1150. break;
  1151. }
  1152. } while (--limit > 0);
  1153. if (limit <= 0) {
  1154. printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
  1155. hv_err);
  1156. }
  1157. #endif
  1158. }
  1159. }
  1160. #endif
  1161. void __init smp_cpus_done(unsigned int max_cpus)
  1162. {
  1163. }
  1164. static void send_cpu_ipi(int cpu)
  1165. {
  1166. xcall_deliver((u64) &xcall_receive_signal,
  1167. 0, 0, cpumask_of(cpu));
  1168. }
  1169. void scheduler_poke(void)
  1170. {
  1171. if (!cpu_poke)
  1172. return;
  1173. if (!__this_cpu_read(poke))
  1174. return;
  1175. __this_cpu_write(poke, false);
  1176. set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
  1177. }
  1178. static unsigned long send_cpu_poke(int cpu)
  1179. {
  1180. unsigned long hv_err;
  1181. per_cpu(poke, cpu) = true;
  1182. hv_err = sun4v_cpu_poke(cpu);
  1183. if (hv_err != HV_EOK) {
  1184. per_cpu(poke, cpu) = false;
  1185. pr_err_ratelimited("%s: sun4v_cpu_poke() fails err=%lu\n",
  1186. __func__, hv_err);
  1187. }
  1188. return hv_err;
  1189. }
  1190. void smp_send_reschedule(int cpu)
  1191. {
  1192. if (cpu == smp_processor_id()) {
  1193. WARN_ON_ONCE(preemptible());
  1194. set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
  1195. return;
  1196. }
  1197. /* Use cpu poke to resume idle cpu if supported. */
  1198. if (cpu_poke && idle_cpu(cpu)) {
  1199. unsigned long ret;
  1200. ret = send_cpu_poke(cpu);
  1201. if (ret == HV_EOK)
  1202. return;
  1203. }
  1204. /* Use IPI in following cases:
  1205. * - cpu poke not supported
  1206. * - cpu not idle
  1207. * - send_cpu_poke() returns with error
  1208. */
  1209. send_cpu_ipi(cpu);
  1210. }
  1211. void smp_init_cpu_poke(void)
  1212. {
  1213. unsigned long major;
  1214. unsigned long minor;
  1215. int ret;
  1216. if (tlb_type != hypervisor)
  1217. return;
  1218. ret = sun4v_hvapi_get(HV_GRP_CORE, &major, &minor);
  1219. if (ret) {
  1220. pr_debug("HV_GRP_CORE is not registered\n");
  1221. return;
  1222. }
  1223. if (major == 1 && minor >= 6) {
  1224. /* CPU POKE is registered. */
  1225. cpu_poke = true;
  1226. return;
  1227. }
  1228. pr_debug("CPU_POKE not supported\n");
  1229. }
  1230. void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
  1231. {
  1232. clear_softint(1 << irq);
  1233. scheduler_ipi();
  1234. }
  1235. static void stop_this_cpu(void *dummy)
  1236. {
  1237. set_cpu_online(smp_processor_id(), false);
  1238. prom_stopself();
  1239. }
  1240. void smp_send_stop(void)
  1241. {
  1242. int cpu;
  1243. if (tlb_type == hypervisor) {
  1244. int this_cpu = smp_processor_id();
  1245. #ifdef CONFIG_SERIAL_SUNHV
  1246. sunhv_migrate_hvcons_irq(this_cpu);
  1247. #endif
  1248. for_each_online_cpu(cpu) {
  1249. if (cpu == this_cpu)
  1250. continue;
  1251. set_cpu_online(cpu, false);
  1252. #ifdef CONFIG_SUN_LDOMS
  1253. if (ldom_domaining_enabled) {
  1254. unsigned long hv_err;
  1255. hv_err = sun4v_cpu_stop(cpu);
  1256. if (hv_err)
  1257. printk(KERN_ERR "sun4v_cpu_stop() "
  1258. "failed err=%lu\n", hv_err);
  1259. } else
  1260. #endif
  1261. prom_stopcpu_cpuid(cpu);
  1262. }
  1263. } else
  1264. smp_call_function(stop_this_cpu, NULL, 0);
  1265. }
  1266. static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
  1267. {
  1268. if (cpu_to_node(from) == cpu_to_node(to))
  1269. return LOCAL_DISTANCE;
  1270. else
  1271. return REMOTE_DISTANCE;
  1272. }
  1273. static int __init pcpu_cpu_to_node(int cpu)
  1274. {
  1275. return cpu_to_node(cpu);
  1276. }
  1277. void __init setup_per_cpu_areas(void)
  1278. {
  1279. unsigned long delta;
  1280. unsigned int cpu;
  1281. int rc = -EINVAL;
  1282. if (pcpu_chosen_fc != PCPU_FC_PAGE) {
  1283. rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
  1284. PERCPU_DYNAMIC_RESERVE, 4 << 20,
  1285. pcpu_cpu_distance,
  1286. pcpu_cpu_to_node);
  1287. if (rc)
  1288. pr_warn("PERCPU: %s allocator failed (%d), "
  1289. "falling back to page size\n",
  1290. pcpu_fc_names[pcpu_chosen_fc], rc);
  1291. }
  1292. if (rc < 0)
  1293. rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
  1294. pcpu_cpu_to_node);
  1295. if (rc < 0)
  1296. panic("cannot initialize percpu area (err=%d)", rc);
  1297. delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
  1298. for_each_possible_cpu(cpu)
  1299. __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
  1300. /* Setup %g5 for the boot cpu. */
  1301. __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
  1302. of_fill_in_cpu_data();
  1303. if (tlb_type == hypervisor)
  1304. mdesc_fill_in_cpu_data(cpu_all_mask);
  1305. }