irq_64.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* irq.c: UltraSparc IRQ handling/init/registry.
  3. *
  4. * Copyright (C) 1997, 2007, 2008 David S. Miller ([email protected])
  5. * Copyright (C) 1998 Eddie C. Dost ([email protected])
  6. * Copyright (C) 1998 Jakub Jelinek ([email protected])
  7. */
  8. #include <linux/sched.h>
  9. #include <linux/linkage.h>
  10. #include <linux/ptrace.h>
  11. #include <linux/errno.h>
  12. #include <linux/kernel_stat.h>
  13. #include <linux/signal.h>
  14. #include <linux/mm.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/slab.h>
  17. #include <linux/random.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include <linux/proc_fs.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/ftrace.h>
  23. #include <linux/irq.h>
  24. #include <asm/ptrace.h>
  25. #include <asm/processor.h>
  26. #include <linux/atomic.h>
  27. #include <asm/irq.h>
  28. #include <asm/io.h>
  29. #include <asm/iommu.h>
  30. #include <asm/upa.h>
  31. #include <asm/oplib.h>
  32. #include <asm/prom.h>
  33. #include <asm/timer.h>
  34. #include <asm/smp.h>
  35. #include <asm/starfire.h>
  36. #include <linux/uaccess.h>
  37. #include <asm/cache.h>
  38. #include <asm/cpudata.h>
  39. #include <asm/auxio.h>
  40. #include <asm/head.h>
  41. #include <asm/hypervisor.h>
  42. #include <asm/cacheflush.h>
  43. #include <asm/softirq_stack.h>
  44. #include "entry.h"
  45. #include "cpumap.h"
  46. #include "kstack.h"
  47. struct ino_bucket *ivector_table;
  48. unsigned long ivector_table_pa;
  49. /* On several sun4u processors, it is illegal to mix bypass and
  50. * non-bypass accesses. Therefore we access all INO buckets
  51. * using bypass accesses only.
  52. */
  53. static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  54. {
  55. unsigned long ret;
  56. __asm__ __volatile__("ldxa [%1] %2, %0"
  57. : "=&r" (ret)
  58. : "r" (bucket_pa +
  59. offsetof(struct ino_bucket,
  60. __irq_chain_pa)),
  61. "i" (ASI_PHYS_USE_EC));
  62. return ret;
  63. }
  64. static void bucket_clear_chain_pa(unsigned long bucket_pa)
  65. {
  66. __asm__ __volatile__("stxa %%g0, [%0] %1"
  67. : /* no outputs */
  68. : "r" (bucket_pa +
  69. offsetof(struct ino_bucket,
  70. __irq_chain_pa)),
  71. "i" (ASI_PHYS_USE_EC));
  72. }
  73. static unsigned int bucket_get_irq(unsigned long bucket_pa)
  74. {
  75. unsigned int ret;
  76. __asm__ __volatile__("lduwa [%1] %2, %0"
  77. : "=&r" (ret)
  78. : "r" (bucket_pa +
  79. offsetof(struct ino_bucket,
  80. __irq)),
  81. "i" (ASI_PHYS_USE_EC));
  82. return ret;
  83. }
  84. static void bucket_set_irq(unsigned long bucket_pa, unsigned int irq)
  85. {
  86. __asm__ __volatile__("stwa %0, [%1] %2"
  87. : /* no outputs */
  88. : "r" (irq),
  89. "r" (bucket_pa +
  90. offsetof(struct ino_bucket,
  91. __irq)),
  92. "i" (ASI_PHYS_USE_EC));
  93. }
  94. #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa)
  95. static unsigned long hvirq_major __initdata;
  96. static int __init early_hvirq_major(char *p)
  97. {
  98. int rc = kstrtoul(p, 10, &hvirq_major);
  99. return rc;
  100. }
  101. early_param("hvirq", early_hvirq_major);
  102. static int hv_irq_version;
  103. /* Major version 2.0 of HV_GRP_INTR added support for the VIRQ cookie
  104. * based interfaces, but:
  105. *
  106. * 1) Several OSs, Solaris and Linux included, use them even when only
  107. * negotiating version 1.0 (or failing to negotiate at all). So the
  108. * hypervisor has a workaround that provides the VIRQ interfaces even
  109. * when only verion 1.0 of the API is in use.
  110. *
  111. * 2) Second, and more importantly, with major version 2.0 these VIRQ
  112. * interfaces only were actually hooked up for LDC interrupts, even
  113. * though the Hypervisor specification clearly stated:
  114. *
  115. * The new interrupt API functions will be available to a guest
  116. * when it negotiates version 2.0 in the interrupt API group 0x2. When
  117. * a guest negotiates version 2.0, all interrupt sources will only
  118. * support using the cookie interface, and any attempt to use the
  119. * version 1.0 interrupt APIs numbered 0xa0 to 0xa6 will result in the
  120. * ENOTSUPPORTED error being returned.
  121. *
  122. * with an emphasis on "all interrupt sources".
  123. *
  124. * To correct this, major version 3.0 was created which does actually
  125. * support VIRQs for all interrupt sources (not just LDC devices). So
  126. * if we want to move completely over the cookie based VIRQs we must
  127. * negotiate major version 3.0 or later of HV_GRP_INTR.
  128. */
  129. static bool sun4v_cookie_only_virqs(void)
  130. {
  131. if (hv_irq_version >= 3)
  132. return true;
  133. return false;
  134. }
  135. static void __init irq_init_hv(void)
  136. {
  137. unsigned long hv_error, major, minor = 0;
  138. if (tlb_type != hypervisor)
  139. return;
  140. if (hvirq_major)
  141. major = hvirq_major;
  142. else
  143. major = 3;
  144. hv_error = sun4v_hvapi_register(HV_GRP_INTR, major, &minor);
  145. if (!hv_error)
  146. hv_irq_version = major;
  147. else
  148. hv_irq_version = 1;
  149. pr_info("SUN4V: Using IRQ API major %d, cookie only virqs %s\n",
  150. hv_irq_version,
  151. sun4v_cookie_only_virqs() ? "enabled" : "disabled");
  152. }
  153. /* This function is for the timer interrupt.*/
  154. int __init arch_probe_nr_irqs(void)
  155. {
  156. return 1;
  157. }
  158. #define DEFAULT_NUM_IVECS (0xfffU)
  159. static unsigned int nr_ivec = DEFAULT_NUM_IVECS;
  160. #define NUM_IVECS (nr_ivec)
  161. static unsigned int __init size_nr_ivec(void)
  162. {
  163. if (tlb_type == hypervisor) {
  164. switch (sun4v_chip_type) {
  165. /* Athena's devhandle|devino is large.*/
  166. case SUN4V_CHIP_SPARC64X:
  167. nr_ivec = 0xffff;
  168. break;
  169. }
  170. }
  171. return nr_ivec;
  172. }
  173. struct irq_handler_data {
  174. union {
  175. struct {
  176. unsigned int dev_handle;
  177. unsigned int dev_ino;
  178. };
  179. unsigned long sysino;
  180. };
  181. struct ino_bucket bucket;
  182. unsigned long iclr;
  183. unsigned long imap;
  184. };
  185. static inline unsigned int irq_data_to_handle(struct irq_data *data)
  186. {
  187. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  188. return ihd->dev_handle;
  189. }
  190. static inline unsigned int irq_data_to_ino(struct irq_data *data)
  191. {
  192. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  193. return ihd->dev_ino;
  194. }
  195. static inline unsigned long irq_data_to_sysino(struct irq_data *data)
  196. {
  197. struct irq_handler_data *ihd = irq_data_get_irq_handler_data(data);
  198. return ihd->sysino;
  199. }
  200. void irq_free(unsigned int irq)
  201. {
  202. void *data = irq_get_handler_data(irq);
  203. kfree(data);
  204. irq_set_handler_data(irq, NULL);
  205. irq_free_descs(irq, 1);
  206. }
  207. unsigned int irq_alloc(unsigned int dev_handle, unsigned int dev_ino)
  208. {
  209. int irq;
  210. irq = __irq_alloc_descs(-1, 1, 1, numa_node_id(), NULL, NULL);
  211. if (irq <= 0)
  212. goto out;
  213. return irq;
  214. out:
  215. return 0;
  216. }
  217. static unsigned int cookie_exists(u32 devhandle, unsigned int devino)
  218. {
  219. unsigned long hv_err, cookie;
  220. struct ino_bucket *bucket;
  221. unsigned int irq = 0U;
  222. hv_err = sun4v_vintr_get_cookie(devhandle, devino, &cookie);
  223. if (hv_err) {
  224. pr_err("HV get cookie failed hv_err = %ld\n", hv_err);
  225. goto out;
  226. }
  227. if (cookie & ((1UL << 63UL))) {
  228. cookie = ~cookie;
  229. bucket = (struct ino_bucket *) __va(cookie);
  230. irq = bucket->__irq;
  231. }
  232. out:
  233. return irq;
  234. }
  235. static unsigned int sysino_exists(u32 devhandle, unsigned int devino)
  236. {
  237. unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
  238. struct ino_bucket *bucket;
  239. unsigned int irq;
  240. bucket = &ivector_table[sysino];
  241. irq = bucket_get_irq(__pa(bucket));
  242. return irq;
  243. }
  244. void ack_bad_irq(unsigned int irq)
  245. {
  246. pr_crit("BAD IRQ ack %d\n", irq);
  247. }
  248. void irq_install_pre_handler(int irq,
  249. void (*func)(unsigned int, void *, void *),
  250. void *arg1, void *arg2)
  251. {
  252. pr_warn("IRQ pre handler NOT supported.\n");
  253. }
  254. /*
  255. * /proc/interrupts printing:
  256. */
  257. int arch_show_interrupts(struct seq_file *p, int prec)
  258. {
  259. int j;
  260. seq_printf(p, "NMI: ");
  261. for_each_online_cpu(j)
  262. seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
  263. seq_printf(p, " Non-maskable interrupts\n");
  264. return 0;
  265. }
  266. static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
  267. {
  268. unsigned int tid;
  269. if (this_is_starfire) {
  270. tid = starfire_translate(imap, cpuid);
  271. tid <<= IMAP_TID_SHIFT;
  272. tid &= IMAP_TID_UPA;
  273. } else {
  274. if (tlb_type == cheetah || tlb_type == cheetah_plus) {
  275. unsigned long ver;
  276. __asm__ ("rdpr %%ver, %0" : "=r" (ver));
  277. if ((ver >> 32UL) == __JALAPENO_ID ||
  278. (ver >> 32UL) == __SERRANO_ID) {
  279. tid = cpuid << IMAP_TID_SHIFT;
  280. tid &= IMAP_TID_JBUS;
  281. } else {
  282. unsigned int a = cpuid & 0x1f;
  283. unsigned int n = (cpuid >> 5) & 0x1f;
  284. tid = ((a << IMAP_AID_SHIFT) |
  285. (n << IMAP_NID_SHIFT));
  286. tid &= (IMAP_AID_SAFARI |
  287. IMAP_NID_SAFARI);
  288. }
  289. } else {
  290. tid = cpuid << IMAP_TID_SHIFT;
  291. tid &= IMAP_TID_UPA;
  292. }
  293. }
  294. return tid;
  295. }
  296. #ifdef CONFIG_SMP
  297. static int irq_choose_cpu(unsigned int irq, const struct cpumask *affinity)
  298. {
  299. cpumask_t mask;
  300. int cpuid;
  301. cpumask_copy(&mask, affinity);
  302. if (cpumask_equal(&mask, cpu_online_mask)) {
  303. cpuid = map_to_cpu(irq);
  304. } else {
  305. cpumask_t tmp;
  306. cpumask_and(&tmp, cpu_online_mask, &mask);
  307. cpuid = cpumask_empty(&tmp) ? map_to_cpu(irq) : cpumask_first(&tmp);
  308. }
  309. return cpuid;
  310. }
  311. #else
  312. #define irq_choose_cpu(irq, affinity) \
  313. real_hard_smp_processor_id()
  314. #endif
  315. static void sun4u_irq_enable(struct irq_data *data)
  316. {
  317. struct irq_handler_data *handler_data;
  318. handler_data = irq_data_get_irq_handler_data(data);
  319. if (likely(handler_data)) {
  320. unsigned long cpuid, imap, val;
  321. unsigned int tid;
  322. cpuid = irq_choose_cpu(data->irq,
  323. irq_data_get_affinity_mask(data));
  324. imap = handler_data->imap;
  325. tid = sun4u_compute_tid(imap, cpuid);
  326. val = upa_readq(imap);
  327. val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
  328. IMAP_AID_SAFARI | IMAP_NID_SAFARI);
  329. val |= tid | IMAP_VALID;
  330. upa_writeq(val, imap);
  331. upa_writeq(ICLR_IDLE, handler_data->iclr);
  332. }
  333. }
  334. static int sun4u_set_affinity(struct irq_data *data,
  335. const struct cpumask *mask, bool force)
  336. {
  337. struct irq_handler_data *handler_data;
  338. handler_data = irq_data_get_irq_handler_data(data);
  339. if (likely(handler_data)) {
  340. unsigned long cpuid, imap, val;
  341. unsigned int tid;
  342. cpuid = irq_choose_cpu(data->irq, mask);
  343. imap = handler_data->imap;
  344. tid = sun4u_compute_tid(imap, cpuid);
  345. val = upa_readq(imap);
  346. val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
  347. IMAP_AID_SAFARI | IMAP_NID_SAFARI);
  348. val |= tid | IMAP_VALID;
  349. upa_writeq(val, imap);
  350. upa_writeq(ICLR_IDLE, handler_data->iclr);
  351. }
  352. return 0;
  353. }
  354. /* Don't do anything. The desc->status check for IRQ_DISABLED in
  355. * handler_irq() will skip the handler call and that will leave the
  356. * interrupt in the sent state. The next ->enable() call will hit the
  357. * ICLR register to reset the state machine.
  358. *
  359. * This scheme is necessary, instead of clearing the Valid bit in the
  360. * IMAP register, to handle the case of IMAP registers being shared by
  361. * multiple INOs (and thus ICLR registers). Since we use a different
  362. * virtual IRQ for each shared IMAP instance, the generic code thinks
  363. * there is only one user so it prematurely calls ->disable() on
  364. * free_irq().
  365. *
  366. * We have to provide an explicit ->disable() method instead of using
  367. * NULL to get the default. The reason is that if the generic code
  368. * sees that, it also hooks up a default ->shutdown method which
  369. * invokes ->mask() which we do not want. See irq_chip_set_defaults().
  370. */
  371. static void sun4u_irq_disable(struct irq_data *data)
  372. {
  373. }
  374. static void sun4u_irq_eoi(struct irq_data *data)
  375. {
  376. struct irq_handler_data *handler_data;
  377. handler_data = irq_data_get_irq_handler_data(data);
  378. if (likely(handler_data))
  379. upa_writeq(ICLR_IDLE, handler_data->iclr);
  380. }
  381. static void sun4v_irq_enable(struct irq_data *data)
  382. {
  383. unsigned long cpuid = irq_choose_cpu(data->irq,
  384. irq_data_get_affinity_mask(data));
  385. unsigned int ino = irq_data_to_sysino(data);
  386. int err;
  387. err = sun4v_intr_settarget(ino, cpuid);
  388. if (err != HV_EOK)
  389. printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
  390. "err(%d)\n", ino, cpuid, err);
  391. err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
  392. if (err != HV_EOK)
  393. printk(KERN_ERR "sun4v_intr_setstate(%x): "
  394. "err(%d)\n", ino, err);
  395. err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
  396. if (err != HV_EOK)
  397. printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
  398. ino, err);
  399. }
  400. static int sun4v_set_affinity(struct irq_data *data,
  401. const struct cpumask *mask, bool force)
  402. {
  403. unsigned long cpuid = irq_choose_cpu(data->irq, mask);
  404. unsigned int ino = irq_data_to_sysino(data);
  405. int err;
  406. err = sun4v_intr_settarget(ino, cpuid);
  407. if (err != HV_EOK)
  408. printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
  409. "err(%d)\n", ino, cpuid, err);
  410. return 0;
  411. }
  412. static void sun4v_irq_disable(struct irq_data *data)
  413. {
  414. unsigned int ino = irq_data_to_sysino(data);
  415. int err;
  416. err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
  417. if (err != HV_EOK)
  418. printk(KERN_ERR "sun4v_intr_setenabled(%x): "
  419. "err(%d)\n", ino, err);
  420. }
  421. static void sun4v_irq_eoi(struct irq_data *data)
  422. {
  423. unsigned int ino = irq_data_to_sysino(data);
  424. int err;
  425. err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
  426. if (err != HV_EOK)
  427. printk(KERN_ERR "sun4v_intr_setstate(%x): "
  428. "err(%d)\n", ino, err);
  429. }
  430. static void sun4v_virq_enable(struct irq_data *data)
  431. {
  432. unsigned long dev_handle = irq_data_to_handle(data);
  433. unsigned long dev_ino = irq_data_to_ino(data);
  434. unsigned long cpuid;
  435. int err;
  436. cpuid = irq_choose_cpu(data->irq, irq_data_get_affinity_mask(data));
  437. err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
  438. if (err != HV_EOK)
  439. printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
  440. "err(%d)\n",
  441. dev_handle, dev_ino, cpuid, err);
  442. err = sun4v_vintr_set_state(dev_handle, dev_ino,
  443. HV_INTR_STATE_IDLE);
  444. if (err != HV_EOK)
  445. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  446. "HV_INTR_STATE_IDLE): err(%d)\n",
  447. dev_handle, dev_ino, err);
  448. err = sun4v_vintr_set_valid(dev_handle, dev_ino,
  449. HV_INTR_ENABLED);
  450. if (err != HV_EOK)
  451. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  452. "HV_INTR_ENABLED): err(%d)\n",
  453. dev_handle, dev_ino, err);
  454. }
  455. static int sun4v_virt_set_affinity(struct irq_data *data,
  456. const struct cpumask *mask, bool force)
  457. {
  458. unsigned long dev_handle = irq_data_to_handle(data);
  459. unsigned long dev_ino = irq_data_to_ino(data);
  460. unsigned long cpuid;
  461. int err;
  462. cpuid = irq_choose_cpu(data->irq, mask);
  463. err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
  464. if (err != HV_EOK)
  465. printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
  466. "err(%d)\n",
  467. dev_handle, dev_ino, cpuid, err);
  468. return 0;
  469. }
  470. static void sun4v_virq_disable(struct irq_data *data)
  471. {
  472. unsigned long dev_handle = irq_data_to_handle(data);
  473. unsigned long dev_ino = irq_data_to_ino(data);
  474. int err;
  475. err = sun4v_vintr_set_valid(dev_handle, dev_ino,
  476. HV_INTR_DISABLED);
  477. if (err != HV_EOK)
  478. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  479. "HV_INTR_DISABLED): err(%d)\n",
  480. dev_handle, dev_ino, err);
  481. }
  482. static void sun4v_virq_eoi(struct irq_data *data)
  483. {
  484. unsigned long dev_handle = irq_data_to_handle(data);
  485. unsigned long dev_ino = irq_data_to_ino(data);
  486. int err;
  487. err = sun4v_vintr_set_state(dev_handle, dev_ino,
  488. HV_INTR_STATE_IDLE);
  489. if (err != HV_EOK)
  490. printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
  491. "HV_INTR_STATE_IDLE): err(%d)\n",
  492. dev_handle, dev_ino, err);
  493. }
  494. static struct irq_chip sun4u_irq = {
  495. .name = "sun4u",
  496. .irq_enable = sun4u_irq_enable,
  497. .irq_disable = sun4u_irq_disable,
  498. .irq_eoi = sun4u_irq_eoi,
  499. .irq_set_affinity = sun4u_set_affinity,
  500. .flags = IRQCHIP_EOI_IF_HANDLED,
  501. };
  502. static struct irq_chip sun4v_irq = {
  503. .name = "sun4v",
  504. .irq_enable = sun4v_irq_enable,
  505. .irq_disable = sun4v_irq_disable,
  506. .irq_eoi = sun4v_irq_eoi,
  507. .irq_set_affinity = sun4v_set_affinity,
  508. .flags = IRQCHIP_EOI_IF_HANDLED,
  509. };
  510. static struct irq_chip sun4v_virq = {
  511. .name = "vsun4v",
  512. .irq_enable = sun4v_virq_enable,
  513. .irq_disable = sun4v_virq_disable,
  514. .irq_eoi = sun4v_virq_eoi,
  515. .irq_set_affinity = sun4v_virt_set_affinity,
  516. .flags = IRQCHIP_EOI_IF_HANDLED,
  517. };
  518. unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
  519. {
  520. struct irq_handler_data *handler_data;
  521. struct ino_bucket *bucket;
  522. unsigned int irq;
  523. int ino;
  524. BUG_ON(tlb_type == hypervisor);
  525. ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
  526. bucket = &ivector_table[ino];
  527. irq = bucket_get_irq(__pa(bucket));
  528. if (!irq) {
  529. irq = irq_alloc(0, ino);
  530. bucket_set_irq(__pa(bucket), irq);
  531. irq_set_chip_and_handler_name(irq, &sun4u_irq,
  532. handle_fasteoi_irq, "IVEC");
  533. }
  534. handler_data = irq_get_handler_data(irq);
  535. if (unlikely(handler_data))
  536. goto out;
  537. handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  538. if (unlikely(!handler_data)) {
  539. prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
  540. prom_halt();
  541. }
  542. irq_set_handler_data(irq, handler_data);
  543. handler_data->imap = imap;
  544. handler_data->iclr = iclr;
  545. out:
  546. return irq;
  547. }
  548. static unsigned int sun4v_build_common(u32 devhandle, unsigned int devino,
  549. void (*handler_data_init)(struct irq_handler_data *data,
  550. u32 devhandle, unsigned int devino),
  551. struct irq_chip *chip)
  552. {
  553. struct irq_handler_data *data;
  554. unsigned int irq;
  555. irq = irq_alloc(devhandle, devino);
  556. if (!irq)
  557. goto out;
  558. data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
  559. if (unlikely(!data)) {
  560. pr_err("IRQ handler data allocation failed.\n");
  561. irq_free(irq);
  562. irq = 0;
  563. goto out;
  564. }
  565. irq_set_handler_data(irq, data);
  566. handler_data_init(data, devhandle, devino);
  567. irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq, "IVEC");
  568. data->imap = ~0UL;
  569. data->iclr = ~0UL;
  570. out:
  571. return irq;
  572. }
  573. static unsigned long cookie_assign(unsigned int irq, u32 devhandle,
  574. unsigned int devino)
  575. {
  576. struct irq_handler_data *ihd = irq_get_handler_data(irq);
  577. unsigned long hv_error, cookie;
  578. /* handler_irq needs to find the irq. cookie is seen signed in
  579. * sun4v_dev_mondo and treated as a non ivector_table delivery.
  580. */
  581. ihd->bucket.__irq = irq;
  582. cookie = ~__pa(&ihd->bucket);
  583. hv_error = sun4v_vintr_set_cookie(devhandle, devino, cookie);
  584. if (hv_error)
  585. pr_err("HV vintr set cookie failed = %ld\n", hv_error);
  586. return hv_error;
  587. }
  588. static void cookie_handler_data(struct irq_handler_data *data,
  589. u32 devhandle, unsigned int devino)
  590. {
  591. data->dev_handle = devhandle;
  592. data->dev_ino = devino;
  593. }
  594. static unsigned int cookie_build_irq(u32 devhandle, unsigned int devino,
  595. struct irq_chip *chip)
  596. {
  597. unsigned long hv_error;
  598. unsigned int irq;
  599. irq = sun4v_build_common(devhandle, devino, cookie_handler_data, chip);
  600. hv_error = cookie_assign(irq, devhandle, devino);
  601. if (hv_error) {
  602. irq_free(irq);
  603. irq = 0;
  604. }
  605. return irq;
  606. }
  607. static unsigned int sun4v_build_cookie(u32 devhandle, unsigned int devino)
  608. {
  609. unsigned int irq;
  610. irq = cookie_exists(devhandle, devino);
  611. if (irq)
  612. goto out;
  613. irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
  614. out:
  615. return irq;
  616. }
  617. static void sysino_set_bucket(unsigned int irq)
  618. {
  619. struct irq_handler_data *ihd = irq_get_handler_data(irq);
  620. struct ino_bucket *bucket;
  621. unsigned long sysino;
  622. sysino = sun4v_devino_to_sysino(ihd->dev_handle, ihd->dev_ino);
  623. BUG_ON(sysino >= nr_ivec);
  624. bucket = &ivector_table[sysino];
  625. bucket_set_irq(__pa(bucket), irq);
  626. }
  627. static void sysino_handler_data(struct irq_handler_data *data,
  628. u32 devhandle, unsigned int devino)
  629. {
  630. unsigned long sysino;
  631. sysino = sun4v_devino_to_sysino(devhandle, devino);
  632. data->sysino = sysino;
  633. }
  634. static unsigned int sysino_build_irq(u32 devhandle, unsigned int devino,
  635. struct irq_chip *chip)
  636. {
  637. unsigned int irq;
  638. irq = sun4v_build_common(devhandle, devino, sysino_handler_data, chip);
  639. if (!irq)
  640. goto out;
  641. sysino_set_bucket(irq);
  642. out:
  643. return irq;
  644. }
  645. static int sun4v_build_sysino(u32 devhandle, unsigned int devino)
  646. {
  647. int irq;
  648. irq = sysino_exists(devhandle, devino);
  649. if (irq)
  650. goto out;
  651. irq = sysino_build_irq(devhandle, devino, &sun4v_irq);
  652. out:
  653. return irq;
  654. }
  655. unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
  656. {
  657. unsigned int irq;
  658. if (sun4v_cookie_only_virqs())
  659. irq = sun4v_build_cookie(devhandle, devino);
  660. else
  661. irq = sun4v_build_sysino(devhandle, devino);
  662. return irq;
  663. }
  664. unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
  665. {
  666. int irq;
  667. irq = cookie_build_irq(devhandle, devino, &sun4v_virq);
  668. if (!irq)
  669. goto out;
  670. /* This is borrowed from the original function.
  671. */
  672. irq_set_status_flags(irq, IRQ_NOAUTOEN);
  673. out:
  674. return irq;
  675. }
  676. void *hardirq_stack[NR_CPUS];
  677. void *softirq_stack[NR_CPUS];
  678. void __irq_entry handler_irq(int pil, struct pt_regs *regs)
  679. {
  680. unsigned long pstate, bucket_pa;
  681. struct pt_regs *old_regs;
  682. void *orig_sp;
  683. clear_softint(1 << pil);
  684. old_regs = set_irq_regs(regs);
  685. irq_enter();
  686. /* Grab an atomic snapshot of the pending IVECs. */
  687. __asm__ __volatile__("rdpr %%pstate, %0\n\t"
  688. "wrpr %0, %3, %%pstate\n\t"
  689. "ldx [%2], %1\n\t"
  690. "stx %%g0, [%2]\n\t"
  691. "wrpr %0, 0x0, %%pstate\n\t"
  692. : "=&r" (pstate), "=&r" (bucket_pa)
  693. : "r" (irq_work_pa(smp_processor_id())),
  694. "i" (PSTATE_IE)
  695. : "memory");
  696. orig_sp = set_hardirq_stack();
  697. while (bucket_pa) {
  698. unsigned long next_pa;
  699. unsigned int irq;
  700. next_pa = bucket_get_chain_pa(bucket_pa);
  701. irq = bucket_get_irq(bucket_pa);
  702. bucket_clear_chain_pa(bucket_pa);
  703. generic_handle_irq(irq);
  704. bucket_pa = next_pa;
  705. }
  706. restore_hardirq_stack(orig_sp);
  707. irq_exit();
  708. set_irq_regs(old_regs);
  709. }
  710. #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
  711. void do_softirq_own_stack(void)
  712. {
  713. void *orig_sp, *sp = softirq_stack[smp_processor_id()];
  714. sp += THREAD_SIZE - 192 - STACK_BIAS;
  715. __asm__ __volatile__("mov %%sp, %0\n\t"
  716. "mov %1, %%sp"
  717. : "=&r" (orig_sp)
  718. : "r" (sp));
  719. __do_softirq();
  720. __asm__ __volatile__("mov %0, %%sp"
  721. : : "r" (orig_sp));
  722. }
  723. #endif
  724. #ifdef CONFIG_HOTPLUG_CPU
  725. void fixup_irqs(void)
  726. {
  727. unsigned int irq;
  728. for (irq = 0; irq < NR_IRQS; irq++) {
  729. struct irq_desc *desc = irq_to_desc(irq);
  730. struct irq_data *data;
  731. unsigned long flags;
  732. if (!desc)
  733. continue;
  734. data = irq_desc_get_irq_data(desc);
  735. raw_spin_lock_irqsave(&desc->lock, flags);
  736. if (desc->action && !irqd_is_per_cpu(data)) {
  737. if (data->chip->irq_set_affinity)
  738. data->chip->irq_set_affinity(data,
  739. irq_data_get_affinity_mask(data),
  740. false);
  741. }
  742. raw_spin_unlock_irqrestore(&desc->lock, flags);
  743. }
  744. tick_ops->disable_irq();
  745. }
  746. #endif
  747. struct sun5_timer {
  748. u64 count0;
  749. u64 limit0;
  750. u64 count1;
  751. u64 limit1;
  752. };
  753. static struct sun5_timer *prom_timers;
  754. static u64 prom_limit0, prom_limit1;
  755. static void map_prom_timers(void)
  756. {
  757. struct device_node *dp;
  758. const unsigned int *addr;
  759. /* PROM timer node hangs out in the top level of device siblings... */
  760. dp = of_find_node_by_path("/");
  761. dp = dp->child;
  762. while (dp) {
  763. if (of_node_name_eq(dp, "counter-timer"))
  764. break;
  765. dp = dp->sibling;
  766. }
  767. /* Assume if node is not present, PROM uses different tick mechanism
  768. * which we should not care about.
  769. */
  770. if (!dp) {
  771. prom_timers = (struct sun5_timer *) 0;
  772. return;
  773. }
  774. /* If PROM is really using this, it must be mapped by him. */
  775. addr = of_get_property(dp, "address", NULL);
  776. if (!addr) {
  777. prom_printf("PROM does not have timer mapped, trying to continue.\n");
  778. prom_timers = (struct sun5_timer *) 0;
  779. return;
  780. }
  781. prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
  782. }
  783. static void kill_prom_timer(void)
  784. {
  785. if (!prom_timers)
  786. return;
  787. /* Save them away for later. */
  788. prom_limit0 = prom_timers->limit0;
  789. prom_limit1 = prom_timers->limit1;
  790. /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
  791. * We turn both off here just to be paranoid.
  792. */
  793. prom_timers->limit0 = 0;
  794. prom_timers->limit1 = 0;
  795. /* Wheee, eat the interrupt packet too... */
  796. __asm__ __volatile__(
  797. " mov 0x40, %%g2\n"
  798. " ldxa [%%g0] %0, %%g1\n"
  799. " ldxa [%%g2] %1, %%g1\n"
  800. " stxa %%g0, [%%g0] %0\n"
  801. " membar #Sync\n"
  802. : /* no outputs */
  803. : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
  804. : "g1", "g2");
  805. }
  806. void notrace init_irqwork_curcpu(void)
  807. {
  808. int cpu = hard_smp_processor_id();
  809. trap_block[cpu].irq_worklist_pa = 0UL;
  810. }
  811. /* Please be very careful with register_one_mondo() and
  812. * sun4v_register_mondo_queues().
  813. *
  814. * On SMP this gets invoked from the CPU trampoline before
  815. * the cpu has fully taken over the trap table from OBP,
  816. * and it's kernel stack + %g6 thread register state is
  817. * not fully cooked yet.
  818. *
  819. * Therefore you cannot make any OBP calls, not even prom_printf,
  820. * from these two routines.
  821. */
  822. static void notrace register_one_mondo(unsigned long paddr, unsigned long type,
  823. unsigned long qmask)
  824. {
  825. unsigned long num_entries = (qmask + 1) / 64;
  826. unsigned long status;
  827. status = sun4v_cpu_qconf(type, paddr, num_entries);
  828. if (status != HV_EOK) {
  829. prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
  830. "err %lu\n", type, paddr, num_entries, status);
  831. prom_halt();
  832. }
  833. }
  834. void notrace sun4v_register_mondo_queues(int this_cpu)
  835. {
  836. struct trap_per_cpu *tb = &trap_block[this_cpu];
  837. register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
  838. tb->cpu_mondo_qmask);
  839. register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
  840. tb->dev_mondo_qmask);
  841. register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
  842. tb->resum_qmask);
  843. register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
  844. tb->nonresum_qmask);
  845. }
  846. /* Each queue region must be a power of 2 multiple of 64 bytes in
  847. * size. The base real address must be aligned to the size of the
  848. * region. Thus, an 8KB queue must be 8KB aligned, for example.
  849. */
  850. static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
  851. {
  852. unsigned long size = PAGE_ALIGN(qmask + 1);
  853. unsigned long order = get_order(size);
  854. unsigned long p;
  855. p = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
  856. if (!p) {
  857. prom_printf("SUN4V: Error, cannot allocate queue.\n");
  858. prom_halt();
  859. }
  860. *pa_ptr = __pa(p);
  861. }
  862. static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
  863. {
  864. #ifdef CONFIG_SMP
  865. unsigned long page;
  866. void *mondo, *p;
  867. BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > PAGE_SIZE);
  868. /* Make sure mondo block is 64byte aligned */
  869. p = kzalloc(127, GFP_KERNEL);
  870. if (!p) {
  871. prom_printf("SUN4V: Error, cannot allocate mondo block.\n");
  872. prom_halt();
  873. }
  874. mondo = (void *)(((unsigned long)p + 63) & ~0x3f);
  875. tb->cpu_mondo_block_pa = __pa(mondo);
  876. page = get_zeroed_page(GFP_KERNEL);
  877. if (!page) {
  878. prom_printf("SUN4V: Error, cannot allocate cpu list page.\n");
  879. prom_halt();
  880. }
  881. tb->cpu_list_pa = __pa(page);
  882. #endif
  883. }
  884. /* Allocate mondo and error queues for all possible cpus. */
  885. static void __init sun4v_init_mondo_queues(void)
  886. {
  887. int cpu;
  888. for_each_possible_cpu(cpu) {
  889. struct trap_per_cpu *tb = &trap_block[cpu];
  890. alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
  891. alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
  892. alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
  893. alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
  894. alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
  895. alloc_one_queue(&tb->nonresum_kernel_buf_pa,
  896. tb->nonresum_qmask);
  897. }
  898. }
  899. static void __init init_send_mondo_info(void)
  900. {
  901. int cpu;
  902. for_each_possible_cpu(cpu) {
  903. struct trap_per_cpu *tb = &trap_block[cpu];
  904. init_cpu_send_mondo_info(tb);
  905. }
  906. }
  907. static struct irqaction timer_irq_action = {
  908. .name = "timer",
  909. };
  910. static void __init irq_ivector_init(void)
  911. {
  912. unsigned long size, order;
  913. unsigned int ivecs;
  914. /* If we are doing cookie only VIRQs then we do not need the ivector
  915. * table to process interrupts.
  916. */
  917. if (sun4v_cookie_only_virqs())
  918. return;
  919. ivecs = size_nr_ivec();
  920. size = sizeof(struct ino_bucket) * ivecs;
  921. order = get_order(size);
  922. ivector_table = (struct ino_bucket *)
  923. __get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
  924. if (!ivector_table) {
  925. prom_printf("Fatal error, cannot allocate ivector_table\n");
  926. prom_halt();
  927. }
  928. __flush_dcache_range((unsigned long) ivector_table,
  929. ((unsigned long) ivector_table) + size);
  930. ivector_table_pa = __pa(ivector_table);
  931. }
  932. /* Only invoked on boot processor.*/
  933. void __init init_IRQ(void)
  934. {
  935. irq_init_hv();
  936. irq_ivector_init();
  937. map_prom_timers();
  938. kill_prom_timer();
  939. if (tlb_type == hypervisor)
  940. sun4v_init_mondo_queues();
  941. init_send_mondo_info();
  942. if (tlb_type == hypervisor) {
  943. /* Load up the boot cpu's entries. */
  944. sun4v_register_mondo_queues(hard_smp_processor_id());
  945. }
  946. /* We need to clear any IRQ's pending in the soft interrupt
  947. * registers, a spurious one could be left around from the
  948. * PROM timer which we just disabled.
  949. */
  950. clear_softint(get_softint());
  951. /* Now that ivector table is initialized, it is safe
  952. * to receive IRQ vector traps. We will normally take
  953. * one or two right now, in case some device PROM used
  954. * to boot us wants to speak to us. We just ignore them.
  955. */
  956. __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
  957. "or %%g1, %0, %%g1\n\t"
  958. "wrpr %%g1, 0x0, %%pstate"
  959. : /* No outputs */
  960. : "i" (PSTATE_IE)
  961. : "g1");
  962. irq_to_desc(0)->action = &timer_irq_action;
  963. }