etrap_64.S 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * etrap.S: Preparing for entry into the kernel on Sparc V9.
  4. *
  5. * Copyright (C) 1996, 1997 David S. Miller ([email protected])
  6. * Copyright (C) 1997, 1998, 1999 Jakub Jelinek ([email protected])
  7. */
  8. #include <asm/asi.h>
  9. #include <asm/pstate.h>
  10. #include <asm/ptrace.h>
  11. #include <asm/page.h>
  12. #include <asm/spitfire.h>
  13. #include <asm/head.h>
  14. #include <asm/processor.h>
  15. #include <asm/mmu.h>
  16. #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
  17. #define ETRAP_PSTATE1 (PSTATE_TSO | PSTATE_PRIV)
  18. #define ETRAP_PSTATE2 \
  19. (PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
  20. /*
  21. * On entry, %g7 is return address - 0x4.
  22. * %g4 and %g5 will be preserved %l4 and %l5 respectively.
  23. */
  24. .text
  25. .align 64
  26. .globl etrap_syscall, etrap, etrap_irq, etraptl1
  27. etrap: rdpr %pil, %g2
  28. etrap_irq: clr %g3
  29. etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
  30. rdpr %tstate, %g1
  31. or %g1, %g3, %g1
  32. sllx %g2, 20, %g3
  33. andcc %g1, TSTATE_PRIV, %g0
  34. or %g1, %g3, %g1
  35. bne,pn %xcc, 1f
  36. sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
  37. 661: wrpr %g0, 7, %cleanwin
  38. .section .fast_win_ctrl_1insn_patch, "ax"
  39. .word 661b
  40. .word 0x85880000 ! allclean
  41. .previous
  42. sethi %hi(TASK_REGOFF), %g2
  43. sethi %hi(TSTATE_PEF), %g3
  44. or %g2, %lo(TASK_REGOFF), %g2
  45. and %g1, %g3, %g3
  46. brnz,pn %g3, 1f
  47. add %g6, %g2, %g2
  48. wr %g0, 0, %fprs
  49. 1: rdpr %tpc, %g3
  50. stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
  51. rdpr %tnpc, %g1
  52. stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
  53. rd %y, %g3
  54. stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
  55. rdpr %tt, %g1
  56. st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
  57. sethi %hi(PT_REGS_MAGIC), %g3
  58. or %g3, %g1, %g1
  59. st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
  60. rdpr %cansave, %g1
  61. brnz,pt %g1, etrap_save
  62. nop
  63. rdpr %cwp, %g1
  64. add %g1, 2, %g1
  65. wrpr %g1, %cwp
  66. be,pt %xcc, etrap_user_spill
  67. mov ASI_AIUP, %g3
  68. rdpr %otherwin, %g3
  69. brz %g3, etrap_kernel_spill
  70. mov ASI_AIUS, %g3
  71. etrap_user_spill:
  72. wr %g3, 0x0, %asi
  73. ldx [%g6 + TI_FLAGS], %g3
  74. and %g3, _TIF_32BIT, %g3
  75. brnz,pt %g3, etrap_user_spill_32bit
  76. nop
  77. ba,a,pt %xcc, etrap_user_spill_64bit
  78. etrap_save: save %g2, -STACK_BIAS, %sp
  79. mov %g6, %l6
  80. bne,pn %xcc, 3f
  81. mov PRIMARY_CONTEXT, %l4
  82. 661: rdpr %canrestore, %g3
  83. .section .fast_win_ctrl_1insn_patch, "ax"
  84. .word 661b
  85. nop
  86. .previous
  87. rdpr %wstate, %g2
  88. 661: wrpr %g0, 0, %canrestore
  89. .section .fast_win_ctrl_1insn_patch, "ax"
  90. .word 661b
  91. nop
  92. .previous
  93. sll %g2, 3, %g2
  94. /* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */
  95. mov 1, %l5
  96. sth %l5, [%l6 + TI_SYS_NOERROR]
  97. 661: wrpr %g3, 0, %otherwin
  98. .section .fast_win_ctrl_1insn_patch, "ax"
  99. .word 661b
  100. .word 0x87880000 ! otherw
  101. .previous
  102. wrpr %g2, 0, %wstate
  103. sethi %hi(sparc64_kern_pri_context), %g2
  104. ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
  105. 661: stxa %g3, [%l4] ASI_DMMU
  106. .section .sun4v_1insn_patch, "ax"
  107. .word 661b
  108. stxa %g3, [%l4] ASI_MMU
  109. .previous
  110. sethi %hi(KERNBASE), %l4
  111. flush %l4
  112. mov ASI_AIUS, %l7
  113. 2: mov %g4, %l4
  114. mov %g5, %l5
  115. add %g7, 4, %l2
  116. /* Go to trap time globals so we can save them. */
  117. 661: wrpr %g0, ETRAP_PSTATE1, %pstate
  118. .section .sun4v_1insn_patch, "ax"
  119. .word 661b
  120. SET_GL(0)
  121. .previous
  122. stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
  123. stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
  124. sllx %l7, 24, %l7
  125. stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
  126. rdpr %cwp, %l0
  127. stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
  128. stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
  129. stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
  130. stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
  131. or %l7, %l0, %l7
  132. 661: sethi %hi(TSTATE_TSO | TSTATE_PEF), %l0
  133. /* If userspace is using ADI, it could potentially pass
  134. * a pointer with version tag embedded in it. To maintain
  135. * the ADI security, we must enable PSTATE.mcde. Userspace
  136. * would have already set TTE.mcd in an earlier call to
  137. * kernel and set the version tag for the address being
  138. * dereferenced. Setting PSTATE.mcde would ensure any
  139. * access to userspace data through a system call honors
  140. * ADI and does not allow a rogue app to bypass ADI by
  141. * using system calls. Setting PSTATE.mcde only affects
  142. * accesses to virtual addresses that have TTE.mcd set.
  143. * Set PMCDPER to ensure any exceptions caused by ADI
  144. * version tag mismatch are exposed before system call
  145. * returns to userspace. Setting PMCDPER affects only
  146. * writes to virtual addresses that have TTE.mcd set and
  147. * have a version tag set as well.
  148. */
  149. .section .sun_m7_1insn_patch, "ax"
  150. .word 661b
  151. sethi %hi(TSTATE_TSO | TSTATE_PEF | TSTATE_MCDE), %l0
  152. .previous
  153. 661: nop
  154. .section .sun_m7_1insn_patch, "ax"
  155. .word 661b
  156. .word 0xaf902001 /* wrpr %g0, 1, %pmcdper */
  157. .previous
  158. or %l7, %l0, %l7
  159. wrpr %l2, %tnpc
  160. wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
  161. stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
  162. stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
  163. stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
  164. stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
  165. stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
  166. stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
  167. stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
  168. mov %l6, %g6
  169. stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
  170. LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
  171. ldx [%g6 + TI_TASK], %g4
  172. done
  173. 3: mov ASI_P, %l7
  174. ldub [%l6 + TI_FPDEPTH], %l5
  175. add %l6, TI_FPSAVED + 1, %l4
  176. srl %l5, 1, %l3
  177. add %l5, 2, %l5
  178. /* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
  179. sth %l5, [%l6 + TI_SYS_NOERROR]
  180. ba,pt %xcc, 2b
  181. stb %g0, [%l4 + %l3]
  182. nop
  183. etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
  184. * We place this right after pt_regs on the trap stack.
  185. * The layout is:
  186. * 0x00 TL1's TSTATE
  187. * 0x08 TL1's TPC
  188. * 0x10 TL1's TNPC
  189. * 0x18 TL1's TT
  190. * ...
  191. * 0x58 TL4's TT
  192. * 0x60 TL
  193. */
  194. TRAP_LOAD_THREAD_REG(%g6, %g1)
  195. sub %sp, ((4 * 8) * 4) + 8, %g2
  196. rdpr %tl, %g1
  197. wrpr %g0, 1, %tl
  198. rdpr %tstate, %g3
  199. stx %g3, [%g2 + STACK_BIAS + 0x00]
  200. rdpr %tpc, %g3
  201. stx %g3, [%g2 + STACK_BIAS + 0x08]
  202. rdpr %tnpc, %g3
  203. stx %g3, [%g2 + STACK_BIAS + 0x10]
  204. rdpr %tt, %g3
  205. stx %g3, [%g2 + STACK_BIAS + 0x18]
  206. wrpr %g0, 2, %tl
  207. rdpr %tstate, %g3
  208. stx %g3, [%g2 + STACK_BIAS + 0x20]
  209. rdpr %tpc, %g3
  210. stx %g3, [%g2 + STACK_BIAS + 0x28]
  211. rdpr %tnpc, %g3
  212. stx %g3, [%g2 + STACK_BIAS + 0x30]
  213. rdpr %tt, %g3
  214. stx %g3, [%g2 + STACK_BIAS + 0x38]
  215. sethi %hi(is_sun4v), %g3
  216. lduw [%g3 + %lo(is_sun4v)], %g3
  217. brnz,pn %g3, finish_tl1_capture
  218. nop
  219. wrpr %g0, 3, %tl
  220. rdpr %tstate, %g3
  221. stx %g3, [%g2 + STACK_BIAS + 0x40]
  222. rdpr %tpc, %g3
  223. stx %g3, [%g2 + STACK_BIAS + 0x48]
  224. rdpr %tnpc, %g3
  225. stx %g3, [%g2 + STACK_BIAS + 0x50]
  226. rdpr %tt, %g3
  227. stx %g3, [%g2 + STACK_BIAS + 0x58]
  228. wrpr %g0, 4, %tl
  229. rdpr %tstate, %g3
  230. stx %g3, [%g2 + STACK_BIAS + 0x60]
  231. rdpr %tpc, %g3
  232. stx %g3, [%g2 + STACK_BIAS + 0x68]
  233. rdpr %tnpc, %g3
  234. stx %g3, [%g2 + STACK_BIAS + 0x70]
  235. rdpr %tt, %g3
  236. stx %g3, [%g2 + STACK_BIAS + 0x78]
  237. stx %g1, [%g2 + STACK_BIAS + 0x80]
  238. finish_tl1_capture:
  239. wrpr %g0, 1, %tl
  240. 661: nop
  241. .section .sun4v_1insn_patch, "ax"
  242. .word 661b
  243. SET_GL(1)
  244. .previous
  245. rdpr %tstate, %g1
  246. sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
  247. ba,pt %xcc, 1b
  248. andcc %g1, TSTATE_PRIV, %g0
  249. #undef TASK_REGOFF
  250. #undef ETRAP_PSTATE1