cherrs.S 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* These get patched into the trap table at boot time
  3. * once we know we have a cheetah processor.
  4. */
  5. .globl cheetah_fecc_trap_vector
  6. .type cheetah_fecc_trap_vector,#function
  7. cheetah_fecc_trap_vector:
  8. membar #Sync
  9. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
  10. andn %g1, DCU_DC | DCU_IC, %g1
  11. stxa %g1, [%g0] ASI_DCU_CONTROL_REG
  12. membar #Sync
  13. sethi %hi(cheetah_fast_ecc), %g2
  14. jmpl %g2 + %lo(cheetah_fast_ecc), %g0
  15. mov 0, %g1
  16. .size cheetah_fecc_trap_vector,.-cheetah_fecc_trap_vector
  17. .globl cheetah_fecc_trap_vector_tl1
  18. .type cheetah_fecc_trap_vector_tl1,#function
  19. cheetah_fecc_trap_vector_tl1:
  20. membar #Sync
  21. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
  22. andn %g1, DCU_DC | DCU_IC, %g1
  23. stxa %g1, [%g0] ASI_DCU_CONTROL_REG
  24. membar #Sync
  25. sethi %hi(cheetah_fast_ecc), %g2
  26. jmpl %g2 + %lo(cheetah_fast_ecc), %g0
  27. mov 1, %g1
  28. .size cheetah_fecc_trap_vector_tl1,.-cheetah_fecc_trap_vector_tl1
  29. .globl cheetah_cee_trap_vector
  30. .type cheetah_cee_trap_vector,#function
  31. cheetah_cee_trap_vector:
  32. membar #Sync
  33. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
  34. andn %g1, DCU_IC, %g1
  35. stxa %g1, [%g0] ASI_DCU_CONTROL_REG
  36. membar #Sync
  37. sethi %hi(cheetah_cee), %g2
  38. jmpl %g2 + %lo(cheetah_cee), %g0
  39. mov 0, %g1
  40. .size cheetah_cee_trap_vector,.-cheetah_cee_trap_vector
  41. .globl cheetah_cee_trap_vector_tl1
  42. .type cheetah_cee_trap_vector_tl1,#function
  43. cheetah_cee_trap_vector_tl1:
  44. membar #Sync
  45. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
  46. andn %g1, DCU_IC, %g1
  47. stxa %g1, [%g0] ASI_DCU_CONTROL_REG
  48. membar #Sync
  49. sethi %hi(cheetah_cee), %g2
  50. jmpl %g2 + %lo(cheetah_cee), %g0
  51. mov 1, %g1
  52. .size cheetah_cee_trap_vector_tl1,.-cheetah_cee_trap_vector_tl1
  53. .globl cheetah_deferred_trap_vector
  54. .type cheetah_deferred_trap_vector,#function
  55. cheetah_deferred_trap_vector:
  56. membar #Sync
  57. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
  58. andn %g1, DCU_DC | DCU_IC, %g1;
  59. stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
  60. membar #Sync;
  61. sethi %hi(cheetah_deferred_trap), %g2
  62. jmpl %g2 + %lo(cheetah_deferred_trap), %g0
  63. mov 0, %g1
  64. .size cheetah_deferred_trap_vector,.-cheetah_deferred_trap_vector
  65. .globl cheetah_deferred_trap_vector_tl1
  66. .type cheetah_deferred_trap_vector_tl1,#function
  67. cheetah_deferred_trap_vector_tl1:
  68. membar #Sync;
  69. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
  70. andn %g1, DCU_DC | DCU_IC, %g1;
  71. stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
  72. membar #Sync;
  73. sethi %hi(cheetah_deferred_trap), %g2
  74. jmpl %g2 + %lo(cheetah_deferred_trap), %g0
  75. mov 1, %g1
  76. .size cheetah_deferred_trap_vector_tl1,.-cheetah_deferred_trap_vector_tl1
  77. /* Cheetah+ specific traps. These are for the new I/D cache parity
  78. * error traps. The first argument to cheetah_plus_parity_handler
  79. * is encoded as follows:
  80. *
  81. * Bit0: 0=dcache,1=icache
  82. * Bit1: 0=recoverable,1=unrecoverable
  83. */
  84. .globl cheetah_plus_dcpe_trap_vector
  85. .type cheetah_plus_dcpe_trap_vector,#function
  86. cheetah_plus_dcpe_trap_vector:
  87. membar #Sync
  88. sethi %hi(do_cheetah_plus_data_parity), %g7
  89. jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
  90. nop
  91. nop
  92. nop
  93. nop
  94. nop
  95. .size cheetah_plus_dcpe_trap_vector,.-cheetah_plus_dcpe_trap_vector
  96. .type do_cheetah_plus_data_parity,#function
  97. do_cheetah_plus_data_parity:
  98. rdpr %pil, %g2
  99. wrpr %g0, PIL_NORMAL_MAX, %pil
  100. ba,pt %xcc, etrap_irq
  101. rd %pc, %g7
  102. #ifdef CONFIG_TRACE_IRQFLAGS
  103. call trace_hardirqs_off
  104. nop
  105. #endif
  106. mov 0x0, %o0
  107. call cheetah_plus_parity_error
  108. add %sp, PTREGS_OFF, %o1
  109. ba,a,pt %xcc, rtrap_irq
  110. .size do_cheetah_plus_data_parity,.-do_cheetah_plus_data_parity
  111. .globl cheetah_plus_dcpe_trap_vector_tl1
  112. .type cheetah_plus_dcpe_trap_vector_tl1,#function
  113. cheetah_plus_dcpe_trap_vector_tl1:
  114. membar #Sync
  115. wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
  116. sethi %hi(do_dcpe_tl1), %g3
  117. jmpl %g3 + %lo(do_dcpe_tl1), %g0
  118. nop
  119. nop
  120. nop
  121. nop
  122. .size cheetah_plus_dcpe_trap_vector_tl1,.-cheetah_plus_dcpe_trap_vector_tl1
  123. .globl cheetah_plus_icpe_trap_vector
  124. .type cheetah_plus_icpe_trap_vector,#function
  125. cheetah_plus_icpe_trap_vector:
  126. membar #Sync
  127. sethi %hi(do_cheetah_plus_insn_parity), %g7
  128. jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
  129. nop
  130. nop
  131. nop
  132. nop
  133. nop
  134. .size cheetah_plus_icpe_trap_vector,.-cheetah_plus_icpe_trap_vector
  135. .type do_cheetah_plus_insn_parity,#function
  136. do_cheetah_plus_insn_parity:
  137. rdpr %pil, %g2
  138. wrpr %g0, PIL_NORMAL_MAX, %pil
  139. ba,pt %xcc, etrap_irq
  140. rd %pc, %g7
  141. #ifdef CONFIG_TRACE_IRQFLAGS
  142. call trace_hardirqs_off
  143. nop
  144. #endif
  145. mov 0x1, %o0
  146. call cheetah_plus_parity_error
  147. add %sp, PTREGS_OFF, %o1
  148. ba,a,pt %xcc, rtrap_irq
  149. .size do_cheetah_plus_insn_parity,.-do_cheetah_plus_insn_parity
  150. .globl cheetah_plus_icpe_trap_vector_tl1
  151. .type cheetah_plus_icpe_trap_vector_tl1,#function
  152. cheetah_plus_icpe_trap_vector_tl1:
  153. membar #Sync
  154. wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
  155. sethi %hi(do_icpe_tl1), %g3
  156. jmpl %g3 + %lo(do_icpe_tl1), %g0
  157. nop
  158. nop
  159. nop
  160. nop
  161. .size cheetah_plus_icpe_trap_vector_tl1,.-cheetah_plus_icpe_trap_vector_tl1
  162. /* If we take one of these traps when tl >= 1, then we
  163. * jump to interrupt globals. If some trap level above us
  164. * was also using interrupt globals, we cannot recover.
  165. * We may use all interrupt global registers except %g6.
  166. */
  167. .globl do_dcpe_tl1
  168. .type do_dcpe_tl1,#function
  169. do_dcpe_tl1:
  170. rdpr %tl, %g1 ! Save original trap level
  171. mov 1, %g2 ! Setup TSTATE checking loop
  172. sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
  173. 1: wrpr %g2, %tl ! Set trap level to check
  174. rdpr %tstate, %g4 ! Read TSTATE for this level
  175. andcc %g4, %g3, %g0 ! Interrupt globals in use?
  176. bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
  177. wrpr %g1, %tl ! Restore original trap level
  178. add %g2, 1, %g2 ! Next trap level
  179. cmp %g2, %g1 ! Hit them all yet?
  180. ble,pt %icc, 1b ! Not yet
  181. nop
  182. wrpr %g1, %tl ! Restore original trap level
  183. do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
  184. sethi %hi(dcache_parity_tl1_occurred), %g2
  185. lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1
  186. add %g1, 1, %g1
  187. stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)]
  188. /* Reset D-cache parity */
  189. sethi %hi(1 << 16), %g1 ! D-cache size
  190. mov (1 << 5), %g2 ! D-cache line size
  191. sub %g1, %g2, %g1 ! Move down 1 cacheline
  192. 1: srl %g1, 14, %g3 ! Compute UTAG
  193. membar #Sync
  194. stxa %g3, [%g1] ASI_DCACHE_UTAG
  195. membar #Sync
  196. sub %g2, 8, %g3 ! 64-bit data word within line
  197. 2: membar #Sync
  198. stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
  199. membar #Sync
  200. subcc %g3, 8, %g3 ! Next 64-bit data word
  201. bge,pt %icc, 2b
  202. nop
  203. subcc %g1, %g2, %g1 ! Next cacheline
  204. bge,pt %icc, 1b
  205. nop
  206. ba,a,pt %xcc, dcpe_icpe_tl1_common
  207. do_dcpe_tl1_fatal:
  208. sethi %hi(1f), %g7
  209. ba,pt %xcc, etraptl1
  210. 1: or %g7, %lo(1b), %g7
  211. mov 0x2, %o0
  212. call cheetah_plus_parity_error
  213. add %sp, PTREGS_OFF, %o1
  214. ba,a,pt %xcc, rtrap
  215. .size do_dcpe_tl1,.-do_dcpe_tl1
  216. .globl do_icpe_tl1
  217. .type do_icpe_tl1,#function
  218. do_icpe_tl1:
  219. rdpr %tl, %g1 ! Save original trap level
  220. mov 1, %g2 ! Setup TSTATE checking loop
  221. sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
  222. 1: wrpr %g2, %tl ! Set trap level to check
  223. rdpr %tstate, %g4 ! Read TSTATE for this level
  224. andcc %g4, %g3, %g0 ! Interrupt globals in use?
  225. bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
  226. wrpr %g1, %tl ! Restore original trap level
  227. add %g2, 1, %g2 ! Next trap level
  228. cmp %g2, %g1 ! Hit them all yet?
  229. ble,pt %icc, 1b ! Not yet
  230. nop
  231. wrpr %g1, %tl ! Restore original trap level
  232. do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
  233. sethi %hi(icache_parity_tl1_occurred), %g2
  234. lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1
  235. add %g1, 1, %g1
  236. stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)]
  237. /* Flush I-cache */
  238. sethi %hi(1 << 15), %g1 ! I-cache size
  239. mov (1 << 5), %g2 ! I-cache line size
  240. sub %g1, %g2, %g1
  241. 1: or %g1, (2 << 3), %g3
  242. stxa %g0, [%g3] ASI_IC_TAG
  243. membar #Sync
  244. subcc %g1, %g2, %g1
  245. bge,pt %icc, 1b
  246. nop
  247. ba,a,pt %xcc, dcpe_icpe_tl1_common
  248. do_icpe_tl1_fatal:
  249. sethi %hi(1f), %g7
  250. ba,pt %xcc, etraptl1
  251. 1: or %g7, %lo(1b), %g7
  252. mov 0x3, %o0
  253. call cheetah_plus_parity_error
  254. add %sp, PTREGS_OFF, %o1
  255. ba,a,pt %xcc, rtrap
  256. .size do_icpe_tl1,.-do_icpe_tl1
  257. .type dcpe_icpe_tl1_common,#function
  258. dcpe_icpe_tl1_common:
  259. /* Flush D-cache, re-enable D/I caches in DCU and finally
  260. * retry the trapping instruction.
  261. */
  262. sethi %hi(1 << 16), %g1 ! D-cache size
  263. mov (1 << 5), %g2 ! D-cache line size
  264. sub %g1, %g2, %g1
  265. 1: stxa %g0, [%g1] ASI_DCACHE_TAG
  266. membar #Sync
  267. subcc %g1, %g2, %g1
  268. bge,pt %icc, 1b
  269. nop
  270. ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
  271. or %g1, (DCU_DC | DCU_IC), %g1
  272. stxa %g1, [%g0] ASI_DCU_CONTROL_REG
  273. membar #Sync
  274. retry
  275. .size dcpe_icpe_tl1_common,.-dcpe_icpe_tl1_common
  276. /* Capture I/D/E-cache state into per-cpu error scoreboard.
  277. *
  278. * %g1: (TL>=0) ? 1 : 0
  279. * %g2: scratch
  280. * %g3: scratch
  281. * %g4: AFSR
  282. * %g5: AFAR
  283. * %g6: unused, will have current thread ptr after etrap
  284. * %g7: scratch
  285. */
  286. .type __cheetah_log_error,#function
  287. __cheetah_log_error:
  288. /* Put "TL1" software bit into AFSR. */
  289. and %g1, 0x1, %g1
  290. sllx %g1, 63, %g2
  291. or %g4, %g2, %g4
  292. /* Get log entry pointer for this cpu at this trap level. */
  293. BRANCH_IF_JALAPENO(g2,g3,50f)
  294. ldxa [%g0] ASI_SAFARI_CONFIG, %g2
  295. srlx %g2, 17, %g2
  296. ba,pt %xcc, 60f
  297. and %g2, 0x3ff, %g2
  298. 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2
  299. srlx %g2, 17, %g2
  300. and %g2, 0x1f, %g2
  301. 60: sllx %g2, 9, %g2
  302. sethi %hi(cheetah_error_log), %g3
  303. ldx [%g3 + %lo(cheetah_error_log)], %g3
  304. brz,pn %g3, 80f
  305. nop
  306. add %g3, %g2, %g3
  307. sllx %g1, 8, %g1
  308. add %g3, %g1, %g1
  309. /* %g1 holds pointer to the top of the logging scoreboard */
  310. ldx [%g1 + 0x0], %g7
  311. cmp %g7, -1
  312. bne,pn %xcc, 80f
  313. nop
  314. stx %g4, [%g1 + 0x0]
  315. stx %g5, [%g1 + 0x8]
  316. add %g1, 0x10, %g1
  317. /* %g1 now points to D-cache logging area */
  318. set 0x3ff8, %g2 /* DC_addr mask */
  319. and %g5, %g2, %g2 /* DC_addr bits of AFAR */
  320. srlx %g5, 12, %g3
  321. or %g3, 1, %g3 /* PHYS tag + valid */
  322. 10: ldxa [%g2] ASI_DCACHE_TAG, %g7
  323. cmp %g3, %g7 /* TAG match? */
  324. bne,pt %xcc, 13f
  325. nop
  326. /* Yep, what we want, capture state. */
  327. stx %g2, [%g1 + 0x20]
  328. stx %g7, [%g1 + 0x28]
  329. /* A membar Sync is required before and after utag access. */
  330. membar #Sync
  331. ldxa [%g2] ASI_DCACHE_UTAG, %g7
  332. membar #Sync
  333. stx %g7, [%g1 + 0x30]
  334. ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
  335. stx %g7, [%g1 + 0x38]
  336. clr %g3
  337. 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
  338. stx %g7, [%g1]
  339. add %g3, (1 << 5), %g3
  340. cmp %g3, (4 << 5)
  341. bl,pt %xcc, 12b
  342. add %g1, 0x8, %g1
  343. ba,pt %xcc, 20f
  344. add %g1, 0x20, %g1
  345. 13: sethi %hi(1 << 14), %g7
  346. add %g2, %g7, %g2
  347. srlx %g2, 14, %g7
  348. cmp %g7, 4
  349. bl,pt %xcc, 10b
  350. nop
  351. add %g1, 0x40, %g1
  352. /* %g1 now points to I-cache logging area */
  353. 20: set 0x1fe0, %g2 /* IC_addr mask */
  354. and %g5, %g2, %g2 /* IC_addr bits of AFAR */
  355. sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
  356. srlx %g5, (13 - 8), %g3 /* Make PTAG */
  357. andn %g3, 0xff, %g3 /* Mask off undefined bits */
  358. 21: ldxa [%g2] ASI_IC_TAG, %g7
  359. andn %g7, 0xff, %g7
  360. cmp %g3, %g7
  361. bne,pt %xcc, 23f
  362. nop
  363. /* Yep, what we want, capture state. */
  364. stx %g2, [%g1 + 0x40]
  365. stx %g7, [%g1 + 0x48]
  366. add %g2, (1 << 3), %g2
  367. ldxa [%g2] ASI_IC_TAG, %g7
  368. add %g2, (1 << 3), %g2
  369. stx %g7, [%g1 + 0x50]
  370. ldxa [%g2] ASI_IC_TAG, %g7
  371. add %g2, (1 << 3), %g2
  372. stx %g7, [%g1 + 0x60]
  373. ldxa [%g2] ASI_IC_TAG, %g7
  374. stx %g7, [%g1 + 0x68]
  375. sub %g2, (3 << 3), %g2
  376. ldxa [%g2] ASI_IC_STAG, %g7
  377. stx %g7, [%g1 + 0x58]
  378. clr %g3
  379. srlx %g2, 2, %g2
  380. 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
  381. stx %g7, [%g1]
  382. add %g3, (1 << 3), %g3
  383. cmp %g3, (8 << 3)
  384. bl,pt %xcc, 22b
  385. add %g1, 0x8, %g1
  386. ba,pt %xcc, 30f
  387. add %g1, 0x30, %g1
  388. 23: sethi %hi(1 << 14), %g7
  389. add %g2, %g7, %g2
  390. srlx %g2, 14, %g7
  391. cmp %g7, 4
  392. bl,pt %xcc, 21b
  393. nop
  394. add %g1, 0x70, %g1
  395. /* %g1 now points to E-cache logging area */
  396. 30: andn %g5, (32 - 1), %g2
  397. stx %g2, [%g1 + 0x20]
  398. ldxa [%g2] ASI_EC_TAG_DATA, %g7
  399. stx %g7, [%g1 + 0x28]
  400. ldxa [%g2] ASI_EC_R, %g0
  401. clr %g3
  402. 31: ldxa [%g3] ASI_EC_DATA, %g7
  403. stx %g7, [%g1 + %g3]
  404. add %g3, 0x8, %g3
  405. cmp %g3, 0x20
  406. bl,pt %xcc, 31b
  407. nop
  408. 80:
  409. rdpr %tt, %g2
  410. cmp %g2, 0x70
  411. be c_fast_ecc
  412. cmp %g2, 0x63
  413. be c_cee
  414. nop
  415. ba,a,pt %xcc, c_deferred
  416. .size __cheetah_log_error,.-__cheetah_log_error
  417. /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
  418. * in the trap table. That code has done a memory barrier
  419. * and has disabled both the I-cache and D-cache in the DCU
  420. * control register. The I-cache is disabled so that we may
  421. * capture the corrupted cache line, and the D-cache is disabled
  422. * because corrupt data may have been placed there and we don't
  423. * want to reference it.
  424. *
  425. * %g1 is one if this trap occurred at %tl >= 1.
  426. *
  427. * Next, we turn off error reporting so that we don't recurse.
  428. */
  429. .globl cheetah_fast_ecc
  430. .type cheetah_fast_ecc,#function
  431. cheetah_fast_ecc:
  432. ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
  433. andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
  434. stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
  435. membar #Sync
  436. /* Fetch and clear AFSR/AFAR */
  437. ldxa [%g0] ASI_AFSR, %g4
  438. ldxa [%g0] ASI_AFAR, %g5
  439. stxa %g4, [%g0] ASI_AFSR
  440. membar #Sync
  441. ba,pt %xcc, __cheetah_log_error
  442. nop
  443. .size cheetah_fast_ecc,.-cheetah_fast_ecc
  444. .type c_fast_ecc,#function
  445. c_fast_ecc:
  446. rdpr %pil, %g2
  447. wrpr %g0, PIL_NORMAL_MAX, %pil
  448. ba,pt %xcc, etrap_irq
  449. rd %pc, %g7
  450. #ifdef CONFIG_TRACE_IRQFLAGS
  451. call trace_hardirqs_off
  452. nop
  453. #endif
  454. mov %l4, %o1
  455. mov %l5, %o2
  456. call cheetah_fecc_handler
  457. add %sp, PTREGS_OFF, %o0
  458. ba,a,pt %xcc, rtrap_irq
  459. .size c_fast_ecc,.-c_fast_ecc
  460. /* Our caller has disabled I-cache and performed membar Sync. */
  461. .globl cheetah_cee
  462. .type cheetah_cee,#function
  463. cheetah_cee:
  464. ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
  465. andn %g2, ESTATE_ERROR_CEEN, %g2
  466. stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
  467. membar #Sync
  468. /* Fetch and clear AFSR/AFAR */
  469. ldxa [%g0] ASI_AFSR, %g4
  470. ldxa [%g0] ASI_AFAR, %g5
  471. stxa %g4, [%g0] ASI_AFSR
  472. membar #Sync
  473. ba,pt %xcc, __cheetah_log_error
  474. nop
  475. .size cheetah_cee,.-cheetah_cee
  476. .type c_cee,#function
  477. c_cee:
  478. rdpr %pil, %g2
  479. wrpr %g0, PIL_NORMAL_MAX, %pil
  480. ba,pt %xcc, etrap_irq
  481. rd %pc, %g7
  482. #ifdef CONFIG_TRACE_IRQFLAGS
  483. call trace_hardirqs_off
  484. nop
  485. #endif
  486. mov %l4, %o1
  487. mov %l5, %o2
  488. call cheetah_cee_handler
  489. add %sp, PTREGS_OFF, %o0
  490. ba,a,pt %xcc, rtrap_irq
  491. .size c_cee,.-c_cee
  492. /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
  493. .globl cheetah_deferred_trap
  494. .type cheetah_deferred_trap,#function
  495. cheetah_deferred_trap:
  496. ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
  497. andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
  498. stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
  499. membar #Sync
  500. /* Fetch and clear AFSR/AFAR */
  501. ldxa [%g0] ASI_AFSR, %g4
  502. ldxa [%g0] ASI_AFAR, %g5
  503. stxa %g4, [%g0] ASI_AFSR
  504. membar #Sync
  505. ba,pt %xcc, __cheetah_log_error
  506. nop
  507. .size cheetah_deferred_trap,.-cheetah_deferred_trap
  508. .type c_deferred,#function
  509. c_deferred:
  510. rdpr %pil, %g2
  511. wrpr %g0, PIL_NORMAL_MAX, %pil
  512. ba,pt %xcc, etrap_irq
  513. rd %pc, %g7
  514. #ifdef CONFIG_TRACE_IRQFLAGS
  515. call trace_hardirqs_off
  516. nop
  517. #endif
  518. mov %l4, %o1
  519. mov %l5, %o2
  520. call cheetah_deferred_handler
  521. add %sp, PTREGS_OFF, %o0
  522. ba,a,pt %xcc, rtrap_irq
  523. .size c_deferred,.-c_deferred