icp-opal.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright 2016 IBM Corporation.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/kernel.h>
  7. #include <linux/irq.h>
  8. #include <linux/smp.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/irqdomain.h>
  11. #include <linux/cpu.h>
  12. #include <linux/of.h>
  13. #include <asm/smp.h>
  14. #include <asm/irq.h>
  15. #include <asm/errno.h>
  16. #include <asm/xics.h>
  17. #include <asm/io.h>
  18. #include <asm/opal.h>
  19. #include <asm/kvm_ppc.h>
  20. static void icp_opal_teardown_cpu(void)
  21. {
  22. int hw_cpu = hard_smp_processor_id();
  23. /* Clear any pending IPI */
  24. opal_int_set_mfrr(hw_cpu, 0xff);
  25. }
  26. static void icp_opal_flush_ipi(void)
  27. {
  28. /*
  29. * We take the ipi irq but and never return so we need to EOI the IPI,
  30. * but want to leave our priority 0.
  31. *
  32. * Should we check all the other interrupts too?
  33. * Should we be flagging idle loop instead?
  34. * Or creating some task to be scheduled?
  35. */
  36. if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0)
  37. force_external_irq_replay();
  38. }
  39. static unsigned int icp_opal_get_xirr(void)
  40. {
  41. unsigned int kvm_xirr;
  42. __be32 hw_xirr;
  43. int64_t rc;
  44. /* Handle an interrupt latched by KVM first */
  45. kvm_xirr = kvmppc_get_xics_latch();
  46. if (kvm_xirr)
  47. return kvm_xirr;
  48. /* Then ask OPAL */
  49. rc = opal_int_get_xirr(&hw_xirr, false);
  50. if (rc < 0)
  51. return 0;
  52. return be32_to_cpu(hw_xirr);
  53. }
  54. static unsigned int icp_opal_get_irq(void)
  55. {
  56. unsigned int xirr;
  57. unsigned int vec;
  58. unsigned int irq;
  59. xirr = icp_opal_get_xirr();
  60. vec = xirr & 0x00ffffff;
  61. if (vec == XICS_IRQ_SPURIOUS)
  62. return 0;
  63. irq = irq_find_mapping(xics_host, vec);
  64. if (likely(irq)) {
  65. xics_push_cppr(vec);
  66. return irq;
  67. }
  68. /* We don't have a linux mapping, so have rtas mask it. */
  69. xics_mask_unknown_vec(vec);
  70. /* We might learn about it later, so EOI it */
  71. if (opal_int_eoi(xirr) > 0)
  72. force_external_irq_replay();
  73. return 0;
  74. }
  75. static void icp_opal_set_cpu_priority(unsigned char cppr)
  76. {
  77. /*
  78. * Here be dragons. The caller has asked to allow only IPI's and not
  79. * external interrupts. But OPAL XIVE doesn't support that. So instead
  80. * of allowing no interrupts allow all. That's still not right, but
  81. * currently the only caller who does this is xics_migrate_irqs_away()
  82. * and it works in that case.
  83. */
  84. if (cppr >= DEFAULT_PRIORITY)
  85. cppr = LOWEST_PRIORITY;
  86. xics_set_base_cppr(cppr);
  87. opal_int_set_cppr(cppr);
  88. iosync();
  89. }
  90. static void icp_opal_eoi(struct irq_data *d)
  91. {
  92. unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
  93. int64_t rc;
  94. iosync();
  95. rc = opal_int_eoi((xics_pop_cppr() << 24) | hw_irq);
  96. /*
  97. * EOI tells us whether there are more interrupts to fetch.
  98. *
  99. * Some HW implementations might not be able to send us another
  100. * external interrupt in that case, so we force a replay.
  101. */
  102. if (rc > 0)
  103. force_external_irq_replay();
  104. }
  105. #ifdef CONFIG_SMP
  106. static void icp_opal_cause_ipi(int cpu)
  107. {
  108. int hw_cpu = get_hard_smp_processor_id(cpu);
  109. kvmppc_set_host_ipi(cpu);
  110. opal_int_set_mfrr(hw_cpu, IPI_PRIORITY);
  111. }
  112. static irqreturn_t icp_opal_ipi_action(int irq, void *dev_id)
  113. {
  114. int cpu = smp_processor_id();
  115. kvmppc_clear_host_ipi(cpu);
  116. opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
  117. return smp_ipi_demux();
  118. }
  119. /*
  120. * Called when an interrupt is received on an off-line CPU to
  121. * clear the interrupt, so that the CPU can go back to nap mode.
  122. */
  123. void icp_opal_flush_interrupt(void)
  124. {
  125. unsigned int xirr;
  126. unsigned int vec;
  127. do {
  128. xirr = icp_opal_get_xirr();
  129. vec = xirr & 0x00ffffff;
  130. if (vec == XICS_IRQ_SPURIOUS)
  131. break;
  132. if (vec == XICS_IPI) {
  133. /* Clear pending IPI */
  134. int cpu = smp_processor_id();
  135. kvmppc_clear_host_ipi(cpu);
  136. opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
  137. } else {
  138. pr_err("XICS: hw interrupt 0x%x to offline cpu, "
  139. "disabling\n", vec);
  140. xics_mask_unknown_vec(vec);
  141. }
  142. /* EOI the interrupt */
  143. } while (opal_int_eoi(xirr) > 0);
  144. }
  145. #endif /* CONFIG_SMP */
  146. static const struct icp_ops icp_opal_ops = {
  147. .get_irq = icp_opal_get_irq,
  148. .eoi = icp_opal_eoi,
  149. .set_priority = icp_opal_set_cpu_priority,
  150. .teardown_cpu = icp_opal_teardown_cpu,
  151. .flush_ipi = icp_opal_flush_ipi,
  152. #ifdef CONFIG_SMP
  153. .ipi_action = icp_opal_ipi_action,
  154. .cause_ipi = icp_opal_cause_ipi,
  155. #endif
  156. };
  157. int __init icp_opal_init(void)
  158. {
  159. struct device_node *np;
  160. np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc");
  161. if (!np)
  162. return -ENODEV;
  163. icp_ops = &icp_opal_ops;
  164. printk("XICS: Using OPAL ICP fallbacks\n");
  165. of_node_put(np);
  166. return 0;
  167. }