mpic.c 51 KB

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  1. /*
  2. * arch/powerpc/kernel/mpic.c
  3. *
  4. * Driver for interrupt controllers following the OpenPIC standard, the
  5. * common implementation being IBM's MPIC. This driver also can deal
  6. * with various broken implementations of this HW.
  7. *
  8. * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
  9. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  10. *
  11. * This file is subject to the terms and conditions of the GNU General Public
  12. * License. See the file COPYING in the main directory of this archive
  13. * for more details.
  14. */
  15. #undef DEBUG
  16. #undef DEBUG_IPI
  17. #undef DEBUG_IRQ
  18. #undef DEBUG_LOW
  19. #include <linux/types.h>
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/irq.h>
  23. #include <linux/smp.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/syscore_ops.h>
  29. #include <linux/ratelimit.h>
  30. #include <linux/pgtable.h>
  31. #include <linux/of_address.h>
  32. #include <linux/of_irq.h>
  33. #include <asm/ptrace.h>
  34. #include <asm/signal.h>
  35. #include <asm/io.h>
  36. #include <asm/irq.h>
  37. #include <asm/machdep.h>
  38. #include <asm/mpic.h>
  39. #include <asm/smp.h>
  40. #include "mpic.h"
  41. #ifdef DEBUG
  42. #define DBG(fmt...) printk(fmt)
  43. #else
  44. #define DBG(fmt...)
  45. #endif
  46. struct bus_type mpic_subsys = {
  47. .name = "mpic",
  48. .dev_name = "mpic",
  49. };
  50. EXPORT_SYMBOL_GPL(mpic_subsys);
  51. static struct mpic *mpics;
  52. static struct mpic *mpic_primary;
  53. static DEFINE_RAW_SPINLOCK(mpic_lock);
  54. #ifdef CONFIG_PPC32 /* XXX for now */
  55. #ifdef CONFIG_IRQ_ALL_CPUS
  56. #define distribute_irqs (1)
  57. #else
  58. #define distribute_irqs (0)
  59. #endif
  60. #endif
  61. #ifdef CONFIG_MPIC_WEIRD
  62. static u32 mpic_infos[][MPIC_IDX_END] = {
  63. [0] = { /* Original OpenPIC compatible MPIC */
  64. MPIC_GREG_BASE,
  65. MPIC_GREG_FEATURE_0,
  66. MPIC_GREG_GLOBAL_CONF_0,
  67. MPIC_GREG_VENDOR_ID,
  68. MPIC_GREG_IPI_VECTOR_PRI_0,
  69. MPIC_GREG_IPI_STRIDE,
  70. MPIC_GREG_SPURIOUS,
  71. MPIC_GREG_TIMER_FREQ,
  72. MPIC_TIMER_BASE,
  73. MPIC_TIMER_STRIDE,
  74. MPIC_TIMER_CURRENT_CNT,
  75. MPIC_TIMER_BASE_CNT,
  76. MPIC_TIMER_VECTOR_PRI,
  77. MPIC_TIMER_DESTINATION,
  78. MPIC_CPU_BASE,
  79. MPIC_CPU_STRIDE,
  80. MPIC_CPU_IPI_DISPATCH_0,
  81. MPIC_CPU_IPI_DISPATCH_STRIDE,
  82. MPIC_CPU_CURRENT_TASK_PRI,
  83. MPIC_CPU_WHOAMI,
  84. MPIC_CPU_INTACK,
  85. MPIC_CPU_EOI,
  86. MPIC_CPU_MCACK,
  87. MPIC_IRQ_BASE,
  88. MPIC_IRQ_STRIDE,
  89. MPIC_IRQ_VECTOR_PRI,
  90. MPIC_VECPRI_VECTOR_MASK,
  91. MPIC_VECPRI_POLARITY_POSITIVE,
  92. MPIC_VECPRI_POLARITY_NEGATIVE,
  93. MPIC_VECPRI_SENSE_LEVEL,
  94. MPIC_VECPRI_SENSE_EDGE,
  95. MPIC_VECPRI_POLARITY_MASK,
  96. MPIC_VECPRI_SENSE_MASK,
  97. MPIC_IRQ_DESTINATION
  98. },
  99. [1] = { /* Tsi108/109 PIC */
  100. TSI108_GREG_BASE,
  101. TSI108_GREG_FEATURE_0,
  102. TSI108_GREG_GLOBAL_CONF_0,
  103. TSI108_GREG_VENDOR_ID,
  104. TSI108_GREG_IPI_VECTOR_PRI_0,
  105. TSI108_GREG_IPI_STRIDE,
  106. TSI108_GREG_SPURIOUS,
  107. TSI108_GREG_TIMER_FREQ,
  108. TSI108_TIMER_BASE,
  109. TSI108_TIMER_STRIDE,
  110. TSI108_TIMER_CURRENT_CNT,
  111. TSI108_TIMER_BASE_CNT,
  112. TSI108_TIMER_VECTOR_PRI,
  113. TSI108_TIMER_DESTINATION,
  114. TSI108_CPU_BASE,
  115. TSI108_CPU_STRIDE,
  116. TSI108_CPU_IPI_DISPATCH_0,
  117. TSI108_CPU_IPI_DISPATCH_STRIDE,
  118. TSI108_CPU_CURRENT_TASK_PRI,
  119. TSI108_CPU_WHOAMI,
  120. TSI108_CPU_INTACK,
  121. TSI108_CPU_EOI,
  122. TSI108_CPU_MCACK,
  123. TSI108_IRQ_BASE,
  124. TSI108_IRQ_STRIDE,
  125. TSI108_IRQ_VECTOR_PRI,
  126. TSI108_VECPRI_VECTOR_MASK,
  127. TSI108_VECPRI_POLARITY_POSITIVE,
  128. TSI108_VECPRI_POLARITY_NEGATIVE,
  129. TSI108_VECPRI_SENSE_LEVEL,
  130. TSI108_VECPRI_SENSE_EDGE,
  131. TSI108_VECPRI_POLARITY_MASK,
  132. TSI108_VECPRI_SENSE_MASK,
  133. TSI108_IRQ_DESTINATION
  134. },
  135. };
  136. #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
  137. #else /* CONFIG_MPIC_WEIRD */
  138. #define MPIC_INFO(name) MPIC_##name
  139. #endif /* CONFIG_MPIC_WEIRD */
  140. static inline unsigned int mpic_processor_id(struct mpic *mpic)
  141. {
  142. unsigned int cpu = 0;
  143. if (!(mpic->flags & MPIC_SECONDARY))
  144. cpu = hard_smp_processor_id();
  145. return cpu;
  146. }
  147. /*
  148. * Register accessor functions
  149. */
  150. static inline u32 _mpic_read(enum mpic_reg_type type,
  151. struct mpic_reg_bank *rb,
  152. unsigned int reg)
  153. {
  154. switch(type) {
  155. #ifdef CONFIG_PPC_DCR
  156. case mpic_access_dcr:
  157. return dcr_read(rb->dhost, reg);
  158. #endif
  159. case mpic_access_mmio_be:
  160. return in_be32(rb->base + (reg >> 2));
  161. case mpic_access_mmio_le:
  162. default:
  163. return in_le32(rb->base + (reg >> 2));
  164. }
  165. }
  166. static inline void _mpic_write(enum mpic_reg_type type,
  167. struct mpic_reg_bank *rb,
  168. unsigned int reg, u32 value)
  169. {
  170. switch(type) {
  171. #ifdef CONFIG_PPC_DCR
  172. case mpic_access_dcr:
  173. dcr_write(rb->dhost, reg, value);
  174. break;
  175. #endif
  176. case mpic_access_mmio_be:
  177. out_be32(rb->base + (reg >> 2), value);
  178. break;
  179. case mpic_access_mmio_le:
  180. default:
  181. out_le32(rb->base + (reg >> 2), value);
  182. break;
  183. }
  184. }
  185. static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
  186. {
  187. enum mpic_reg_type type = mpic->reg_type;
  188. unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
  189. (ipi * MPIC_INFO(GREG_IPI_STRIDE));
  190. if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
  191. type = mpic_access_mmio_be;
  192. return _mpic_read(type, &mpic->gregs, offset);
  193. }
  194. static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
  195. {
  196. unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
  197. (ipi * MPIC_INFO(GREG_IPI_STRIDE));
  198. _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
  199. }
  200. static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
  201. {
  202. return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
  203. (tm & 3) * MPIC_INFO(TIMER_STRIDE);
  204. }
  205. static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
  206. {
  207. unsigned int offset = mpic_tm_offset(mpic, tm) +
  208. MPIC_INFO(TIMER_VECTOR_PRI);
  209. return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
  210. }
  211. static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
  212. {
  213. unsigned int offset = mpic_tm_offset(mpic, tm) +
  214. MPIC_INFO(TIMER_VECTOR_PRI);
  215. _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
  216. }
  217. static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
  218. {
  219. unsigned int cpu = mpic_processor_id(mpic);
  220. return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
  221. }
  222. static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
  223. {
  224. unsigned int cpu = mpic_processor_id(mpic);
  225. _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
  226. }
  227. static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
  228. {
  229. unsigned int isu = src_no >> mpic->isu_shift;
  230. unsigned int idx = src_no & mpic->isu_mask;
  231. unsigned int val;
  232. val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
  233. reg + (idx * MPIC_INFO(IRQ_STRIDE)));
  234. #ifdef CONFIG_MPIC_BROKEN_REGREAD
  235. if (reg == 0)
  236. val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
  237. mpic->isu_reg0_shadow[src_no];
  238. #endif
  239. return val;
  240. }
  241. static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
  242. unsigned int reg, u32 value)
  243. {
  244. unsigned int isu = src_no >> mpic->isu_shift;
  245. unsigned int idx = src_no & mpic->isu_mask;
  246. _mpic_write(mpic->reg_type, &mpic->isus[isu],
  247. reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
  248. #ifdef CONFIG_MPIC_BROKEN_REGREAD
  249. if (reg == 0)
  250. mpic->isu_reg0_shadow[src_no] =
  251. value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
  252. #endif
  253. }
  254. #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
  255. #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
  256. #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
  257. #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
  258. #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
  259. #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
  260. #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
  261. #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
  262. #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
  263. #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
  264. /*
  265. * Low level utility functions
  266. */
  267. static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
  268. struct mpic_reg_bank *rb, unsigned int offset,
  269. unsigned int size)
  270. {
  271. rb->base = ioremap(phys_addr + offset, size);
  272. BUG_ON(rb->base == NULL);
  273. }
  274. #ifdef CONFIG_PPC_DCR
  275. static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
  276. unsigned int offset, unsigned int size)
  277. {
  278. phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
  279. rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
  280. BUG_ON(!DCR_MAP_OK(rb->dhost));
  281. }
  282. static inline void mpic_map(struct mpic *mpic,
  283. phys_addr_t phys_addr, struct mpic_reg_bank *rb,
  284. unsigned int offset, unsigned int size)
  285. {
  286. if (mpic->flags & MPIC_USES_DCR)
  287. _mpic_map_dcr(mpic, rb, offset, size);
  288. else
  289. _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
  290. }
  291. #else /* CONFIG_PPC_DCR */
  292. #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
  293. #endif /* !CONFIG_PPC_DCR */
  294. /* Check if we have one of those nice broken MPICs with a flipped endian on
  295. * reads from IPI registers
  296. */
  297. static void __init mpic_test_broken_ipi(struct mpic *mpic)
  298. {
  299. u32 r;
  300. mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
  301. r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
  302. if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
  303. printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
  304. mpic->flags |= MPIC_BROKEN_IPI;
  305. }
  306. }
  307. #ifdef CONFIG_MPIC_U3_HT_IRQS
  308. /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
  309. * to force the edge setting on the MPIC and do the ack workaround.
  310. */
  311. static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
  312. {
  313. if (source >= 128 || !mpic->fixups)
  314. return 0;
  315. return mpic->fixups[source].base != NULL;
  316. }
  317. static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
  318. {
  319. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  320. if (fixup->applebase) {
  321. unsigned int soff = (fixup->index >> 3) & ~3;
  322. unsigned int mask = 1U << (fixup->index & 0x1f);
  323. writel(mask, fixup->applebase + soff);
  324. } else {
  325. raw_spin_lock(&mpic->fixup_lock);
  326. writeb(0x11 + 2 * fixup->index, fixup->base + 2);
  327. writel(fixup->data, fixup->base + 4);
  328. raw_spin_unlock(&mpic->fixup_lock);
  329. }
  330. }
  331. static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
  332. bool level)
  333. {
  334. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  335. unsigned long flags;
  336. u32 tmp;
  337. if (fixup->base == NULL)
  338. return;
  339. DBG("startup_ht_interrupt(0x%x) index: %d\n",
  340. source, fixup->index);
  341. raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
  342. /* Enable and configure */
  343. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  344. tmp = readl(fixup->base + 4);
  345. tmp &= ~(0x23U);
  346. if (level)
  347. tmp |= 0x22;
  348. writel(tmp, fixup->base + 4);
  349. raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
  350. #ifdef CONFIG_PM
  351. /* use the lowest bit inverted to the actual HW,
  352. * set if this fixup was enabled, clear otherwise */
  353. mpic->save_data[source].fixup_data = tmp | 1;
  354. #endif
  355. }
  356. static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
  357. {
  358. struct mpic_irq_fixup *fixup = &mpic->fixups[source];
  359. unsigned long flags;
  360. u32 tmp;
  361. if (fixup->base == NULL)
  362. return;
  363. DBG("shutdown_ht_interrupt(0x%x)\n", source);
  364. /* Disable */
  365. raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
  366. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  367. tmp = readl(fixup->base + 4);
  368. tmp |= 1;
  369. writel(tmp, fixup->base + 4);
  370. raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
  371. #ifdef CONFIG_PM
  372. /* use the lowest bit inverted to the actual HW,
  373. * set if this fixup was enabled, clear otherwise */
  374. mpic->save_data[source].fixup_data = tmp & ~1;
  375. #endif
  376. }
  377. #ifdef CONFIG_PCI_MSI
  378. static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
  379. unsigned int devfn)
  380. {
  381. u8 __iomem *base;
  382. u8 pos, flags;
  383. u64 addr = 0;
  384. for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
  385. pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
  386. u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
  387. if (id == PCI_CAP_ID_HT) {
  388. id = readb(devbase + pos + 3);
  389. if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
  390. break;
  391. }
  392. }
  393. if (pos == 0)
  394. return;
  395. base = devbase + pos;
  396. flags = readb(base + HT_MSI_FLAGS);
  397. if (!(flags & HT_MSI_FLAGS_FIXED)) {
  398. addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
  399. addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
  400. }
  401. printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
  402. PCI_SLOT(devfn), PCI_FUNC(devfn),
  403. flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
  404. if (!(flags & HT_MSI_FLAGS_ENABLE))
  405. writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
  406. }
  407. #else
  408. static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
  409. unsigned int devfn)
  410. {
  411. return;
  412. }
  413. #endif
  414. static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
  415. unsigned int devfn, u32 vdid)
  416. {
  417. int i, irq, n;
  418. u8 __iomem *base;
  419. u32 tmp;
  420. u8 pos;
  421. for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
  422. pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
  423. u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
  424. if (id == PCI_CAP_ID_HT) {
  425. id = readb(devbase + pos + 3);
  426. if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
  427. break;
  428. }
  429. }
  430. if (pos == 0)
  431. return;
  432. base = devbase + pos;
  433. writeb(0x01, base + 2);
  434. n = (readl(base + 4) >> 16) & 0xff;
  435. printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
  436. " has %d irqs\n",
  437. devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
  438. for (i = 0; i <= n; i++) {
  439. writeb(0x10 + 2 * i, base + 2);
  440. tmp = readl(base + 4);
  441. irq = (tmp >> 16) & 0xff;
  442. DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
  443. /* mask it , will be unmasked later */
  444. tmp |= 0x1;
  445. writel(tmp, base + 4);
  446. mpic->fixups[irq].index = i;
  447. mpic->fixups[irq].base = base;
  448. /* Apple HT PIC has a non-standard way of doing EOIs */
  449. if ((vdid & 0xffff) == 0x106b)
  450. mpic->fixups[irq].applebase = devbase + 0x60;
  451. else
  452. mpic->fixups[irq].applebase = NULL;
  453. writeb(0x11 + 2 * i, base + 2);
  454. mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
  455. }
  456. }
  457. static void __init mpic_scan_ht_pics(struct mpic *mpic)
  458. {
  459. unsigned int devfn;
  460. u8 __iomem *cfgspace;
  461. printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
  462. /* Allocate fixups array */
  463. mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL);
  464. BUG_ON(mpic->fixups == NULL);
  465. /* Init spinlock */
  466. raw_spin_lock_init(&mpic->fixup_lock);
  467. /* Map U3 config space. We assume all IO-APICs are on the primary bus
  468. * so we only need to map 64kB.
  469. */
  470. cfgspace = ioremap(0xf2000000, 0x10000);
  471. BUG_ON(cfgspace == NULL);
  472. /* Now we scan all slots. We do a very quick scan, we read the header
  473. * type, vendor ID and device ID only, that's plenty enough
  474. */
  475. for (devfn = 0; devfn < 0x100; devfn++) {
  476. u8 __iomem *devbase = cfgspace + (devfn << 8);
  477. u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
  478. u32 l = readl(devbase + PCI_VENDOR_ID);
  479. u16 s;
  480. DBG("devfn %x, l: %x\n", devfn, l);
  481. /* If no device, skip */
  482. if (l == 0xffffffff || l == 0x00000000 ||
  483. l == 0x0000ffff || l == 0xffff0000)
  484. goto next;
  485. /* Check if is supports capability lists */
  486. s = readw(devbase + PCI_STATUS);
  487. if (!(s & PCI_STATUS_CAP_LIST))
  488. goto next;
  489. mpic_scan_ht_pic(mpic, devbase, devfn, l);
  490. mpic_scan_ht_msi(mpic, devbase, devfn);
  491. next:
  492. /* next device, if function 0 */
  493. if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
  494. devfn += 7;
  495. }
  496. }
  497. #else /* CONFIG_MPIC_U3_HT_IRQS */
  498. static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
  499. {
  500. return 0;
  501. }
  502. static void __init mpic_scan_ht_pics(struct mpic *mpic)
  503. {
  504. }
  505. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  506. /* Find an mpic associated with a given linux interrupt */
  507. static struct mpic *mpic_find(unsigned int irq)
  508. {
  509. if (irq < NR_IRQS_LEGACY)
  510. return NULL;
  511. return irq_get_chip_data(irq);
  512. }
  513. /* Determine if the linux irq is an IPI */
  514. static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
  515. {
  516. return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
  517. }
  518. /* Determine if the linux irq is a timer */
  519. static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
  520. {
  521. return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
  522. }
  523. /* Convert a cpu mask from logical to physical cpu numbers. */
  524. static inline u32 mpic_physmask(u32 cpumask)
  525. {
  526. int i;
  527. u32 mask = 0;
  528. for (i = 0; i < min(32, NR_CPUS) && cpu_possible(i); ++i, cpumask >>= 1)
  529. mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
  530. return mask;
  531. }
  532. #ifdef CONFIG_SMP
  533. /* Get the mpic structure from the IPI number */
  534. static inline struct mpic * mpic_from_ipi(struct irq_data *d)
  535. {
  536. return irq_data_get_irq_chip_data(d);
  537. }
  538. #endif
  539. /* Get the mpic structure from the irq number */
  540. static inline struct mpic * mpic_from_irq(unsigned int irq)
  541. {
  542. return irq_get_chip_data(irq);
  543. }
  544. /* Get the mpic structure from the irq data */
  545. static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
  546. {
  547. return irq_data_get_irq_chip_data(d);
  548. }
  549. /* Send an EOI */
  550. static inline void mpic_eoi(struct mpic *mpic)
  551. {
  552. mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
  553. }
  554. /*
  555. * Linux descriptor level callbacks
  556. */
  557. void mpic_unmask_irq(struct irq_data *d)
  558. {
  559. unsigned int loops = 100000;
  560. struct mpic *mpic = mpic_from_irq_data(d);
  561. unsigned int src = irqd_to_hwirq(d);
  562. DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
  563. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  564. mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
  565. ~MPIC_VECPRI_MASK);
  566. /* make sure mask gets to controller before we return to user */
  567. do {
  568. if (!loops--) {
  569. printk(KERN_ERR "%s: timeout on hwirq %u\n",
  570. __func__, src);
  571. break;
  572. }
  573. } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
  574. }
  575. void mpic_mask_irq(struct irq_data *d)
  576. {
  577. unsigned int loops = 100000;
  578. struct mpic *mpic = mpic_from_irq_data(d);
  579. unsigned int src = irqd_to_hwirq(d);
  580. DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
  581. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  582. mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
  583. MPIC_VECPRI_MASK);
  584. /* make sure mask gets to controller before we return to user */
  585. do {
  586. if (!loops--) {
  587. printk(KERN_ERR "%s: timeout on hwirq %u\n",
  588. __func__, src);
  589. break;
  590. }
  591. } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
  592. }
  593. void mpic_end_irq(struct irq_data *d)
  594. {
  595. struct mpic *mpic = mpic_from_irq_data(d);
  596. #ifdef DEBUG_IRQ
  597. DBG("%s: end_irq: %d\n", mpic->name, d->irq);
  598. #endif
  599. /* We always EOI on end_irq() even for edge interrupts since that
  600. * should only lower the priority, the MPIC should have properly
  601. * latched another edge interrupt coming in anyway
  602. */
  603. mpic_eoi(mpic);
  604. }
  605. #ifdef CONFIG_MPIC_U3_HT_IRQS
  606. static void mpic_unmask_ht_irq(struct irq_data *d)
  607. {
  608. struct mpic *mpic = mpic_from_irq_data(d);
  609. unsigned int src = irqd_to_hwirq(d);
  610. mpic_unmask_irq(d);
  611. if (irqd_is_level_type(d))
  612. mpic_ht_end_irq(mpic, src);
  613. }
  614. static unsigned int mpic_startup_ht_irq(struct irq_data *d)
  615. {
  616. struct mpic *mpic = mpic_from_irq_data(d);
  617. unsigned int src = irqd_to_hwirq(d);
  618. mpic_unmask_irq(d);
  619. mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
  620. return 0;
  621. }
  622. static void mpic_shutdown_ht_irq(struct irq_data *d)
  623. {
  624. struct mpic *mpic = mpic_from_irq_data(d);
  625. unsigned int src = irqd_to_hwirq(d);
  626. mpic_shutdown_ht_interrupt(mpic, src);
  627. mpic_mask_irq(d);
  628. }
  629. static void mpic_end_ht_irq(struct irq_data *d)
  630. {
  631. struct mpic *mpic = mpic_from_irq_data(d);
  632. unsigned int src = irqd_to_hwirq(d);
  633. #ifdef DEBUG_IRQ
  634. DBG("%s: end_irq: %d\n", mpic->name, d->irq);
  635. #endif
  636. /* We always EOI on end_irq() even for edge interrupts since that
  637. * should only lower the priority, the MPIC should have properly
  638. * latched another edge interrupt coming in anyway
  639. */
  640. if (irqd_is_level_type(d))
  641. mpic_ht_end_irq(mpic, src);
  642. mpic_eoi(mpic);
  643. }
  644. #endif /* !CONFIG_MPIC_U3_HT_IRQS */
  645. #ifdef CONFIG_SMP
  646. static void mpic_unmask_ipi(struct irq_data *d)
  647. {
  648. struct mpic *mpic = mpic_from_ipi(d);
  649. unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
  650. DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
  651. mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
  652. }
  653. static void mpic_mask_ipi(struct irq_data *d)
  654. {
  655. /* NEVER disable an IPI... that's just plain wrong! */
  656. }
  657. static void mpic_end_ipi(struct irq_data *d)
  658. {
  659. struct mpic *mpic = mpic_from_ipi(d);
  660. /*
  661. * IPIs are marked IRQ_PER_CPU. This has the side effect of
  662. * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
  663. * applying to them. We EOI them late to avoid re-entering.
  664. */
  665. mpic_eoi(mpic);
  666. }
  667. #endif /* CONFIG_SMP */
  668. static void mpic_unmask_tm(struct irq_data *d)
  669. {
  670. struct mpic *mpic = mpic_from_irq_data(d);
  671. unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
  672. DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
  673. mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
  674. mpic_tm_read(src);
  675. }
  676. static void mpic_mask_tm(struct irq_data *d)
  677. {
  678. struct mpic *mpic = mpic_from_irq_data(d);
  679. unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
  680. mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
  681. mpic_tm_read(src);
  682. }
  683. int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
  684. bool force)
  685. {
  686. struct mpic *mpic = mpic_from_irq_data(d);
  687. unsigned int src = irqd_to_hwirq(d);
  688. if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
  689. int cpuid = irq_choose_cpu(cpumask);
  690. mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
  691. } else {
  692. u32 mask = cpumask_bits(cpumask)[0];
  693. mask &= cpumask_bits(cpu_online_mask)[0];
  694. mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
  695. mpic_physmask(mask));
  696. }
  697. return IRQ_SET_MASK_OK;
  698. }
  699. static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
  700. {
  701. /* Now convert sense value */
  702. switch(type & IRQ_TYPE_SENSE_MASK) {
  703. case IRQ_TYPE_EDGE_RISING:
  704. return MPIC_INFO(VECPRI_SENSE_EDGE) |
  705. MPIC_INFO(VECPRI_POLARITY_POSITIVE);
  706. case IRQ_TYPE_EDGE_FALLING:
  707. case IRQ_TYPE_EDGE_BOTH:
  708. return MPIC_INFO(VECPRI_SENSE_EDGE) |
  709. MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
  710. case IRQ_TYPE_LEVEL_HIGH:
  711. return MPIC_INFO(VECPRI_SENSE_LEVEL) |
  712. MPIC_INFO(VECPRI_POLARITY_POSITIVE);
  713. case IRQ_TYPE_LEVEL_LOW:
  714. default:
  715. return MPIC_INFO(VECPRI_SENSE_LEVEL) |
  716. MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
  717. }
  718. }
  719. int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
  720. {
  721. struct mpic *mpic = mpic_from_irq_data(d);
  722. unsigned int src = irqd_to_hwirq(d);
  723. unsigned int vecpri, vold, vnew;
  724. DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
  725. mpic, d->irq, src, flow_type);
  726. if (src >= mpic->num_sources)
  727. return -EINVAL;
  728. vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
  729. /* We don't support "none" type */
  730. if (flow_type == IRQ_TYPE_NONE)
  731. flow_type = IRQ_TYPE_DEFAULT;
  732. /* Default: read HW settings */
  733. if (flow_type == IRQ_TYPE_DEFAULT) {
  734. int vold_ps;
  735. vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
  736. MPIC_INFO(VECPRI_SENSE_MASK));
  737. if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
  738. MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
  739. flow_type = IRQ_TYPE_EDGE_RISING;
  740. else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
  741. MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
  742. flow_type = IRQ_TYPE_EDGE_FALLING;
  743. else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
  744. MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
  745. flow_type = IRQ_TYPE_LEVEL_HIGH;
  746. else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
  747. MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
  748. flow_type = IRQ_TYPE_LEVEL_LOW;
  749. else
  750. WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
  751. }
  752. /* Apply to irq desc */
  753. irqd_set_trigger_type(d, flow_type);
  754. /* Apply to HW */
  755. if (mpic_is_ht_interrupt(mpic, src))
  756. vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
  757. MPIC_VECPRI_SENSE_EDGE;
  758. else
  759. vecpri = mpic_type_to_vecpri(mpic, flow_type);
  760. vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
  761. MPIC_INFO(VECPRI_SENSE_MASK));
  762. vnew |= vecpri;
  763. if (vold != vnew)
  764. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
  765. return IRQ_SET_MASK_OK_NOCOPY;
  766. }
  767. void mpic_set_vector(unsigned int virq, unsigned int vector)
  768. {
  769. struct mpic *mpic = mpic_from_irq(virq);
  770. unsigned int src = virq_to_hw(virq);
  771. unsigned int vecpri;
  772. DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
  773. mpic, virq, src, vector);
  774. if (src >= mpic->num_sources)
  775. return;
  776. vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
  777. vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
  778. vecpri |= vector;
  779. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
  780. }
  781. static void mpic_set_destination(unsigned int virq, unsigned int cpuid)
  782. {
  783. struct mpic *mpic = mpic_from_irq(virq);
  784. unsigned int src = virq_to_hw(virq);
  785. DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
  786. mpic, virq, src, cpuid);
  787. if (src >= mpic->num_sources)
  788. return;
  789. mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
  790. }
  791. static struct irq_chip mpic_irq_chip = {
  792. .irq_mask = mpic_mask_irq,
  793. .irq_unmask = mpic_unmask_irq,
  794. .irq_eoi = mpic_end_irq,
  795. .irq_set_type = mpic_set_irq_type,
  796. };
  797. #ifdef CONFIG_SMP
  798. static const struct irq_chip mpic_ipi_chip = {
  799. .irq_mask = mpic_mask_ipi,
  800. .irq_unmask = mpic_unmask_ipi,
  801. .irq_eoi = mpic_end_ipi,
  802. };
  803. #endif /* CONFIG_SMP */
  804. static struct irq_chip mpic_tm_chip = {
  805. .irq_mask = mpic_mask_tm,
  806. .irq_unmask = mpic_unmask_tm,
  807. .irq_eoi = mpic_end_irq,
  808. };
  809. #ifdef CONFIG_MPIC_U3_HT_IRQS
  810. static const struct irq_chip mpic_irq_ht_chip = {
  811. .irq_startup = mpic_startup_ht_irq,
  812. .irq_shutdown = mpic_shutdown_ht_irq,
  813. .irq_mask = mpic_mask_irq,
  814. .irq_unmask = mpic_unmask_ht_irq,
  815. .irq_eoi = mpic_end_ht_irq,
  816. .irq_set_type = mpic_set_irq_type,
  817. };
  818. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  819. static int mpic_host_match(struct irq_domain *h, struct device_node *node,
  820. enum irq_domain_bus_token bus_token)
  821. {
  822. /* Exact match, unless mpic node is NULL */
  823. struct device_node *of_node = irq_domain_get_of_node(h);
  824. return of_node == NULL || of_node == node;
  825. }
  826. static int mpic_host_map(struct irq_domain *h, unsigned int virq,
  827. irq_hw_number_t hw)
  828. {
  829. struct mpic *mpic = h->host_data;
  830. struct irq_chip *chip;
  831. DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
  832. if (hw == mpic->spurious_vec)
  833. return -EINVAL;
  834. if (mpic->protected && test_bit(hw, mpic->protected)) {
  835. pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n",
  836. (unsigned int)hw);
  837. return -EPERM;
  838. }
  839. #ifdef CONFIG_SMP
  840. else if (hw >= mpic->ipi_vecs[0]) {
  841. WARN_ON(mpic->flags & MPIC_SECONDARY);
  842. DBG("mpic: mapping as IPI\n");
  843. irq_set_chip_data(virq, mpic);
  844. irq_set_chip_and_handler(virq, &mpic->hc_ipi,
  845. handle_percpu_irq);
  846. return 0;
  847. }
  848. #endif /* CONFIG_SMP */
  849. if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
  850. WARN_ON(mpic->flags & MPIC_SECONDARY);
  851. DBG("mpic: mapping as timer\n");
  852. irq_set_chip_data(virq, mpic);
  853. irq_set_chip_and_handler(virq, &mpic->hc_tm,
  854. handle_fasteoi_irq);
  855. return 0;
  856. }
  857. if (mpic_map_error_int(mpic, virq, hw))
  858. return 0;
  859. if (hw >= mpic->num_sources) {
  860. pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n",
  861. (unsigned int)hw);
  862. return -EINVAL;
  863. }
  864. mpic_msi_reserve_hwirq(mpic, hw);
  865. /* Default chip */
  866. chip = &mpic->hc_irq;
  867. #ifdef CONFIG_MPIC_U3_HT_IRQS
  868. /* Check for HT interrupts, override vecpri */
  869. if (mpic_is_ht_interrupt(mpic, hw))
  870. chip = &mpic->hc_ht_irq;
  871. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  872. DBG("mpic: mapping to irq chip @%p\n", chip);
  873. irq_set_chip_data(virq, mpic);
  874. irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
  875. /* Set default irq type */
  876. irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
  877. /* If the MPIC was reset, then all vectors have already been
  878. * initialized. Otherwise, a per source lazy initialization
  879. * is done here.
  880. */
  881. if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
  882. int cpu;
  883. preempt_disable();
  884. cpu = mpic_processor_id(mpic);
  885. preempt_enable();
  886. mpic_set_vector(virq, hw);
  887. mpic_set_destination(virq, cpu);
  888. mpic_irq_set_priority(virq, 8);
  889. }
  890. return 0;
  891. }
  892. static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
  893. const u32 *intspec, unsigned int intsize,
  894. irq_hw_number_t *out_hwirq, unsigned int *out_flags)
  895. {
  896. struct mpic *mpic = h->host_data;
  897. static unsigned char map_mpic_senses[4] = {
  898. IRQ_TYPE_EDGE_RISING,
  899. IRQ_TYPE_LEVEL_LOW,
  900. IRQ_TYPE_LEVEL_HIGH,
  901. IRQ_TYPE_EDGE_FALLING,
  902. };
  903. *out_hwirq = intspec[0];
  904. if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
  905. /*
  906. * Freescale MPIC with extended intspec:
  907. * First two cells are as usual. Third specifies
  908. * an "interrupt type". Fourth is type-specific data.
  909. *
  910. * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
  911. */
  912. switch (intspec[2]) {
  913. case 0:
  914. break;
  915. case 1:
  916. if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
  917. break;
  918. if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
  919. return -EINVAL;
  920. *out_hwirq = mpic->err_int_vecs[intspec[3]];
  921. break;
  922. case 2:
  923. if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
  924. return -EINVAL;
  925. *out_hwirq = mpic->ipi_vecs[intspec[0]];
  926. break;
  927. case 3:
  928. if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
  929. return -EINVAL;
  930. *out_hwirq = mpic->timer_vecs[intspec[0]];
  931. break;
  932. default:
  933. pr_debug("%s: unknown irq type %u\n",
  934. __func__, intspec[2]);
  935. return -EINVAL;
  936. }
  937. *out_flags = map_mpic_senses[intspec[1] & 3];
  938. } else if (intsize > 1) {
  939. u32 mask = 0x3;
  940. /* Apple invented a new race of encoding on machines with
  941. * an HT APIC. They encode, among others, the index within
  942. * the HT APIC. We don't care about it here since thankfully,
  943. * it appears that they have the APIC already properly
  944. * configured, and thus our current fixup code that reads the
  945. * APIC config works fine. However, we still need to mask out
  946. * bits in the specifier to make sure we only get bit 0 which
  947. * is the level/edge bit (the only sense bit exposed by Apple),
  948. * as their bit 1 means something else.
  949. */
  950. if (machine_is(powermac))
  951. mask = 0x1;
  952. *out_flags = map_mpic_senses[intspec[1] & mask];
  953. } else
  954. *out_flags = IRQ_TYPE_NONE;
  955. DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
  956. intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
  957. return 0;
  958. }
  959. /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
  960. static void mpic_cascade(struct irq_desc *desc)
  961. {
  962. struct irq_chip *chip = irq_desc_get_chip(desc);
  963. struct mpic *mpic = irq_desc_get_handler_data(desc);
  964. unsigned int virq;
  965. BUG_ON(!(mpic->flags & MPIC_SECONDARY));
  966. virq = mpic_get_one_irq(mpic);
  967. if (virq)
  968. generic_handle_irq(virq);
  969. chip->irq_eoi(&desc->irq_data);
  970. }
  971. static const struct irq_domain_ops mpic_host_ops = {
  972. .match = mpic_host_match,
  973. .map = mpic_host_map,
  974. .xlate = mpic_host_xlate,
  975. };
  976. static u32 fsl_mpic_get_version(struct mpic *mpic)
  977. {
  978. u32 brr1;
  979. if (!(mpic->flags & MPIC_FSL))
  980. return 0;
  981. brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
  982. MPIC_FSL_BRR1);
  983. return brr1 & MPIC_FSL_BRR1_VER;
  984. }
  985. /*
  986. * Exported functions
  987. */
  988. u32 fsl_mpic_primary_get_version(void)
  989. {
  990. struct mpic *mpic = mpic_primary;
  991. if (mpic)
  992. return fsl_mpic_get_version(mpic);
  993. return 0;
  994. }
  995. struct mpic * __init mpic_alloc(struct device_node *node,
  996. phys_addr_t phys_addr,
  997. unsigned int flags,
  998. unsigned int isu_size,
  999. unsigned int irq_count,
  1000. const char *name)
  1001. {
  1002. int i, psize, intvec_top;
  1003. struct mpic *mpic;
  1004. u32 greg_feature;
  1005. const char *vers;
  1006. const u32 *psrc;
  1007. u32 last_irq;
  1008. u32 fsl_version = 0;
  1009. /* Default MPIC search parameters */
  1010. static const struct of_device_id __initconst mpic_device_id[] = {
  1011. { .type = "open-pic", },
  1012. { .compatible = "open-pic", },
  1013. {},
  1014. };
  1015. /*
  1016. * If we were not passed a device-tree node, then perform the default
  1017. * search for standardized a standardized OpenPIC.
  1018. */
  1019. if (node) {
  1020. node = of_node_get(node);
  1021. } else {
  1022. node = of_find_matching_node(NULL, mpic_device_id);
  1023. if (!node)
  1024. return NULL;
  1025. }
  1026. /* Pick the physical address from the device tree if unspecified */
  1027. if (!phys_addr) {
  1028. /* Check if it is DCR-based */
  1029. if (of_property_read_bool(node, "dcr-reg")) {
  1030. flags |= MPIC_USES_DCR;
  1031. } else {
  1032. struct resource r;
  1033. if (of_address_to_resource(node, 0, &r))
  1034. goto err_of_node_put;
  1035. phys_addr = r.start;
  1036. }
  1037. }
  1038. /* Read extra device-tree properties into the flags variable */
  1039. if (of_get_property(node, "big-endian", NULL))
  1040. flags |= MPIC_BIG_ENDIAN;
  1041. if (of_get_property(node, "pic-no-reset", NULL))
  1042. flags |= MPIC_NO_RESET;
  1043. if (of_get_property(node, "single-cpu-affinity", NULL))
  1044. flags |= MPIC_SINGLE_DEST_CPU;
  1045. if (of_device_is_compatible(node, "fsl,mpic")) {
  1046. flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
  1047. mpic_irq_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
  1048. mpic_tm_chip.flags |= IRQCHIP_SKIP_SET_WAKE;
  1049. }
  1050. mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
  1051. if (mpic == NULL)
  1052. goto err_of_node_put;
  1053. mpic->name = name;
  1054. mpic->node = node;
  1055. mpic->paddr = phys_addr;
  1056. mpic->flags = flags;
  1057. mpic->hc_irq = mpic_irq_chip;
  1058. mpic->hc_irq.name = name;
  1059. if (!(mpic->flags & MPIC_SECONDARY))
  1060. mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
  1061. #ifdef CONFIG_MPIC_U3_HT_IRQS
  1062. mpic->hc_ht_irq = mpic_irq_ht_chip;
  1063. mpic->hc_ht_irq.name = name;
  1064. if (!(mpic->flags & MPIC_SECONDARY))
  1065. mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
  1066. #endif /* CONFIG_MPIC_U3_HT_IRQS */
  1067. #ifdef CONFIG_SMP
  1068. mpic->hc_ipi = mpic_ipi_chip;
  1069. mpic->hc_ipi.name = name;
  1070. #endif /* CONFIG_SMP */
  1071. mpic->hc_tm = mpic_tm_chip;
  1072. mpic->hc_tm.name = name;
  1073. mpic->num_sources = 0; /* so far */
  1074. if (mpic->flags & MPIC_LARGE_VECTORS)
  1075. intvec_top = 2047;
  1076. else
  1077. intvec_top = 255;
  1078. mpic->timer_vecs[0] = intvec_top - 12;
  1079. mpic->timer_vecs[1] = intvec_top - 11;
  1080. mpic->timer_vecs[2] = intvec_top - 10;
  1081. mpic->timer_vecs[3] = intvec_top - 9;
  1082. mpic->timer_vecs[4] = intvec_top - 8;
  1083. mpic->timer_vecs[5] = intvec_top - 7;
  1084. mpic->timer_vecs[6] = intvec_top - 6;
  1085. mpic->timer_vecs[7] = intvec_top - 5;
  1086. mpic->ipi_vecs[0] = intvec_top - 4;
  1087. mpic->ipi_vecs[1] = intvec_top - 3;
  1088. mpic->ipi_vecs[2] = intvec_top - 2;
  1089. mpic->ipi_vecs[3] = intvec_top - 1;
  1090. mpic->spurious_vec = intvec_top;
  1091. /* Look for protected sources */
  1092. psrc = of_get_property(mpic->node, "protected-sources", &psize);
  1093. if (psrc) {
  1094. /* Allocate a bitmap with one bit per interrupt */
  1095. mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL);
  1096. BUG_ON(mpic->protected == NULL);
  1097. for (i = 0; i < psize/sizeof(u32); i++) {
  1098. if (psrc[i] > intvec_top)
  1099. continue;
  1100. __set_bit(psrc[i], mpic->protected);
  1101. }
  1102. }
  1103. #ifdef CONFIG_MPIC_WEIRD
  1104. mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
  1105. #endif
  1106. /* default register type */
  1107. if (mpic->flags & MPIC_BIG_ENDIAN)
  1108. mpic->reg_type = mpic_access_mmio_be;
  1109. else
  1110. mpic->reg_type = mpic_access_mmio_le;
  1111. /*
  1112. * An MPIC with a "dcr-reg" property must be accessed that way, but
  1113. * only if the kernel includes DCR support.
  1114. */
  1115. #ifdef CONFIG_PPC_DCR
  1116. if (mpic->flags & MPIC_USES_DCR)
  1117. mpic->reg_type = mpic_access_dcr;
  1118. #else
  1119. BUG_ON(mpic->flags & MPIC_USES_DCR);
  1120. #endif
  1121. /* Map the global registers */
  1122. mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
  1123. mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
  1124. if (mpic->flags & MPIC_FSL) {
  1125. int ret;
  1126. /*
  1127. * Yes, Freescale really did put global registers in the
  1128. * magic per-cpu area -- and they don't even show up in the
  1129. * non-magic per-cpu copies that this driver normally uses.
  1130. */
  1131. mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
  1132. MPIC_CPU_THISBASE, 0x1000);
  1133. fsl_version = fsl_mpic_get_version(mpic);
  1134. /* Error interrupt mask register (EIMR) is required for
  1135. * handling individual device error interrupts. EIMR
  1136. * was added in MPIC version 4.1.
  1137. *
  1138. * Over here we reserve vector number space for error
  1139. * interrupt vectors. This space is stolen from the
  1140. * global vector number space, as in case of ipis
  1141. * and timer interrupts.
  1142. *
  1143. * Available vector space = intvec_top - 13, where 13
  1144. * is the number of vectors which have been consumed by
  1145. * ipis, timer interrupts and spurious.
  1146. */
  1147. if (fsl_version >= 0x401) {
  1148. ret = mpic_setup_error_int(mpic, intvec_top - 13);
  1149. if (ret)
  1150. return NULL;
  1151. }
  1152. }
  1153. /*
  1154. * EPR is only available starting with v4.0. To support
  1155. * platforms that don't know the MPIC version at compile-time,
  1156. * such as qemu-e500, turn off coreint if this MPIC doesn't
  1157. * support it. Note that we never enable it if it wasn't
  1158. * requested in the first place.
  1159. *
  1160. * This is done outside the MPIC_FSL check, so that we
  1161. * also disable coreint if the MPIC node doesn't have
  1162. * an "fsl,mpic" compatible at all. This will be the case
  1163. * with device trees generated by older versions of QEMU.
  1164. * fsl_version will be zero if MPIC_FSL is not set.
  1165. */
  1166. if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT))
  1167. ppc_md.get_irq = mpic_get_irq;
  1168. /* Reset */
  1169. /* When using a device-node, reset requests are only honored if the MPIC
  1170. * is allowed to reset.
  1171. */
  1172. if (!(mpic->flags & MPIC_NO_RESET)) {
  1173. printk(KERN_DEBUG "mpic: Resetting\n");
  1174. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1175. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1176. | MPIC_GREG_GCONF_RESET);
  1177. while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1178. & MPIC_GREG_GCONF_RESET)
  1179. mb();
  1180. }
  1181. /* CoreInt */
  1182. if (mpic->flags & MPIC_ENABLE_COREINT)
  1183. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1184. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1185. | MPIC_GREG_GCONF_COREINT);
  1186. if (mpic->flags & MPIC_ENABLE_MCK)
  1187. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1188. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1189. | MPIC_GREG_GCONF_MCK);
  1190. /*
  1191. * The MPIC driver will crash if there are more cores than we
  1192. * can initialize, so we may as well catch that problem here.
  1193. */
  1194. BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
  1195. /* Map the per-CPU registers */
  1196. for_each_possible_cpu(i) {
  1197. unsigned int cpu = get_hard_smp_processor_id(i);
  1198. mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
  1199. MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
  1200. 0x1000);
  1201. }
  1202. /*
  1203. * Read feature register. For non-ISU MPICs, num sources as well. On
  1204. * ISU MPICs, sources are counted as ISUs are added
  1205. */
  1206. greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
  1207. /*
  1208. * By default, the last source number comes from the MPIC, but the
  1209. * device-tree and board support code can override it on buggy hw.
  1210. * If we get passed an isu_size (multi-isu MPIC) then we use that
  1211. * as a default instead of the value read from the HW.
  1212. */
  1213. last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
  1214. >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
  1215. if (isu_size)
  1216. last_irq = isu_size * MPIC_MAX_ISU - 1;
  1217. of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
  1218. if (irq_count)
  1219. last_irq = irq_count - 1;
  1220. /* Initialize main ISU if none provided */
  1221. if (!isu_size) {
  1222. isu_size = last_irq + 1;
  1223. mpic->num_sources = isu_size;
  1224. mpic_map(mpic, mpic->paddr, &mpic->isus[0],
  1225. MPIC_INFO(IRQ_BASE),
  1226. MPIC_INFO(IRQ_STRIDE) * isu_size);
  1227. }
  1228. mpic->isu_size = isu_size;
  1229. mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
  1230. mpic->isu_mask = (1 << mpic->isu_shift) - 1;
  1231. mpic->irqhost = irq_domain_add_linear(mpic->node,
  1232. intvec_top,
  1233. &mpic_host_ops, mpic);
  1234. /*
  1235. * FIXME: The code leaks the MPIC object and mappings here; this
  1236. * is very unlikely to fail but it ought to be fixed anyways.
  1237. */
  1238. if (mpic->irqhost == NULL)
  1239. return NULL;
  1240. /* Display version */
  1241. switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
  1242. case 1:
  1243. vers = "1.0";
  1244. break;
  1245. case 2:
  1246. vers = "1.2";
  1247. break;
  1248. case 3:
  1249. vers = "1.3";
  1250. break;
  1251. default:
  1252. vers = "<unknown>";
  1253. break;
  1254. }
  1255. printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
  1256. " max %d CPUs\n",
  1257. name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
  1258. printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
  1259. mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
  1260. mpic->next = mpics;
  1261. mpics = mpic;
  1262. if (!(mpic->flags & MPIC_SECONDARY)) {
  1263. mpic_primary = mpic;
  1264. irq_set_default_host(mpic->irqhost);
  1265. }
  1266. return mpic;
  1267. err_of_node_put:
  1268. of_node_put(node);
  1269. return NULL;
  1270. }
  1271. void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
  1272. phys_addr_t paddr)
  1273. {
  1274. unsigned int isu_first = isu_num * mpic->isu_size;
  1275. BUG_ON(isu_num >= MPIC_MAX_ISU);
  1276. mpic_map(mpic,
  1277. paddr, &mpic->isus[isu_num], 0,
  1278. MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
  1279. if ((isu_first + mpic->isu_size) > mpic->num_sources)
  1280. mpic->num_sources = isu_first + mpic->isu_size;
  1281. }
  1282. void __init mpic_init(struct mpic *mpic)
  1283. {
  1284. int i, cpu;
  1285. int num_timers = 4;
  1286. BUG_ON(mpic->num_sources == 0);
  1287. printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
  1288. /* Set current processor priority to max */
  1289. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
  1290. if (mpic->flags & MPIC_FSL) {
  1291. u32 version = fsl_mpic_get_version(mpic);
  1292. /*
  1293. * Timer group B is present at the latest in MPIC 3.1 (e.g.
  1294. * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
  1295. * I don't know about the status of intermediate versions (or
  1296. * whether they even exist).
  1297. */
  1298. if (version >= 0x0301)
  1299. num_timers = 8;
  1300. }
  1301. /* Initialize timers to our reserved vectors and mask them for now */
  1302. for (i = 0; i < num_timers; i++) {
  1303. unsigned int offset = mpic_tm_offset(mpic, i);
  1304. mpic_write(mpic->tmregs,
  1305. offset + MPIC_INFO(TIMER_DESTINATION),
  1306. 1 << hard_smp_processor_id());
  1307. mpic_write(mpic->tmregs,
  1308. offset + MPIC_INFO(TIMER_VECTOR_PRI),
  1309. MPIC_VECPRI_MASK |
  1310. (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
  1311. (mpic->timer_vecs[0] + i));
  1312. }
  1313. /* Initialize IPIs to our reserved vectors and mark them disabled for now */
  1314. mpic_test_broken_ipi(mpic);
  1315. for (i = 0; i < 4; i++) {
  1316. mpic_ipi_write(i,
  1317. MPIC_VECPRI_MASK |
  1318. (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
  1319. (mpic->ipi_vecs[0] + i));
  1320. }
  1321. /* Do the HT PIC fixups on U3 broken mpic */
  1322. DBG("MPIC flags: %x\n", mpic->flags);
  1323. if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
  1324. mpic_scan_ht_pics(mpic);
  1325. mpic_u3msi_init(mpic);
  1326. }
  1327. mpic_pasemi_msi_init(mpic);
  1328. cpu = mpic_processor_id(mpic);
  1329. if (!(mpic->flags & MPIC_NO_RESET)) {
  1330. for (i = 0; i < mpic->num_sources; i++) {
  1331. /* start with vector = source number, and masked */
  1332. u32 vecpri = MPIC_VECPRI_MASK | i |
  1333. (8 << MPIC_VECPRI_PRIORITY_SHIFT);
  1334. /* check if protected */
  1335. if (mpic->protected && test_bit(i, mpic->protected))
  1336. continue;
  1337. /* init hw */
  1338. mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
  1339. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
  1340. }
  1341. }
  1342. /* Init spurious vector */
  1343. mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
  1344. /* Disable 8259 passthrough, if supported */
  1345. if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
  1346. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1347. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1348. | MPIC_GREG_GCONF_8259_PTHROU_DIS);
  1349. if (mpic->flags & MPIC_NO_BIAS)
  1350. mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
  1351. mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
  1352. | MPIC_GREG_GCONF_NO_BIAS);
  1353. /* Set current processor priority to 0 */
  1354. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
  1355. #ifdef CONFIG_PM
  1356. /* allocate memory to save mpic state */
  1357. mpic->save_data = kmalloc_array(mpic->num_sources,
  1358. sizeof(*mpic->save_data),
  1359. GFP_KERNEL);
  1360. BUG_ON(mpic->save_data == NULL);
  1361. #endif
  1362. /* Check if this MPIC is chained from a parent interrupt controller */
  1363. if (mpic->flags & MPIC_SECONDARY) {
  1364. int virq = irq_of_parse_and_map(mpic->node, 0);
  1365. if (virq) {
  1366. printk(KERN_INFO "%pOF: hooking up to IRQ %d\n",
  1367. mpic->node, virq);
  1368. irq_set_handler_data(virq, mpic);
  1369. irq_set_chained_handler(virq, &mpic_cascade);
  1370. }
  1371. }
  1372. /* FSL mpic error interrupt initialization */
  1373. if (mpic->flags & MPIC_FSL_HAS_EIMR)
  1374. mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
  1375. }
  1376. void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
  1377. {
  1378. struct mpic *mpic = mpic_find(irq);
  1379. unsigned int src = virq_to_hw(irq);
  1380. unsigned long flags;
  1381. u32 reg;
  1382. if (!mpic)
  1383. return;
  1384. raw_spin_lock_irqsave(&mpic_lock, flags);
  1385. if (mpic_is_ipi(mpic, src)) {
  1386. reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
  1387. ~MPIC_VECPRI_PRIORITY_MASK;
  1388. mpic_ipi_write(src - mpic->ipi_vecs[0],
  1389. reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
  1390. } else if (mpic_is_tm(mpic, src)) {
  1391. reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
  1392. ~MPIC_VECPRI_PRIORITY_MASK;
  1393. mpic_tm_write(src - mpic->timer_vecs[0],
  1394. reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
  1395. } else {
  1396. reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
  1397. & ~MPIC_VECPRI_PRIORITY_MASK;
  1398. mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
  1399. reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
  1400. }
  1401. raw_spin_unlock_irqrestore(&mpic_lock, flags);
  1402. }
  1403. void mpic_setup_this_cpu(void)
  1404. {
  1405. #ifdef CONFIG_SMP
  1406. struct mpic *mpic = mpic_primary;
  1407. unsigned long flags;
  1408. u32 msk = 1 << hard_smp_processor_id();
  1409. unsigned int i;
  1410. BUG_ON(mpic == NULL);
  1411. DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
  1412. raw_spin_lock_irqsave(&mpic_lock, flags);
  1413. /* let the mpic know we want intrs. default affinity is 0xffffffff
  1414. * until changed via /proc. That's how it's done on x86. If we want
  1415. * it differently, then we should make sure we also change the default
  1416. * values of irq_desc[].affinity in irq.c.
  1417. */
  1418. if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
  1419. for (i = 0; i < mpic->num_sources ; i++)
  1420. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1421. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
  1422. }
  1423. /* Set current processor priority to 0 */
  1424. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
  1425. raw_spin_unlock_irqrestore(&mpic_lock, flags);
  1426. #endif /* CONFIG_SMP */
  1427. }
  1428. int mpic_cpu_get_priority(void)
  1429. {
  1430. struct mpic *mpic = mpic_primary;
  1431. return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
  1432. }
  1433. void mpic_cpu_set_priority(int prio)
  1434. {
  1435. struct mpic *mpic = mpic_primary;
  1436. prio &= MPIC_CPU_TASKPRI_MASK;
  1437. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
  1438. }
  1439. void mpic_teardown_this_cpu(int secondary)
  1440. {
  1441. struct mpic *mpic = mpic_primary;
  1442. unsigned long flags;
  1443. u32 msk = 1 << hard_smp_processor_id();
  1444. unsigned int i;
  1445. BUG_ON(mpic == NULL);
  1446. DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
  1447. raw_spin_lock_irqsave(&mpic_lock, flags);
  1448. /* let the mpic know we don't want intrs. */
  1449. for (i = 0; i < mpic->num_sources ; i++)
  1450. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1451. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
  1452. /* Set current processor priority to max */
  1453. mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
  1454. /* We need to EOI the IPI since not all platforms reset the MPIC
  1455. * on boot and new interrupts wouldn't get delivered otherwise.
  1456. */
  1457. mpic_eoi(mpic);
  1458. raw_spin_unlock_irqrestore(&mpic_lock, flags);
  1459. }
  1460. static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
  1461. {
  1462. u32 src;
  1463. src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
  1464. #ifdef DEBUG_LOW
  1465. DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
  1466. #endif
  1467. if (unlikely(src == mpic->spurious_vec)) {
  1468. if (mpic->flags & MPIC_SPV_EOI)
  1469. mpic_eoi(mpic);
  1470. return 0;
  1471. }
  1472. if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
  1473. printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
  1474. mpic->name, (int)src);
  1475. mpic_eoi(mpic);
  1476. return 0;
  1477. }
  1478. return irq_linear_revmap(mpic->irqhost, src);
  1479. }
  1480. unsigned int mpic_get_one_irq(struct mpic *mpic)
  1481. {
  1482. return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
  1483. }
  1484. unsigned int mpic_get_irq(void)
  1485. {
  1486. struct mpic *mpic = mpic_primary;
  1487. BUG_ON(mpic == NULL);
  1488. return mpic_get_one_irq(mpic);
  1489. }
  1490. unsigned int mpic_get_coreint_irq(void)
  1491. {
  1492. #ifdef CONFIG_BOOKE
  1493. struct mpic *mpic = mpic_primary;
  1494. u32 src;
  1495. BUG_ON(mpic == NULL);
  1496. src = mfspr(SPRN_EPR);
  1497. if (unlikely(src == mpic->spurious_vec)) {
  1498. if (mpic->flags & MPIC_SPV_EOI)
  1499. mpic_eoi(mpic);
  1500. return 0;
  1501. }
  1502. if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
  1503. printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
  1504. mpic->name, (int)src);
  1505. return 0;
  1506. }
  1507. return irq_linear_revmap(mpic->irqhost, src);
  1508. #else
  1509. return 0;
  1510. #endif
  1511. }
  1512. unsigned int mpic_get_mcirq(void)
  1513. {
  1514. struct mpic *mpic = mpic_primary;
  1515. BUG_ON(mpic == NULL);
  1516. return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
  1517. }
  1518. #ifdef CONFIG_SMP
  1519. void __init mpic_request_ipis(void)
  1520. {
  1521. struct mpic *mpic = mpic_primary;
  1522. int i;
  1523. BUG_ON(mpic == NULL);
  1524. printk(KERN_INFO "mpic: requesting IPIs...\n");
  1525. for (i = 0; i < 4; i++) {
  1526. unsigned int vipi = irq_create_mapping(mpic->irqhost,
  1527. mpic->ipi_vecs[0] + i);
  1528. if (!vipi) {
  1529. printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
  1530. continue;
  1531. }
  1532. smp_request_message_ipi(vipi, i);
  1533. }
  1534. }
  1535. void smp_mpic_message_pass(int cpu, int msg)
  1536. {
  1537. struct mpic *mpic = mpic_primary;
  1538. u32 physmask;
  1539. BUG_ON(mpic == NULL);
  1540. /* make sure we're sending something that translates to an IPI */
  1541. if ((unsigned int)msg > 3) {
  1542. printk("SMP %d: smp_message_pass: unknown msg %d\n",
  1543. smp_processor_id(), msg);
  1544. return;
  1545. }
  1546. #ifdef DEBUG_IPI
  1547. DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
  1548. #endif
  1549. physmask = 1 << get_hard_smp_processor_id(cpu);
  1550. mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
  1551. msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
  1552. }
  1553. void __init smp_mpic_probe(void)
  1554. {
  1555. int nr_cpus;
  1556. DBG("smp_mpic_probe()...\n");
  1557. nr_cpus = num_possible_cpus();
  1558. DBG("nr_cpus: %d\n", nr_cpus);
  1559. if (nr_cpus > 1)
  1560. mpic_request_ipis();
  1561. }
  1562. void smp_mpic_setup_cpu(int cpu)
  1563. {
  1564. mpic_setup_this_cpu();
  1565. }
  1566. void mpic_reset_core(int cpu)
  1567. {
  1568. struct mpic *mpic = mpic_primary;
  1569. u32 pir;
  1570. int cpuid = get_hard_smp_processor_id(cpu);
  1571. int i;
  1572. /* Set target bit for core reset */
  1573. pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
  1574. pir |= (1 << cpuid);
  1575. mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
  1576. mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
  1577. /* Restore target bit after reset complete */
  1578. pir &= ~(1 << cpuid);
  1579. mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
  1580. mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
  1581. /* Perform 15 EOI on each reset core to clear pending interrupts.
  1582. * This is required for FSL CoreNet based devices */
  1583. if (mpic->flags & MPIC_FSL) {
  1584. for (i = 0; i < 15; i++) {
  1585. _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
  1586. MPIC_CPU_EOI, 0);
  1587. }
  1588. }
  1589. }
  1590. #endif /* CONFIG_SMP */
  1591. #ifdef CONFIG_PM
  1592. static void mpic_suspend_one(struct mpic *mpic)
  1593. {
  1594. int i;
  1595. for (i = 0; i < mpic->num_sources; i++) {
  1596. mpic->save_data[i].vecprio =
  1597. mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
  1598. mpic->save_data[i].dest =
  1599. mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
  1600. }
  1601. }
  1602. static int mpic_suspend(void)
  1603. {
  1604. struct mpic *mpic = mpics;
  1605. while (mpic) {
  1606. mpic_suspend_one(mpic);
  1607. mpic = mpic->next;
  1608. }
  1609. return 0;
  1610. }
  1611. static void mpic_resume_one(struct mpic *mpic)
  1612. {
  1613. int i;
  1614. for (i = 0; i < mpic->num_sources; i++) {
  1615. mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
  1616. mpic->save_data[i].vecprio);
  1617. mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
  1618. mpic->save_data[i].dest);
  1619. #ifdef CONFIG_MPIC_U3_HT_IRQS
  1620. if (mpic->fixups) {
  1621. struct mpic_irq_fixup *fixup = &mpic->fixups[i];
  1622. if (fixup->base) {
  1623. /* we use the lowest bit in an inverted meaning */
  1624. if ((mpic->save_data[i].fixup_data & 1) == 0)
  1625. continue;
  1626. /* Enable and configure */
  1627. writeb(0x10 + 2 * fixup->index, fixup->base + 2);
  1628. writel(mpic->save_data[i].fixup_data & ~1,
  1629. fixup->base + 4);
  1630. }
  1631. }
  1632. #endif
  1633. } /* end for loop */
  1634. }
  1635. static void mpic_resume(void)
  1636. {
  1637. struct mpic *mpic = mpics;
  1638. while (mpic) {
  1639. mpic_resume_one(mpic);
  1640. mpic = mpic->next;
  1641. }
  1642. }
  1643. static struct syscore_ops mpic_syscore_ops = {
  1644. .resume = mpic_resume,
  1645. .suspend = mpic_suspend,
  1646. };
  1647. static int mpic_init_sys(void)
  1648. {
  1649. int rc;
  1650. register_syscore_ops(&mpic_syscore_ops);
  1651. rc = subsys_system_register(&mpic_subsys, NULL);
  1652. if (rc) {
  1653. unregister_syscore_ops(&mpic_syscore_ops);
  1654. pr_err("mpic: Failed to register subsystem!\n");
  1655. return rc;
  1656. }
  1657. return 0;
  1658. }
  1659. device_initcall(mpic_init_sys);
  1660. #endif