ipic.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * IPIC private definitions and structure.
  4. *
  5. * Maintainer: Kumar Gala <[email protected]>
  6. *
  7. * Copyright 2005 Freescale Semiconductor, Inc
  8. */
  9. #ifndef __IPIC_H__
  10. #define __IPIC_H__
  11. #include <asm/ipic.h>
  12. #define NR_IPIC_INTS 128
  13. /* External IRQS */
  14. #define IPIC_IRQ_EXT0 48
  15. #define IPIC_IRQ_EXT1 17
  16. #define IPIC_IRQ_EXT7 23
  17. /* Default Priority Registers */
  18. #define IPIC_PRIORITY_DEFAULT 0x05309770
  19. /* System Global Interrupt Configuration Register */
  20. #define SICFR_IPSA 0x00010000
  21. #define SICFR_IPSB 0x00020000
  22. #define SICFR_IPSC 0x00040000
  23. #define SICFR_IPSD 0x00080000
  24. #define SICFR_MPSA 0x00200000
  25. #define SICFR_MPSB 0x00400000
  26. /* System External Interrupt Mask Register */
  27. #define SEMSR_SIRQ0 0x00008000
  28. /* System Error Control Register */
  29. #define SERCR_MCPR 0x00000001
  30. struct ipic {
  31. volatile u32 __iomem *regs;
  32. /* The remapper for this IPIC */
  33. struct irq_domain *irqhost;
  34. };
  35. struct ipic_info {
  36. u8 ack; /* pending register offset from base if the irq
  37. supports ack operation */
  38. u8 mask; /* mask register offset from base */
  39. u8 prio; /* priority register offset from base */
  40. u8 force; /* force register offset from base */
  41. u8 bit; /* register bit position (as per doc)
  42. bit mask = 1 << (31 - bit) */
  43. u8 prio_mask; /* priority mask value */
  44. };
  45. #endif /* __IPIC_H__ */