ipic.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * arch/powerpc/sysdev/ipic.c
  4. *
  5. * IPIC routines implementations.
  6. *
  7. * Copyright 2005 Freescale Semiconductor, Inc.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/init.h>
  11. #include <linux/errno.h>
  12. #include <linux/reboot.h>
  13. #include <linux/slab.h>
  14. #include <linux/stddef.h>
  15. #include <linux/sched.h>
  16. #include <linux/signal.h>
  17. #include <linux/syscore_ops.h>
  18. #include <linux/device.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/irqdomain.h>
  22. #include <linux/of_address.h>
  23. #include <asm/irq.h>
  24. #include <asm/io.h>
  25. #include <asm/ipic.h>
  26. #include "ipic.h"
  27. static struct ipic * primary_ipic;
  28. static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
  29. static DEFINE_RAW_SPINLOCK(ipic_lock);
  30. static struct ipic_info ipic_info[] = {
  31. [1] = {
  32. .mask = IPIC_SIMSR_H,
  33. .prio = IPIC_SIPRR_C,
  34. .force = IPIC_SIFCR_H,
  35. .bit = 16,
  36. .prio_mask = 0,
  37. },
  38. [2] = {
  39. .mask = IPIC_SIMSR_H,
  40. .prio = IPIC_SIPRR_C,
  41. .force = IPIC_SIFCR_H,
  42. .bit = 17,
  43. .prio_mask = 1,
  44. },
  45. [3] = {
  46. .mask = IPIC_SIMSR_H,
  47. .prio = IPIC_SIPRR_C,
  48. .force = IPIC_SIFCR_H,
  49. .bit = 18,
  50. .prio_mask = 2,
  51. },
  52. [4] = {
  53. .mask = IPIC_SIMSR_H,
  54. .prio = IPIC_SIPRR_C,
  55. .force = IPIC_SIFCR_H,
  56. .bit = 19,
  57. .prio_mask = 3,
  58. },
  59. [5] = {
  60. .mask = IPIC_SIMSR_H,
  61. .prio = IPIC_SIPRR_C,
  62. .force = IPIC_SIFCR_H,
  63. .bit = 20,
  64. .prio_mask = 4,
  65. },
  66. [6] = {
  67. .mask = IPIC_SIMSR_H,
  68. .prio = IPIC_SIPRR_C,
  69. .force = IPIC_SIFCR_H,
  70. .bit = 21,
  71. .prio_mask = 5,
  72. },
  73. [7] = {
  74. .mask = IPIC_SIMSR_H,
  75. .prio = IPIC_SIPRR_C,
  76. .force = IPIC_SIFCR_H,
  77. .bit = 22,
  78. .prio_mask = 6,
  79. },
  80. [8] = {
  81. .mask = IPIC_SIMSR_H,
  82. .prio = IPIC_SIPRR_C,
  83. .force = IPIC_SIFCR_H,
  84. .bit = 23,
  85. .prio_mask = 7,
  86. },
  87. [9] = {
  88. .mask = IPIC_SIMSR_H,
  89. .prio = IPIC_SIPRR_D,
  90. .force = IPIC_SIFCR_H,
  91. .bit = 24,
  92. .prio_mask = 0,
  93. },
  94. [10] = {
  95. .mask = IPIC_SIMSR_H,
  96. .prio = IPIC_SIPRR_D,
  97. .force = IPIC_SIFCR_H,
  98. .bit = 25,
  99. .prio_mask = 1,
  100. },
  101. [11] = {
  102. .mask = IPIC_SIMSR_H,
  103. .prio = IPIC_SIPRR_D,
  104. .force = IPIC_SIFCR_H,
  105. .bit = 26,
  106. .prio_mask = 2,
  107. },
  108. [12] = {
  109. .mask = IPIC_SIMSR_H,
  110. .prio = IPIC_SIPRR_D,
  111. .force = IPIC_SIFCR_H,
  112. .bit = 27,
  113. .prio_mask = 3,
  114. },
  115. [13] = {
  116. .mask = IPIC_SIMSR_H,
  117. .prio = IPIC_SIPRR_D,
  118. .force = IPIC_SIFCR_H,
  119. .bit = 28,
  120. .prio_mask = 4,
  121. },
  122. [14] = {
  123. .mask = IPIC_SIMSR_H,
  124. .prio = IPIC_SIPRR_D,
  125. .force = IPIC_SIFCR_H,
  126. .bit = 29,
  127. .prio_mask = 5,
  128. },
  129. [15] = {
  130. .mask = IPIC_SIMSR_H,
  131. .prio = IPIC_SIPRR_D,
  132. .force = IPIC_SIFCR_H,
  133. .bit = 30,
  134. .prio_mask = 6,
  135. },
  136. [16] = {
  137. .mask = IPIC_SIMSR_H,
  138. .prio = IPIC_SIPRR_D,
  139. .force = IPIC_SIFCR_H,
  140. .bit = 31,
  141. .prio_mask = 7,
  142. },
  143. [17] = {
  144. .ack = IPIC_SEPNR,
  145. .mask = IPIC_SEMSR,
  146. .prio = IPIC_SMPRR_A,
  147. .force = IPIC_SEFCR,
  148. .bit = 1,
  149. .prio_mask = 5,
  150. },
  151. [18] = {
  152. .ack = IPIC_SEPNR,
  153. .mask = IPIC_SEMSR,
  154. .prio = IPIC_SMPRR_A,
  155. .force = IPIC_SEFCR,
  156. .bit = 2,
  157. .prio_mask = 6,
  158. },
  159. [19] = {
  160. .ack = IPIC_SEPNR,
  161. .mask = IPIC_SEMSR,
  162. .prio = IPIC_SMPRR_A,
  163. .force = IPIC_SEFCR,
  164. .bit = 3,
  165. .prio_mask = 7,
  166. },
  167. [20] = {
  168. .ack = IPIC_SEPNR,
  169. .mask = IPIC_SEMSR,
  170. .prio = IPIC_SMPRR_B,
  171. .force = IPIC_SEFCR,
  172. .bit = 4,
  173. .prio_mask = 4,
  174. },
  175. [21] = {
  176. .ack = IPIC_SEPNR,
  177. .mask = IPIC_SEMSR,
  178. .prio = IPIC_SMPRR_B,
  179. .force = IPIC_SEFCR,
  180. .bit = 5,
  181. .prio_mask = 5,
  182. },
  183. [22] = {
  184. .ack = IPIC_SEPNR,
  185. .mask = IPIC_SEMSR,
  186. .prio = IPIC_SMPRR_B,
  187. .force = IPIC_SEFCR,
  188. .bit = 6,
  189. .prio_mask = 6,
  190. },
  191. [23] = {
  192. .ack = IPIC_SEPNR,
  193. .mask = IPIC_SEMSR,
  194. .prio = IPIC_SMPRR_B,
  195. .force = IPIC_SEFCR,
  196. .bit = 7,
  197. .prio_mask = 7,
  198. },
  199. [32] = {
  200. .mask = IPIC_SIMSR_H,
  201. .prio = IPIC_SIPRR_A,
  202. .force = IPIC_SIFCR_H,
  203. .bit = 0,
  204. .prio_mask = 0,
  205. },
  206. [33] = {
  207. .mask = IPIC_SIMSR_H,
  208. .prio = IPIC_SIPRR_A,
  209. .force = IPIC_SIFCR_H,
  210. .bit = 1,
  211. .prio_mask = 1,
  212. },
  213. [34] = {
  214. .mask = IPIC_SIMSR_H,
  215. .prio = IPIC_SIPRR_A,
  216. .force = IPIC_SIFCR_H,
  217. .bit = 2,
  218. .prio_mask = 2,
  219. },
  220. [35] = {
  221. .mask = IPIC_SIMSR_H,
  222. .prio = IPIC_SIPRR_A,
  223. .force = IPIC_SIFCR_H,
  224. .bit = 3,
  225. .prio_mask = 3,
  226. },
  227. [36] = {
  228. .mask = IPIC_SIMSR_H,
  229. .prio = IPIC_SIPRR_A,
  230. .force = IPIC_SIFCR_H,
  231. .bit = 4,
  232. .prio_mask = 4,
  233. },
  234. [37] = {
  235. .mask = IPIC_SIMSR_H,
  236. .prio = IPIC_SIPRR_A,
  237. .force = IPIC_SIFCR_H,
  238. .bit = 5,
  239. .prio_mask = 5,
  240. },
  241. [38] = {
  242. .mask = IPIC_SIMSR_H,
  243. .prio = IPIC_SIPRR_A,
  244. .force = IPIC_SIFCR_H,
  245. .bit = 6,
  246. .prio_mask = 6,
  247. },
  248. [39] = {
  249. .mask = IPIC_SIMSR_H,
  250. .prio = IPIC_SIPRR_A,
  251. .force = IPIC_SIFCR_H,
  252. .bit = 7,
  253. .prio_mask = 7,
  254. },
  255. [40] = {
  256. .mask = IPIC_SIMSR_H,
  257. .prio = IPIC_SIPRR_B,
  258. .force = IPIC_SIFCR_H,
  259. .bit = 8,
  260. .prio_mask = 0,
  261. },
  262. [41] = {
  263. .mask = IPIC_SIMSR_H,
  264. .prio = IPIC_SIPRR_B,
  265. .force = IPIC_SIFCR_H,
  266. .bit = 9,
  267. .prio_mask = 1,
  268. },
  269. [42] = {
  270. .mask = IPIC_SIMSR_H,
  271. .prio = IPIC_SIPRR_B,
  272. .force = IPIC_SIFCR_H,
  273. .bit = 10,
  274. .prio_mask = 2,
  275. },
  276. [43] = {
  277. .mask = IPIC_SIMSR_H,
  278. .prio = IPIC_SIPRR_B,
  279. .force = IPIC_SIFCR_H,
  280. .bit = 11,
  281. .prio_mask = 3,
  282. },
  283. [44] = {
  284. .mask = IPIC_SIMSR_H,
  285. .prio = IPIC_SIPRR_B,
  286. .force = IPIC_SIFCR_H,
  287. .bit = 12,
  288. .prio_mask = 4,
  289. },
  290. [45] = {
  291. .mask = IPIC_SIMSR_H,
  292. .prio = IPIC_SIPRR_B,
  293. .force = IPIC_SIFCR_H,
  294. .bit = 13,
  295. .prio_mask = 5,
  296. },
  297. [46] = {
  298. .mask = IPIC_SIMSR_H,
  299. .prio = IPIC_SIPRR_B,
  300. .force = IPIC_SIFCR_H,
  301. .bit = 14,
  302. .prio_mask = 6,
  303. },
  304. [47] = {
  305. .mask = IPIC_SIMSR_H,
  306. .prio = IPIC_SIPRR_B,
  307. .force = IPIC_SIFCR_H,
  308. .bit = 15,
  309. .prio_mask = 7,
  310. },
  311. [48] = {
  312. .ack = IPIC_SEPNR,
  313. .mask = IPIC_SEMSR,
  314. .prio = IPIC_SMPRR_A,
  315. .force = IPIC_SEFCR,
  316. .bit = 0,
  317. .prio_mask = 4,
  318. },
  319. [64] = {
  320. .mask = IPIC_SIMSR_L,
  321. .prio = IPIC_SMPRR_A,
  322. .force = IPIC_SIFCR_L,
  323. .bit = 0,
  324. .prio_mask = 0,
  325. },
  326. [65] = {
  327. .mask = IPIC_SIMSR_L,
  328. .prio = IPIC_SMPRR_A,
  329. .force = IPIC_SIFCR_L,
  330. .bit = 1,
  331. .prio_mask = 1,
  332. },
  333. [66] = {
  334. .mask = IPIC_SIMSR_L,
  335. .prio = IPIC_SMPRR_A,
  336. .force = IPIC_SIFCR_L,
  337. .bit = 2,
  338. .prio_mask = 2,
  339. },
  340. [67] = {
  341. .mask = IPIC_SIMSR_L,
  342. .prio = IPIC_SMPRR_A,
  343. .force = IPIC_SIFCR_L,
  344. .bit = 3,
  345. .prio_mask = 3,
  346. },
  347. [68] = {
  348. .mask = IPIC_SIMSR_L,
  349. .prio = IPIC_SMPRR_B,
  350. .force = IPIC_SIFCR_L,
  351. .bit = 4,
  352. .prio_mask = 0,
  353. },
  354. [69] = {
  355. .mask = IPIC_SIMSR_L,
  356. .prio = IPIC_SMPRR_B,
  357. .force = IPIC_SIFCR_L,
  358. .bit = 5,
  359. .prio_mask = 1,
  360. },
  361. [70] = {
  362. .mask = IPIC_SIMSR_L,
  363. .prio = IPIC_SMPRR_B,
  364. .force = IPIC_SIFCR_L,
  365. .bit = 6,
  366. .prio_mask = 2,
  367. },
  368. [71] = {
  369. .mask = IPIC_SIMSR_L,
  370. .prio = IPIC_SMPRR_B,
  371. .force = IPIC_SIFCR_L,
  372. .bit = 7,
  373. .prio_mask = 3,
  374. },
  375. [72] = {
  376. .mask = IPIC_SIMSR_L,
  377. .prio = 0,
  378. .force = IPIC_SIFCR_L,
  379. .bit = 8,
  380. },
  381. [73] = {
  382. .mask = IPIC_SIMSR_L,
  383. .prio = 0,
  384. .force = IPIC_SIFCR_L,
  385. .bit = 9,
  386. },
  387. [74] = {
  388. .mask = IPIC_SIMSR_L,
  389. .prio = 0,
  390. .force = IPIC_SIFCR_L,
  391. .bit = 10,
  392. },
  393. [75] = {
  394. .mask = IPIC_SIMSR_L,
  395. .prio = 0,
  396. .force = IPIC_SIFCR_L,
  397. .bit = 11,
  398. },
  399. [76] = {
  400. .mask = IPIC_SIMSR_L,
  401. .prio = 0,
  402. .force = IPIC_SIFCR_L,
  403. .bit = 12,
  404. },
  405. [77] = {
  406. .mask = IPIC_SIMSR_L,
  407. .prio = 0,
  408. .force = IPIC_SIFCR_L,
  409. .bit = 13,
  410. },
  411. [78] = {
  412. .mask = IPIC_SIMSR_L,
  413. .prio = 0,
  414. .force = IPIC_SIFCR_L,
  415. .bit = 14,
  416. },
  417. [79] = {
  418. .mask = IPIC_SIMSR_L,
  419. .prio = 0,
  420. .force = IPIC_SIFCR_L,
  421. .bit = 15,
  422. },
  423. [80] = {
  424. .mask = IPIC_SIMSR_L,
  425. .prio = 0,
  426. .force = IPIC_SIFCR_L,
  427. .bit = 16,
  428. },
  429. [81] = {
  430. .mask = IPIC_SIMSR_L,
  431. .prio = 0,
  432. .force = IPIC_SIFCR_L,
  433. .bit = 17,
  434. },
  435. [82] = {
  436. .mask = IPIC_SIMSR_L,
  437. .prio = 0,
  438. .force = IPIC_SIFCR_L,
  439. .bit = 18,
  440. },
  441. [83] = {
  442. .mask = IPIC_SIMSR_L,
  443. .prio = 0,
  444. .force = IPIC_SIFCR_L,
  445. .bit = 19,
  446. },
  447. [84] = {
  448. .mask = IPIC_SIMSR_L,
  449. .prio = 0,
  450. .force = IPIC_SIFCR_L,
  451. .bit = 20,
  452. },
  453. [85] = {
  454. .mask = IPIC_SIMSR_L,
  455. .prio = 0,
  456. .force = IPIC_SIFCR_L,
  457. .bit = 21,
  458. },
  459. [86] = {
  460. .mask = IPIC_SIMSR_L,
  461. .prio = 0,
  462. .force = IPIC_SIFCR_L,
  463. .bit = 22,
  464. },
  465. [87] = {
  466. .mask = IPIC_SIMSR_L,
  467. .prio = 0,
  468. .force = IPIC_SIFCR_L,
  469. .bit = 23,
  470. },
  471. [88] = {
  472. .mask = IPIC_SIMSR_L,
  473. .prio = 0,
  474. .force = IPIC_SIFCR_L,
  475. .bit = 24,
  476. },
  477. [89] = {
  478. .mask = IPIC_SIMSR_L,
  479. .prio = 0,
  480. .force = IPIC_SIFCR_L,
  481. .bit = 25,
  482. },
  483. [90] = {
  484. .mask = IPIC_SIMSR_L,
  485. .prio = 0,
  486. .force = IPIC_SIFCR_L,
  487. .bit = 26,
  488. },
  489. [91] = {
  490. .mask = IPIC_SIMSR_L,
  491. .prio = 0,
  492. .force = IPIC_SIFCR_L,
  493. .bit = 27,
  494. },
  495. [94] = {
  496. .mask = IPIC_SIMSR_L,
  497. .prio = 0,
  498. .force = IPIC_SIFCR_L,
  499. .bit = 30,
  500. },
  501. };
  502. static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
  503. {
  504. return in_be32(base + (reg >> 2));
  505. }
  506. static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
  507. {
  508. out_be32(base + (reg >> 2), value);
  509. }
  510. static inline struct ipic * ipic_from_irq(unsigned int virq)
  511. {
  512. return primary_ipic;
  513. }
  514. static void ipic_unmask_irq(struct irq_data *d)
  515. {
  516. struct ipic *ipic = ipic_from_irq(d->irq);
  517. unsigned int src = irqd_to_hwirq(d);
  518. unsigned long flags;
  519. u32 temp;
  520. raw_spin_lock_irqsave(&ipic_lock, flags);
  521. temp = ipic_read(ipic->regs, ipic_info[src].mask);
  522. temp |= (1 << (31 - ipic_info[src].bit));
  523. ipic_write(ipic->regs, ipic_info[src].mask, temp);
  524. raw_spin_unlock_irqrestore(&ipic_lock, flags);
  525. }
  526. static void ipic_mask_irq(struct irq_data *d)
  527. {
  528. struct ipic *ipic = ipic_from_irq(d->irq);
  529. unsigned int src = irqd_to_hwirq(d);
  530. unsigned long flags;
  531. u32 temp;
  532. raw_spin_lock_irqsave(&ipic_lock, flags);
  533. temp = ipic_read(ipic->regs, ipic_info[src].mask);
  534. temp &= ~(1 << (31 - ipic_info[src].bit));
  535. ipic_write(ipic->regs, ipic_info[src].mask, temp);
  536. /* mb() can't guarantee that masking is finished. But it does finish
  537. * for nearly all cases. */
  538. mb();
  539. raw_spin_unlock_irqrestore(&ipic_lock, flags);
  540. }
  541. static void ipic_ack_irq(struct irq_data *d)
  542. {
  543. struct ipic *ipic = ipic_from_irq(d->irq);
  544. unsigned int src = irqd_to_hwirq(d);
  545. unsigned long flags;
  546. u32 temp;
  547. raw_spin_lock_irqsave(&ipic_lock, flags);
  548. temp = 1 << (31 - ipic_info[src].bit);
  549. ipic_write(ipic->regs, ipic_info[src].ack, temp);
  550. /* mb() can't guarantee that ack is finished. But it does finish
  551. * for nearly all cases. */
  552. mb();
  553. raw_spin_unlock_irqrestore(&ipic_lock, flags);
  554. }
  555. static void ipic_mask_irq_and_ack(struct irq_data *d)
  556. {
  557. struct ipic *ipic = ipic_from_irq(d->irq);
  558. unsigned int src = irqd_to_hwirq(d);
  559. unsigned long flags;
  560. u32 temp;
  561. raw_spin_lock_irqsave(&ipic_lock, flags);
  562. temp = ipic_read(ipic->regs, ipic_info[src].mask);
  563. temp &= ~(1 << (31 - ipic_info[src].bit));
  564. ipic_write(ipic->regs, ipic_info[src].mask, temp);
  565. temp = 1 << (31 - ipic_info[src].bit);
  566. ipic_write(ipic->regs, ipic_info[src].ack, temp);
  567. /* mb() can't guarantee that ack is finished. But it does finish
  568. * for nearly all cases. */
  569. mb();
  570. raw_spin_unlock_irqrestore(&ipic_lock, flags);
  571. }
  572. static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
  573. {
  574. struct ipic *ipic = ipic_from_irq(d->irq);
  575. unsigned int src = irqd_to_hwirq(d);
  576. unsigned int vold, vnew, edibit;
  577. if (flow_type == IRQ_TYPE_NONE)
  578. flow_type = IRQ_TYPE_LEVEL_LOW;
  579. /* ipic supports only low assertion and high-to-low change senses
  580. */
  581. if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
  582. printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
  583. flow_type);
  584. return -EINVAL;
  585. }
  586. /* ipic supports only edge mode on external interrupts */
  587. if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
  588. printk(KERN_ERR "ipic: edge sense not supported on internal "
  589. "interrupts\n");
  590. return -EINVAL;
  591. }
  592. irqd_set_trigger_type(d, flow_type);
  593. if (flow_type & IRQ_TYPE_LEVEL_LOW) {
  594. irq_set_handler_locked(d, handle_level_irq);
  595. d->chip = &ipic_level_irq_chip;
  596. } else {
  597. irq_set_handler_locked(d, handle_edge_irq);
  598. d->chip = &ipic_edge_irq_chip;
  599. }
  600. /* only EXT IRQ senses are programmable on ipic
  601. * internal IRQ senses are LEVEL_LOW
  602. */
  603. if (src == IPIC_IRQ_EXT0)
  604. edibit = 15;
  605. else
  606. if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
  607. edibit = (14 - (src - IPIC_IRQ_EXT1));
  608. else
  609. return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
  610. vold = ipic_read(ipic->regs, IPIC_SECNR);
  611. if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
  612. vnew = vold | (1 << edibit);
  613. } else {
  614. vnew = vold & ~(1 << edibit);
  615. }
  616. if (vold != vnew)
  617. ipic_write(ipic->regs, IPIC_SECNR, vnew);
  618. return IRQ_SET_MASK_OK_NOCOPY;
  619. }
  620. /* level interrupts and edge interrupts have different ack operations */
  621. static struct irq_chip ipic_level_irq_chip = {
  622. .name = "IPIC",
  623. .irq_unmask = ipic_unmask_irq,
  624. .irq_mask = ipic_mask_irq,
  625. .irq_mask_ack = ipic_mask_irq,
  626. .irq_set_type = ipic_set_irq_type,
  627. };
  628. static struct irq_chip ipic_edge_irq_chip = {
  629. .name = "IPIC",
  630. .irq_unmask = ipic_unmask_irq,
  631. .irq_mask = ipic_mask_irq,
  632. .irq_mask_ack = ipic_mask_irq_and_ack,
  633. .irq_ack = ipic_ack_irq,
  634. .irq_set_type = ipic_set_irq_type,
  635. };
  636. static int ipic_host_match(struct irq_domain *h, struct device_node *node,
  637. enum irq_domain_bus_token bus_token)
  638. {
  639. /* Exact match, unless ipic node is NULL */
  640. struct device_node *of_node = irq_domain_get_of_node(h);
  641. return of_node == NULL || of_node == node;
  642. }
  643. static int ipic_host_map(struct irq_domain *h, unsigned int virq,
  644. irq_hw_number_t hw)
  645. {
  646. struct ipic *ipic = h->host_data;
  647. irq_set_chip_data(virq, ipic);
  648. irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
  649. /* Set default irq type */
  650. irq_set_irq_type(virq, IRQ_TYPE_NONE);
  651. return 0;
  652. }
  653. static const struct irq_domain_ops ipic_host_ops = {
  654. .match = ipic_host_match,
  655. .map = ipic_host_map,
  656. .xlate = irq_domain_xlate_onetwocell,
  657. };
  658. struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
  659. {
  660. struct ipic *ipic;
  661. struct resource res;
  662. u32 temp = 0, ret;
  663. ret = of_address_to_resource(node, 0, &res);
  664. if (ret)
  665. return NULL;
  666. ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
  667. if (ipic == NULL)
  668. return NULL;
  669. ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
  670. &ipic_host_ops, ipic);
  671. if (ipic->irqhost == NULL) {
  672. kfree(ipic);
  673. return NULL;
  674. }
  675. ipic->regs = ioremap(res.start, resource_size(&res));
  676. /* init hw */
  677. ipic_write(ipic->regs, IPIC_SICNR, 0x0);
  678. /* default priority scheme is grouped. If spread mode is required
  679. * configure SICFR accordingly */
  680. if (flags & IPIC_SPREADMODE_GRP_A)
  681. temp |= SICFR_IPSA;
  682. if (flags & IPIC_SPREADMODE_GRP_B)
  683. temp |= SICFR_IPSB;
  684. if (flags & IPIC_SPREADMODE_GRP_C)
  685. temp |= SICFR_IPSC;
  686. if (flags & IPIC_SPREADMODE_GRP_D)
  687. temp |= SICFR_IPSD;
  688. if (flags & IPIC_SPREADMODE_MIX_A)
  689. temp |= SICFR_MPSA;
  690. if (flags & IPIC_SPREADMODE_MIX_B)
  691. temp |= SICFR_MPSB;
  692. ipic_write(ipic->regs, IPIC_SICFR, temp);
  693. /* handle MCP route */
  694. temp = 0;
  695. if (flags & IPIC_DISABLE_MCP_OUT)
  696. temp = SERCR_MCPR;
  697. ipic_write(ipic->regs, IPIC_SERCR, temp);
  698. /* handle routing of IRQ0 to MCP */
  699. temp = ipic_read(ipic->regs, IPIC_SEMSR);
  700. if (flags & IPIC_IRQ0_MCP)
  701. temp |= SEMSR_SIRQ0;
  702. else
  703. temp &= ~SEMSR_SIRQ0;
  704. ipic_write(ipic->regs, IPIC_SEMSR, temp);
  705. primary_ipic = ipic;
  706. irq_set_default_host(primary_ipic->irqhost);
  707. ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
  708. ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
  709. printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
  710. primary_ipic->regs);
  711. return ipic;
  712. }
  713. void __init ipic_set_default_priority(void)
  714. {
  715. ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
  716. ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
  717. ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
  718. ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
  719. ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
  720. ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
  721. }
  722. u32 ipic_get_mcp_status(void)
  723. {
  724. return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0;
  725. }
  726. void ipic_clear_mcp_status(u32 mask)
  727. {
  728. ipic_write(primary_ipic->regs, IPIC_SERSR, mask);
  729. }
  730. /* Return an interrupt vector or 0 if no interrupt is pending. */
  731. unsigned int ipic_get_irq(void)
  732. {
  733. int irq;
  734. BUG_ON(primary_ipic == NULL);
  735. #define IPIC_SIVCR_VECTOR_MASK 0x7f
  736. irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
  737. if (irq == 0) /* 0 --> no irq is pending */
  738. return 0;
  739. return irq_linear_revmap(primary_ipic->irqhost, irq);
  740. }
  741. #ifdef CONFIG_SUSPEND
  742. static struct {
  743. u32 sicfr;
  744. u32 siprr[2];
  745. u32 simsr[2];
  746. u32 sicnr;
  747. u32 smprr[2];
  748. u32 semsr;
  749. u32 secnr;
  750. u32 sermr;
  751. u32 sercr;
  752. } ipic_saved_state;
  753. static int ipic_suspend(void)
  754. {
  755. struct ipic *ipic = primary_ipic;
  756. ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
  757. ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
  758. ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
  759. ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
  760. ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
  761. ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
  762. ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
  763. ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
  764. ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
  765. ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
  766. ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
  767. ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
  768. if (fsl_deep_sleep()) {
  769. /* In deep sleep, make sure there can be no
  770. * pending interrupts, as this can cause
  771. * problems on 831x.
  772. */
  773. ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
  774. ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
  775. ipic_write(ipic->regs, IPIC_SEMSR, 0);
  776. ipic_write(ipic->regs, IPIC_SERMR, 0);
  777. }
  778. return 0;
  779. }
  780. static void ipic_resume(void)
  781. {
  782. struct ipic *ipic = primary_ipic;
  783. ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
  784. ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
  785. ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
  786. ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
  787. ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
  788. ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
  789. ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
  790. ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
  791. ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
  792. ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
  793. ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
  794. ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
  795. }
  796. #else
  797. #define ipic_suspend NULL
  798. #define ipic_resume NULL
  799. #endif
  800. static struct syscore_ops ipic_syscore_ops = {
  801. .suspend = ipic_suspend,
  802. .resume = ipic_resume,
  803. };
  804. static int __init init_ipic_syscore(void)
  805. {
  806. if (!primary_ipic || !primary_ipic->regs)
  807. return -ENODEV;
  808. printk(KERN_DEBUG "Registering ipic system core operations\n");
  809. register_syscore_ops(&ipic_syscore_ops);
  810. return 0;
  811. }
  812. subsys_initcall(init_ipic_syscore);