tm.S 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Transactional memory support routines to reclaim and recheckpoint
  4. * transactional process state.
  5. *
  6. * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
  7. */
  8. #include <asm/asm-offsets.h>
  9. #include <asm/ppc_asm.h>
  10. #include <asm/ppc-opcode.h>
  11. #include <asm/ptrace.h>
  12. #include <asm/reg.h>
  13. #include <asm/bug.h>
  14. #include <asm/export.h>
  15. #include <asm/feature-fixups.h>
  16. #ifdef CONFIG_VSX
  17. /* See fpu.S, this is borrowed from there */
  18. #define __SAVE_32FPRS_VSRS(n,c,base) \
  19. BEGIN_FTR_SECTION \
  20. b 2f; \
  21. END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
  22. SAVE_32FPRS(n,base); \
  23. b 3f; \
  24. 2: SAVE_32VSRS(n,c,base); \
  25. 3:
  26. #define __REST_32FPRS_VSRS(n,c,base) \
  27. BEGIN_FTR_SECTION \
  28. b 2f; \
  29. END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
  30. REST_32FPRS(n,base); \
  31. b 3f; \
  32. 2: REST_32VSRS(n,c,base); \
  33. 3:
  34. #else
  35. #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
  36. #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
  37. #endif
  38. #define SAVE_32FPRS_VSRS(n,c,base) \
  39. __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
  40. #define REST_32FPRS_VSRS(n,c,base) \
  41. __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
  42. /* Stack frame offsets for local variables. */
  43. #define TM_FRAME_L0 TM_FRAME_SIZE-16
  44. #define TM_FRAME_L1 TM_FRAME_SIZE-8
  45. /* In order to access the TM SPRs, TM must be enabled. So, do so: */
  46. _GLOBAL(tm_enable)
  47. mfmsr r4
  48. li r3, MSR_TM >> 32
  49. sldi r3, r3, 32
  50. and. r0, r4, r3
  51. bne 1f
  52. or r4, r4, r3
  53. mtmsrd r4
  54. 1: blr
  55. EXPORT_SYMBOL_GPL(tm_enable);
  56. _GLOBAL(tm_disable)
  57. mfmsr r4
  58. li r3, MSR_TM >> 32
  59. sldi r3, r3, 32
  60. andc r4, r4, r3
  61. mtmsrd r4
  62. blr
  63. EXPORT_SYMBOL_GPL(tm_disable);
  64. _GLOBAL(tm_save_sprs)
  65. mfspr r0, SPRN_TFHAR
  66. std r0, THREAD_TM_TFHAR(r3)
  67. mfspr r0, SPRN_TEXASR
  68. std r0, THREAD_TM_TEXASR(r3)
  69. mfspr r0, SPRN_TFIAR
  70. std r0, THREAD_TM_TFIAR(r3)
  71. blr
  72. _GLOBAL(tm_restore_sprs)
  73. ld r0, THREAD_TM_TFHAR(r3)
  74. mtspr SPRN_TFHAR, r0
  75. ld r0, THREAD_TM_TEXASR(r3)
  76. mtspr SPRN_TEXASR, r0
  77. ld r0, THREAD_TM_TFIAR(r3)
  78. mtspr SPRN_TFIAR, r0
  79. blr
  80. /* Passed an 8-bit failure cause as first argument. */
  81. _GLOBAL(tm_abort)
  82. TABORT(R3)
  83. blr
  84. EXPORT_SYMBOL_GPL(tm_abort);
  85. /*
  86. * void tm_reclaim(struct thread_struct *thread,
  87. * uint8_t cause)
  88. *
  89. * - Performs a full reclaim. This destroys outstanding
  90. * transactions and updates thread.ckpt_regs, thread.ckfp_state and
  91. * thread.ckvr_state with the original checkpointed state. Note that
  92. * thread->regs is unchanged.
  93. *
  94. * Purpose is to both abort transactions of, and preserve the state of,
  95. * a transactions at a context switch. We preserve/restore both sets of process
  96. * state to restore them when the thread's scheduled again. We continue in
  97. * userland as though nothing happened, but when the transaction is resumed
  98. * they will abort back to the checkpointed state we save out here.
  99. *
  100. * Call with IRQs off, stacks get all out of sync for some periods in here!
  101. */
  102. _GLOBAL(tm_reclaim)
  103. mfcr r5
  104. mflr r0
  105. stw r5, 8(r1)
  106. std r0, 16(r1)
  107. std r2, STK_GOT(r1)
  108. stdu r1, -TM_FRAME_SIZE(r1)
  109. /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
  110. std r3, STK_PARAM(R3)(r1)
  111. SAVE_NVGPRS(r1)
  112. /*
  113. * Save kernel live AMR since it will be clobbered by treclaim
  114. * but can be used elsewhere later in kernel space.
  115. */
  116. mfspr r3, SPRN_AMR
  117. std r3, TM_FRAME_L1(r1)
  118. /* We need to setup MSR for VSX register save instructions. */
  119. mfmsr r14
  120. mr r15, r14
  121. ori r15, r15, MSR_FP
  122. li r16, 0
  123. ori r16, r16, MSR_EE /* IRQs hard off */
  124. andc r15, r15, r16
  125. oris r15, r15, MSR_VEC@h
  126. #ifdef CONFIG_VSX
  127. BEGIN_FTR_SECTION
  128. oris r15,r15, MSR_VSX@h
  129. END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  130. #endif
  131. mtmsrd r15
  132. std r14, TM_FRAME_L0(r1)
  133. /* Do sanity check on MSR to make sure we are suspended */
  134. li r7, (MSR_TS_S)@higher
  135. srdi r6, r14, 32
  136. and r6, r6, r7
  137. 1: tdeqi r6, 0
  138. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
  139. /* Stash the stack pointer away for use after reclaim */
  140. std r1, PACAR1(r13)
  141. /* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
  142. li r5, 0
  143. mtmsrd r5, 1
  144. /*
  145. * BE CAREFUL HERE:
  146. * At this point we can't take an SLB miss since we have MSR_RI
  147. * off. Load only to/from the stack/paca which are in SLB bolted regions
  148. * until we turn MSR RI back on.
  149. *
  150. * The moment we treclaim, ALL of our GPRs will switch
  151. * to user register state. (FPRs, CCR etc. also!)
  152. * Use an sprg and a tm_scratch in the PACA to shuffle.
  153. */
  154. TRECLAIM(R4) /* Cause in r4 */
  155. /*
  156. * ******************** GPRs ********************
  157. * Stash the checkpointed r13 in the scratch SPR and get the real paca.
  158. */
  159. SET_SCRATCH0(r13)
  160. GET_PACA(r13)
  161. /*
  162. * Stash the checkpointed r1 away in paca->tm_scratch and get the real
  163. * stack pointer back into r1.
  164. */
  165. std r1, PACATMSCRATCH(r13)
  166. ld r1, PACAR1(r13)
  167. std r11, GPR11(r1) /* Temporary stash */
  168. /*
  169. * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is
  170. * clobbered by an exception once we turn on MSR_RI below.
  171. */
  172. ld r11, PACATMSCRATCH(r13)
  173. std r11, GPR1(r1)
  174. /*
  175. * Store r13 away so we can free up the scratch SPR for the SLB fault
  176. * handler (needed once we start accessing the thread_struct).
  177. */
  178. GET_SCRATCH0(r11)
  179. std r11, GPR13(r1)
  180. /* Reset MSR RI so we can take SLB faults again */
  181. li r11, MSR_RI
  182. mtmsrd r11, 1
  183. /* Store the PPR in r11 and reset to decent value */
  184. mfspr r11, SPRN_PPR
  185. HMT_MEDIUM
  186. /* Now get some more GPRS free */
  187. std r7, GPR7(r1) /* Temporary stash */
  188. std r12, GPR12(r1) /* '' '' '' */
  189. ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
  190. std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
  191. addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
  192. /*
  193. * Make r7 look like an exception frame so that we can use the neat
  194. * GPRx(n) macros. r7 is NOT a pt_regs ptr!
  195. */
  196. subi r7, r7, STACK_FRAME_OVERHEAD
  197. /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
  198. SAVE_GPR(0, r7) /* user r0 */
  199. SAVE_GPRS(2, 6, r7) /* user r2-r6 */
  200. SAVE_GPRS(8, 10, r7) /* user r8-r10 */
  201. ld r3, GPR1(r1) /* user r1 */
  202. ld r4, GPR7(r1) /* user r7 */
  203. ld r5, GPR11(r1) /* user r11 */
  204. ld r6, GPR12(r1) /* user r12 */
  205. ld r8, GPR13(r1) /* user r13 */
  206. std r3, GPR1(r7)
  207. std r4, GPR7(r7)
  208. std r5, GPR11(r7)
  209. std r6, GPR12(r7)
  210. std r8, GPR13(r7)
  211. SAVE_NVGPRS(r7) /* user r14-r31 */
  212. /* ******************** NIP ******************** */
  213. mfspr r3, SPRN_TFHAR
  214. std r3, _NIP(r7) /* Returns to failhandler */
  215. /*
  216. * The checkpointed NIP is ignored when rescheduling/rechkpting,
  217. * but is used in signal return to 'wind back' to the abort handler.
  218. */
  219. /* ***************** CTR, LR, CR, XER ********** */
  220. mfctr r3
  221. mflr r4
  222. mfcr r5
  223. mfxer r6
  224. std r3, _CTR(r7)
  225. std r4, _LINK(r7)
  226. std r5, _CCR(r7)
  227. std r6, _XER(r7)
  228. /* ******************** TAR, DSCR ********** */
  229. mfspr r3, SPRN_TAR
  230. mfspr r4, SPRN_DSCR
  231. std r3, THREAD_TM_TAR(r12)
  232. std r4, THREAD_TM_DSCR(r12)
  233. /* ******************** AMR **************** */
  234. mfspr r3, SPRN_AMR
  235. std r3, THREAD_TM_AMR(r12)
  236. /*
  237. * MSR and flags: We don't change CRs, and we don't need to alter MSR.
  238. */
  239. /*
  240. * ******************** FPR/VR/VSRs ************
  241. * After reclaiming, capture the checkpointed FPRs/VRs.
  242. *
  243. * We enabled VEC/FP/VSX in the msr above, so we can execute these
  244. * instructions!
  245. */
  246. mr r3, r12
  247. /* Altivec (VEC/VMX/VR)*/
  248. addi r7, r3, THREAD_CKVRSTATE
  249. SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 ckvr_state */
  250. mfvscr v0
  251. li r6, VRSTATE_VSCR
  252. stvx v0, r7, r6
  253. /* VRSAVE */
  254. mfspr r0, SPRN_VRSAVE
  255. std r0, THREAD_CKVRSAVE(r3)
  256. /* Floating Point (FP) */
  257. addi r7, r3, THREAD_CKFPSTATE
  258. SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 ckfp_state */
  259. mffs fr0
  260. stfd fr0,FPSTATE_FPSCR(r7)
  261. /*
  262. * TM regs, incl TEXASR -- these live in thread_struct. Note they've
  263. * been updated by the treclaim, to explain to userland the failure
  264. * cause (aborted).
  265. */
  266. mfspr r0, SPRN_TEXASR
  267. mfspr r3, SPRN_TFHAR
  268. mfspr r4, SPRN_TFIAR
  269. std r0, THREAD_TM_TEXASR(r12)
  270. std r3, THREAD_TM_TFHAR(r12)
  271. std r4, THREAD_TM_TFIAR(r12)
  272. /* Restore kernel live AMR */
  273. ld r8, TM_FRAME_L1(r1)
  274. mtspr SPRN_AMR, r8
  275. /* Restore original MSR/IRQ state & clear TM mode */
  276. ld r14, TM_FRAME_L0(r1) /* Orig MSR */
  277. li r15, 0
  278. rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
  279. mtmsrd r14
  280. REST_NVGPRS(r1)
  281. addi r1, r1, TM_FRAME_SIZE
  282. lwz r4, 8(r1)
  283. ld r0, 16(r1)
  284. mtcr r4
  285. mtlr r0
  286. ld r2, STK_GOT(r1)
  287. /* Load CPU's default DSCR */
  288. ld r0, PACA_DSCR_DEFAULT(r13)
  289. mtspr SPRN_DSCR, r0
  290. blr
  291. /*
  292. * void __tm_recheckpoint(struct thread_struct *thread)
  293. * - Restore the checkpointed register state saved by tm_reclaim
  294. * when we switch_to a process.
  295. *
  296. * Call with IRQs off, stacks get all out of sync for
  297. * some periods in here!
  298. */
  299. _GLOBAL(__tm_recheckpoint)
  300. mfcr r5
  301. mflr r0
  302. stw r5, 8(r1)
  303. std r0, 16(r1)
  304. std r2, STK_GOT(r1)
  305. stdu r1, -TM_FRAME_SIZE(r1)
  306. /*
  307. * We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
  308. * This is used for backing up the NVGPRs:
  309. */
  310. SAVE_NVGPRS(r1)
  311. /*
  312. * Save kernel live AMR since it will be clobbered for trechkpt
  313. * but can be used elsewhere later in kernel space.
  314. */
  315. mfspr r8, SPRN_AMR
  316. std r8, TM_FRAME_L0(r1)
  317. /* Load complete register state from ts_ckpt* registers */
  318. addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
  319. /*
  320. * Make r7 look like an exception frame so that we can use the neat
  321. * GPRx(n) macros. r7 is now NOT a pt_regs ptr!
  322. */
  323. subi r7, r7, STACK_FRAME_OVERHEAD
  324. /* We need to setup MSR for FP/VMX/VSX register save instructions. */
  325. mfmsr r6
  326. mr r5, r6
  327. ori r5, r5, MSR_FP
  328. #ifdef CONFIG_ALTIVEC
  329. oris r5, r5, MSR_VEC@h
  330. #endif
  331. #ifdef CONFIG_VSX
  332. BEGIN_FTR_SECTION
  333. oris r5,r5, MSR_VSX@h
  334. END_FTR_SECTION_IFSET(CPU_FTR_VSX)
  335. #endif
  336. mtmsrd r5
  337. #ifdef CONFIG_ALTIVEC
  338. /*
  339. * FP and VEC registers: These are recheckpointed from
  340. * thread.ckfp_state and thread.ckvr_state respectively. The
  341. * thread.fp_state[] version holds the 'live' (transactional)
  342. * and will be loaded subsequently by any FPUnavailable trap.
  343. */
  344. addi r8, r3, THREAD_CKVRSTATE
  345. li r5, VRSTATE_VSCR
  346. lvx v0, r8, r5
  347. mtvscr v0
  348. REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
  349. ld r5, THREAD_CKVRSAVE(r3)
  350. mtspr SPRN_VRSAVE, r5
  351. #endif
  352. addi r8, r3, THREAD_CKFPSTATE
  353. lfd fr0, FPSTATE_FPSCR(r8)
  354. MTFSF_L(fr0)
  355. REST_32FPRS_VSRS(0, R4, R8)
  356. mtmsr r6 /* FP/Vec off again! */
  357. restore_gprs:
  358. /* ****************** CTR, LR, XER ************* */
  359. ld r4, _CTR(r7)
  360. ld r5, _LINK(r7)
  361. ld r8, _XER(r7)
  362. mtctr r4
  363. mtlr r5
  364. mtxer r8
  365. /* ******************** TAR ******************** */
  366. ld r4, THREAD_TM_TAR(r3)
  367. mtspr SPRN_TAR, r4
  368. /* ******************** AMR ******************** */
  369. ld r4, THREAD_TM_AMR(r3)
  370. mtspr SPRN_AMR, r4
  371. /* Load up the PPR and DSCR in GPRs only at this stage */
  372. ld r5, THREAD_TM_DSCR(r3)
  373. ld r6, THREAD_TM_PPR(r3)
  374. REST_GPR(0, r7) /* GPR0 */
  375. REST_GPRS(2, 4, r7) /* GPR2-4 */
  376. REST_GPRS(8, 12, r7) /* GPR8-12 */
  377. REST_GPRS(14, 31, r7) /* GPR14-31 */
  378. /* Load up PPR and DSCR here so we don't run with user values for long */
  379. mtspr SPRN_DSCR, r5
  380. mtspr SPRN_PPR, r6
  381. /*
  382. * Do final sanity check on TEXASR to make sure FS is set. Do this
  383. * here before we load up the userspace r1 so any bugs we hit will get
  384. * a call chain.
  385. */
  386. mfspr r5, SPRN_TEXASR
  387. srdi r5, r5, 16
  388. li r6, (TEXASR_FS)@h
  389. and r6, r6, r5
  390. 1: tdeqi r6, 0
  391. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
  392. /*
  393. * Do final sanity check on MSR to make sure we are not transactional
  394. * or suspended.
  395. */
  396. mfmsr r6
  397. li r5, (MSR_TS_MASK)@higher
  398. srdi r6, r6, 32
  399. and r6, r6, r5
  400. 1: tdnei r6, 0
  401. EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
  402. /* Restore CR */
  403. ld r6, _CCR(r7)
  404. mtcr r6
  405. REST_GPR(6, r7)
  406. /*
  407. * Store user r1 and r5 and r13 on the stack (in the unused save
  408. * areas / compiler reserved areas), so that we can access them after
  409. * we clear MSR RI.
  410. */
  411. REST_GPR(5, r7)
  412. std r5, -8(r1)
  413. ld r5, GPR13(r7)
  414. std r5, -16(r1)
  415. ld r5, GPR1(r7)
  416. std r5, -24(r1)
  417. REST_GPR(7, r7)
  418. /* Stash the stack pointer away for use after recheckpoint */
  419. std r1, PACAR1(r13)
  420. /* Clear MSR RI since we are about to clobber r13. EE is already off */
  421. li r5, 0
  422. mtmsrd r5, 1
  423. /*
  424. * BE CAREFUL HERE:
  425. * At this point we can't take an SLB miss since we have MSR_RI
  426. * off. Load only to/from the stack/paca which are in SLB bolted regions
  427. * until we turn MSR RI back on.
  428. */
  429. ld r5, -8(r1)
  430. ld r13, -16(r1)
  431. ld r1, -24(r1)
  432. /* Commit register state as checkpointed state: */
  433. TRECHKPT
  434. HMT_MEDIUM
  435. /*
  436. * Our transactional state has now changed.
  437. *
  438. * Now just get out of here. Transactional (current) state will be
  439. * updated once restore is called on the return path in the _switch-ed
  440. * -to process.
  441. */
  442. GET_PACA(r13)
  443. ld r1, PACAR1(r13)
  444. /* R13, R1 is restored, so we are recoverable again. EE is still off */
  445. li r4, MSR_RI
  446. mtmsrd r4, 1
  447. /* Restore kernel live AMR */
  448. ld r8, TM_FRAME_L0(r1)
  449. mtspr SPRN_AMR, r8
  450. REST_NVGPRS(r1)
  451. addi r1, r1, TM_FRAME_SIZE
  452. lwz r4, 8(r1)
  453. ld r0, 16(r1)
  454. mtcr r4
  455. mtlr r0
  456. ld r2, STK_GOT(r1)
  457. /* Load CPU's default DSCR */
  458. ld r0, PACA_DSCR_DEFAULT(r13)
  459. mtspr SPRN_DSCR, r0
  460. blr
  461. /* ****************************************************************** */