optprobes.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Code for Kernel probes Jump optimization.
  4. *
  5. * Copyright 2017, Anju T, IBM Corp.
  6. */
  7. #include <linux/kprobes.h>
  8. #include <linux/jump_label.h>
  9. #include <linux/types.h>
  10. #include <linux/slab.h>
  11. #include <linux/list.h>
  12. #include <asm/kprobes.h>
  13. #include <asm/ptrace.h>
  14. #include <asm/cacheflush.h>
  15. #include <asm/code-patching.h>
  16. #include <asm/sstep.h>
  17. #include <asm/ppc-opcode.h>
  18. #include <asm/inst.h>
  19. #define TMPL_CALL_HDLR_IDX (optprobe_template_call_handler - optprobe_template_entry)
  20. #define TMPL_EMULATE_IDX (optprobe_template_call_emulate - optprobe_template_entry)
  21. #define TMPL_RET_IDX (optprobe_template_ret - optprobe_template_entry)
  22. #define TMPL_OP_IDX (optprobe_template_op_address - optprobe_template_entry)
  23. #define TMPL_INSN_IDX (optprobe_template_insn - optprobe_template_entry)
  24. #define TMPL_END_IDX (optprobe_template_end - optprobe_template_entry)
  25. static bool insn_page_in_use;
  26. void *alloc_optinsn_page(void)
  27. {
  28. if (insn_page_in_use)
  29. return NULL;
  30. insn_page_in_use = true;
  31. return &optinsn_slot;
  32. }
  33. void free_optinsn_page(void *page)
  34. {
  35. insn_page_in_use = false;
  36. }
  37. /*
  38. * Check if we can optimize this probe. Returns NIP post-emulation if this can
  39. * be optimized and 0 otherwise.
  40. */
  41. static unsigned long can_optimize(struct kprobe *p)
  42. {
  43. struct pt_regs regs;
  44. struct instruction_op op;
  45. unsigned long nip = 0;
  46. unsigned long addr = (unsigned long)p->addr;
  47. /*
  48. * kprobe placed for kretprobe during boot time
  49. * has a 'nop' instruction, which can be emulated.
  50. * So further checks can be skipped.
  51. */
  52. if (p->addr == (kprobe_opcode_t *)&__kretprobe_trampoline)
  53. return addr + sizeof(kprobe_opcode_t);
  54. /*
  55. * We only support optimizing kernel addresses, but not
  56. * module addresses.
  57. *
  58. * FIXME: Optimize kprobes placed in module addresses.
  59. */
  60. if (!is_kernel_addr(addr))
  61. return 0;
  62. memset(&regs, 0, sizeof(struct pt_regs));
  63. regs.nip = addr;
  64. regs.trap = 0x0;
  65. regs.msr = MSR_KERNEL;
  66. /*
  67. * Kprobe placed in conditional branch instructions are
  68. * not optimized, as we can't predict the nip prior with
  69. * dummy pt_regs and can not ensure that the return branch
  70. * from detour buffer falls in the range of address (i.e 32MB).
  71. * A branch back from trampoline is set up in the detour buffer
  72. * to the nip returned by the analyse_instr() here.
  73. *
  74. * Ensure that the instruction is not a conditional branch,
  75. * and that can be emulated.
  76. */
  77. if (!is_conditional_branch(ppc_inst_read(p->ainsn.insn)) &&
  78. analyse_instr(&op, &regs, ppc_inst_read(p->ainsn.insn)) == 1) {
  79. emulate_update_regs(&regs, &op);
  80. nip = regs.nip;
  81. }
  82. return nip;
  83. }
  84. static void optimized_callback(struct optimized_kprobe *op,
  85. struct pt_regs *regs)
  86. {
  87. /* This is possible if op is under delayed unoptimizing */
  88. if (kprobe_disabled(&op->kp))
  89. return;
  90. preempt_disable();
  91. if (kprobe_running()) {
  92. kprobes_inc_nmissed_count(&op->kp);
  93. } else {
  94. __this_cpu_write(current_kprobe, &op->kp);
  95. regs_set_return_ip(regs, (unsigned long)op->kp.addr);
  96. get_kprobe_ctlblk()->kprobe_status = KPROBE_HIT_ACTIVE;
  97. opt_pre_handler(&op->kp, regs);
  98. __this_cpu_write(current_kprobe, NULL);
  99. }
  100. preempt_enable_no_resched();
  101. }
  102. NOKPROBE_SYMBOL(optimized_callback);
  103. void arch_remove_optimized_kprobe(struct optimized_kprobe *op)
  104. {
  105. if (op->optinsn.insn) {
  106. free_optinsn_slot(op->optinsn.insn, 1);
  107. op->optinsn.insn = NULL;
  108. }
  109. }
  110. static void patch_imm32_load_insns(unsigned long val, int reg, kprobe_opcode_t *addr)
  111. {
  112. patch_instruction(addr++, ppc_inst(PPC_RAW_LIS(reg, PPC_HI(val))));
  113. patch_instruction(addr, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_LO(val))));
  114. }
  115. /*
  116. * Generate instructions to load provided immediate 64-bit value
  117. * to register 'reg' and patch these instructions at 'addr'.
  118. */
  119. static void patch_imm64_load_insns(unsigned long long val, int reg, kprobe_opcode_t *addr)
  120. {
  121. patch_instruction(addr++, ppc_inst(PPC_RAW_LIS(reg, PPC_HIGHEST(val))));
  122. patch_instruction(addr++, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_HIGHER(val))));
  123. patch_instruction(addr++, ppc_inst(PPC_RAW_SLDI(reg, reg, 32)));
  124. patch_instruction(addr++, ppc_inst(PPC_RAW_ORIS(reg, reg, PPC_HI(val))));
  125. patch_instruction(addr, ppc_inst(PPC_RAW_ORI(reg, reg, PPC_LO(val))));
  126. }
  127. static void patch_imm_load_insns(unsigned long val, int reg, kprobe_opcode_t *addr)
  128. {
  129. if (IS_ENABLED(CONFIG_PPC64))
  130. patch_imm64_load_insns(val, reg, addr);
  131. else
  132. patch_imm32_load_insns(val, reg, addr);
  133. }
  134. int arch_prepare_optimized_kprobe(struct optimized_kprobe *op, struct kprobe *p)
  135. {
  136. ppc_inst_t branch_op_callback, branch_emulate_step, temp;
  137. unsigned long op_callback_addr, emulate_step_addr;
  138. kprobe_opcode_t *buff;
  139. long b_offset;
  140. unsigned long nip, size;
  141. int rc, i;
  142. nip = can_optimize(p);
  143. if (!nip)
  144. return -EILSEQ;
  145. /* Allocate instruction slot for detour buffer */
  146. buff = get_optinsn_slot();
  147. if (!buff)
  148. return -ENOMEM;
  149. /*
  150. * OPTPROBE uses 'b' instruction to branch to optinsn.insn.
  151. *
  152. * The target address has to be relatively nearby, to permit use
  153. * of branch instruction in powerpc, because the address is specified
  154. * in an immediate field in the instruction opcode itself, ie 24 bits
  155. * in the opcode specify the address. Therefore the address should
  156. * be within 32MB on either side of the current instruction.
  157. */
  158. b_offset = (unsigned long)buff - (unsigned long)p->addr;
  159. if (!is_offset_in_branch_range(b_offset))
  160. goto error;
  161. /* Check if the return address is also within 32MB range */
  162. b_offset = (unsigned long)(buff + TMPL_RET_IDX) - nip;
  163. if (!is_offset_in_branch_range(b_offset))
  164. goto error;
  165. /* Setup template */
  166. /* We can optimize this via patch_instruction_window later */
  167. size = (TMPL_END_IDX * sizeof(kprobe_opcode_t)) / sizeof(int);
  168. pr_devel("Copying template to %p, size %lu\n", buff, size);
  169. for (i = 0; i < size; i++) {
  170. rc = patch_instruction(buff + i, ppc_inst(*(optprobe_template_entry + i)));
  171. if (rc < 0)
  172. goto error;
  173. }
  174. /*
  175. * Fixup the template with instructions to:
  176. * 1. load the address of the actual probepoint
  177. */
  178. patch_imm_load_insns((unsigned long)op, 3, buff + TMPL_OP_IDX);
  179. /*
  180. * 2. branch to optimized_callback() and emulate_step()
  181. */
  182. op_callback_addr = ppc_kallsyms_lookup_name("optimized_callback");
  183. emulate_step_addr = ppc_kallsyms_lookup_name("emulate_step");
  184. if (!op_callback_addr || !emulate_step_addr) {
  185. WARN(1, "Unable to lookup optimized_callback()/emulate_step()\n");
  186. goto error;
  187. }
  188. rc = create_branch(&branch_op_callback, buff + TMPL_CALL_HDLR_IDX,
  189. op_callback_addr, BRANCH_SET_LINK);
  190. rc |= create_branch(&branch_emulate_step, buff + TMPL_EMULATE_IDX,
  191. emulate_step_addr, BRANCH_SET_LINK);
  192. if (rc)
  193. goto error;
  194. patch_instruction(buff + TMPL_CALL_HDLR_IDX, branch_op_callback);
  195. patch_instruction(buff + TMPL_EMULATE_IDX, branch_emulate_step);
  196. /*
  197. * 3. load instruction to be emulated into relevant register, and
  198. */
  199. temp = ppc_inst_read(p->ainsn.insn);
  200. patch_imm_load_insns(ppc_inst_as_ulong(temp), 4, buff + TMPL_INSN_IDX);
  201. /*
  202. * 4. branch back from trampoline
  203. */
  204. patch_branch(buff + TMPL_RET_IDX, nip, 0);
  205. flush_icache_range((unsigned long)buff, (unsigned long)(&buff[TMPL_END_IDX]));
  206. op->optinsn.insn = buff;
  207. return 0;
  208. error:
  209. free_optinsn_slot(buff, 0);
  210. return -ERANGE;
  211. }
  212. int arch_prepared_optinsn(struct arch_optimized_insn *optinsn)
  213. {
  214. return optinsn->insn != NULL;
  215. }
  216. /*
  217. * On powerpc, Optprobes always replaces one instruction (4 bytes
  218. * aligned and 4 bytes long). It is impossible to encounter another
  219. * kprobe in this address range. So always return 0.
  220. */
  221. int arch_check_optimized_kprobe(struct optimized_kprobe *op)
  222. {
  223. return 0;
  224. }
  225. void arch_optimize_kprobes(struct list_head *oplist)
  226. {
  227. ppc_inst_t instr;
  228. struct optimized_kprobe *op;
  229. struct optimized_kprobe *tmp;
  230. list_for_each_entry_safe(op, tmp, oplist, list) {
  231. /*
  232. * Backup instructions which will be replaced
  233. * by jump address
  234. */
  235. memcpy(op->optinsn.copied_insn, op->kp.addr, RELATIVEJUMP_SIZE);
  236. create_branch(&instr, op->kp.addr, (unsigned long)op->optinsn.insn, 0);
  237. patch_instruction(op->kp.addr, instr);
  238. list_del_init(&op->list);
  239. }
  240. }
  241. void arch_unoptimize_kprobe(struct optimized_kprobe *op)
  242. {
  243. arch_arm_kprobe(&op->kp);
  244. }
  245. void arch_unoptimize_kprobes(struct list_head *oplist, struct list_head *done_list)
  246. {
  247. struct optimized_kprobe *op;
  248. struct optimized_kprobe *tmp;
  249. list_for_each_entry_safe(op, tmp, oplist, list) {
  250. arch_unoptimize_kprobe(op);
  251. list_move(&op->list, done_list);
  252. }
  253. }
  254. int arch_within_optimized_kprobe(struct optimized_kprobe *op, kprobe_opcode_t *addr)
  255. {
  256. return (op->kp.addr <= addr &&
  257. op->kp.addr + (RELATIVEJUMP_SIZE / sizeof(kprobe_opcode_t)) > addr);
  258. }