irq.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Derived from arch/i386/kernel/irq.c
  4. * Copyright (C) 1992 Linus Torvalds
  5. * Adapted from arch/i386 by Gary Thomas
  6. * Copyright (C) 1995-1996 Gary Thomas ([email protected])
  7. * Updated and modified by Cort Dougan <[email protected]>
  8. * Copyright (C) 1996-2001 Cort Dougan
  9. * Adapted for Power Macintosh by Paul Mackerras
  10. * Copyright (C) 1996 Paul Mackerras ([email protected])
  11. *
  12. * This file contains the code used by various IRQ handling routines:
  13. * asking for different IRQ's should be done through these routines
  14. * instead of just grabbing them. Thus setups with different IRQ numbers
  15. * shouldn't result in any weird surprises, and installing new handlers
  16. * should be easier.
  17. *
  18. * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
  19. * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
  20. * mask register (of which only 16 are defined), hence the weird shifting
  21. * and complement of the cached_irq_mask. I want to be able to stuff
  22. * this right into the SIU SMASK register.
  23. * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
  24. * to reduce code space and undefined function references.
  25. */
  26. #undef DEBUG
  27. #include <linux/export.h>
  28. #include <linux/threads.h>
  29. #include <linux/kernel_stat.h>
  30. #include <linux/signal.h>
  31. #include <linux/sched.h>
  32. #include <linux/ptrace.h>
  33. #include <linux/ioport.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/timex.h>
  36. #include <linux/init.h>
  37. #include <linux/slab.h>
  38. #include <linux/delay.h>
  39. #include <linux/irq.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/cpumask.h>
  42. #include <linux/profile.h>
  43. #include <linux/bitops.h>
  44. #include <linux/list.h>
  45. #include <linux/radix-tree.h>
  46. #include <linux/mutex.h>
  47. #include <linux/pci.h>
  48. #include <linux/debugfs.h>
  49. #include <linux/of.h>
  50. #include <linux/of_irq.h>
  51. #include <linux/vmalloc.h>
  52. #include <linux/pgtable.h>
  53. #include <linux/static_call.h>
  54. #include <linux/uaccess.h>
  55. #include <asm/interrupt.h>
  56. #include <asm/io.h>
  57. #include <asm/irq.h>
  58. #include <asm/cache.h>
  59. #include <asm/ptrace.h>
  60. #include <asm/machdep.h>
  61. #include <asm/udbg.h>
  62. #include <asm/smp.h>
  63. #include <asm/hw_irq.h>
  64. #include <asm/softirq_stack.h>
  65. #include <asm/ppc_asm.h>
  66. #define CREATE_TRACE_POINTS
  67. #include <asm/trace.h>
  68. #include <asm/cpu_has_feature.h>
  69. DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
  70. EXPORT_PER_CPU_SYMBOL(irq_stat);
  71. #ifdef CONFIG_PPC32
  72. atomic_t ppc_n_lost_interrupts;
  73. #ifdef CONFIG_TAU_INT
  74. extern int tau_initialized;
  75. u32 tau_interrupts(unsigned long cpu);
  76. #endif
  77. #endif /* CONFIG_PPC32 */
  78. int arch_show_interrupts(struct seq_file *p, int prec)
  79. {
  80. int j;
  81. #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
  82. if (tau_initialized) {
  83. seq_printf(p, "%*s: ", prec, "TAU");
  84. for_each_online_cpu(j)
  85. seq_printf(p, "%10u ", tau_interrupts(j));
  86. seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
  87. }
  88. #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
  89. seq_printf(p, "%*s: ", prec, "LOC");
  90. for_each_online_cpu(j)
  91. seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
  92. seq_printf(p, " Local timer interrupts for timer event device\n");
  93. seq_printf(p, "%*s: ", prec, "BCT");
  94. for_each_online_cpu(j)
  95. seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event);
  96. seq_printf(p, " Broadcast timer interrupts for timer event device\n");
  97. seq_printf(p, "%*s: ", prec, "LOC");
  98. for_each_online_cpu(j)
  99. seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
  100. seq_printf(p, " Local timer interrupts for others\n");
  101. seq_printf(p, "%*s: ", prec, "SPU");
  102. for_each_online_cpu(j)
  103. seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
  104. seq_printf(p, " Spurious interrupts\n");
  105. seq_printf(p, "%*s: ", prec, "PMI");
  106. for_each_online_cpu(j)
  107. seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
  108. seq_printf(p, " Performance monitoring interrupts\n");
  109. seq_printf(p, "%*s: ", prec, "MCE");
  110. for_each_online_cpu(j)
  111. seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
  112. seq_printf(p, " Machine check exceptions\n");
  113. #ifdef CONFIG_PPC_BOOK3S_64
  114. if (cpu_has_feature(CPU_FTR_HVMODE)) {
  115. seq_printf(p, "%*s: ", prec, "HMI");
  116. for_each_online_cpu(j)
  117. seq_printf(p, "%10u ", paca_ptrs[j]->hmi_irqs);
  118. seq_printf(p, " Hypervisor Maintenance Interrupts\n");
  119. }
  120. #endif
  121. seq_printf(p, "%*s: ", prec, "NMI");
  122. for_each_online_cpu(j)
  123. seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs);
  124. seq_printf(p, " System Reset interrupts\n");
  125. #ifdef CONFIG_PPC_WATCHDOG
  126. seq_printf(p, "%*s: ", prec, "WDG");
  127. for_each_online_cpu(j)
  128. seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs);
  129. seq_printf(p, " Watchdog soft-NMI interrupts\n");
  130. #endif
  131. #ifdef CONFIG_PPC_DOORBELL
  132. if (cpu_has_feature(CPU_FTR_DBELL)) {
  133. seq_printf(p, "%*s: ", prec, "DBL");
  134. for_each_online_cpu(j)
  135. seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
  136. seq_printf(p, " Doorbell interrupts\n");
  137. }
  138. #endif
  139. return 0;
  140. }
  141. /*
  142. * /proc/stat helpers
  143. */
  144. u64 arch_irq_stat_cpu(unsigned int cpu)
  145. {
  146. u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
  147. sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
  148. sum += per_cpu(irq_stat, cpu).pmu_irqs;
  149. sum += per_cpu(irq_stat, cpu).mce_exceptions;
  150. sum += per_cpu(irq_stat, cpu).spurious_irqs;
  151. sum += per_cpu(irq_stat, cpu).timer_irqs_others;
  152. #ifdef CONFIG_PPC_BOOK3S_64
  153. sum += paca_ptrs[cpu]->hmi_irqs;
  154. #endif
  155. sum += per_cpu(irq_stat, cpu).sreset_irqs;
  156. #ifdef CONFIG_PPC_WATCHDOG
  157. sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
  158. #endif
  159. #ifdef CONFIG_PPC_DOORBELL
  160. sum += per_cpu(irq_stat, cpu).doorbell_irqs;
  161. #endif
  162. return sum;
  163. }
  164. static inline void check_stack_overflow(unsigned long sp)
  165. {
  166. if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
  167. return;
  168. sp &= THREAD_SIZE - 1;
  169. /* check for stack overflow: is there less than 1/4th free? */
  170. if (unlikely(sp < THREAD_SIZE / 4)) {
  171. pr_err("do_IRQ: stack overflow: %ld\n", sp);
  172. dump_stack();
  173. }
  174. }
  175. #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
  176. static __always_inline void call_do_softirq(const void *sp)
  177. {
  178. /* Temporarily switch r1 to sp, call __do_softirq() then restore r1. */
  179. asm volatile (
  180. PPC_STLU " %%r1, %[offset](%[sp]) ;"
  181. "mr %%r1, %[sp] ;"
  182. "bl %[callee] ;"
  183. PPC_LL " %%r1, 0(%%r1) ;"
  184. : // Outputs
  185. : // Inputs
  186. [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_OVERHEAD),
  187. [callee] "i" (__do_softirq)
  188. : // Clobbers
  189. "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6",
  190. "cr7", "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
  191. "r11", "r12"
  192. );
  193. }
  194. #endif
  195. DEFINE_STATIC_CALL_RET0(ppc_get_irq, *ppc_md.get_irq);
  196. static void __do_irq(struct pt_regs *regs, unsigned long oldsp)
  197. {
  198. unsigned int irq;
  199. trace_irq_entry(regs);
  200. check_stack_overflow(oldsp);
  201. /*
  202. * Query the platform PIC for the interrupt & ack it.
  203. *
  204. * This will typically lower the interrupt line to the CPU
  205. */
  206. irq = static_call(ppc_get_irq)();
  207. /* We can hard enable interrupts now to allow perf interrupts */
  208. if (should_hard_irq_enable(regs))
  209. do_hard_irq_enable();
  210. /* And finally process it */
  211. if (unlikely(!irq))
  212. __this_cpu_inc(irq_stat.spurious_irqs);
  213. else
  214. generic_handle_irq(irq);
  215. trace_irq_exit(regs);
  216. }
  217. static __always_inline void call_do_irq(struct pt_regs *regs, void *sp)
  218. {
  219. register unsigned long r3 asm("r3") = (unsigned long)regs;
  220. /* Temporarily switch r1 to sp, call __do_irq() then restore r1. */
  221. asm volatile (
  222. PPC_STLU " %%r1, %[offset](%[sp]) ;"
  223. "mr %%r4, %%r1 ;"
  224. "mr %%r1, %[sp] ;"
  225. "bl %[callee] ;"
  226. PPC_LL " %%r1, 0(%%r1) ;"
  227. : // Outputs
  228. "+r" (r3)
  229. : // Inputs
  230. [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_OVERHEAD),
  231. [callee] "i" (__do_irq)
  232. : // Clobbers
  233. "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6",
  234. "cr7", "r0", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
  235. "r11", "r12"
  236. );
  237. }
  238. void __do_IRQ(struct pt_regs *regs)
  239. {
  240. struct pt_regs *old_regs = set_irq_regs(regs);
  241. void *cursp, *irqsp, *sirqsp;
  242. /* Switch to the irq stack to handle this */
  243. cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
  244. irqsp = hardirq_ctx[raw_smp_processor_id()];
  245. sirqsp = softirq_ctx[raw_smp_processor_id()];
  246. /* Already there ? If not switch stack and call */
  247. if (unlikely(cursp == irqsp || cursp == sirqsp))
  248. __do_irq(regs, current_stack_pointer);
  249. else
  250. call_do_irq(regs, irqsp);
  251. set_irq_regs(old_regs);
  252. }
  253. DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ)
  254. {
  255. __do_IRQ(regs);
  256. }
  257. static void *__init alloc_vm_stack(void)
  258. {
  259. return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
  260. NUMA_NO_NODE, (void *)_RET_IP_);
  261. }
  262. static void __init vmap_irqstack_init(void)
  263. {
  264. int i;
  265. for_each_possible_cpu(i) {
  266. softirq_ctx[i] = alloc_vm_stack();
  267. hardirq_ctx[i] = alloc_vm_stack();
  268. }
  269. }
  270. void __init init_IRQ(void)
  271. {
  272. if (IS_ENABLED(CONFIG_VMAP_STACK))
  273. vmap_irqstack_init();
  274. if (ppc_md.init_IRQ)
  275. ppc_md.init_IRQ();
  276. if (!WARN_ON(!ppc_md.get_irq))
  277. static_call_update(ppc_get_irq, ppc_md.get_irq);
  278. }
  279. #ifdef CONFIG_BOOKE_OR_40x
  280. void *critirq_ctx[NR_CPUS] __read_mostly;
  281. void *dbgirq_ctx[NR_CPUS] __read_mostly;
  282. void *mcheckirq_ctx[NR_CPUS] __read_mostly;
  283. #endif
  284. void *softirq_ctx[NR_CPUS] __read_mostly;
  285. void *hardirq_ctx[NR_CPUS] __read_mostly;
  286. #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
  287. void do_softirq_own_stack(void)
  288. {
  289. call_do_softirq(softirq_ctx[smp_processor_id()]);
  290. }
  291. #endif
  292. irq_hw_number_t virq_to_hw(unsigned int virq)
  293. {
  294. struct irq_data *irq_data = irq_get_irq_data(virq);
  295. return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
  296. }
  297. EXPORT_SYMBOL_GPL(virq_to_hw);
  298. #ifdef CONFIG_SMP
  299. int irq_choose_cpu(const struct cpumask *mask)
  300. {
  301. int cpuid;
  302. if (cpumask_equal(mask, cpu_online_mask)) {
  303. static int irq_rover;
  304. static DEFINE_RAW_SPINLOCK(irq_rover_lock);
  305. unsigned long flags;
  306. /* Round-robin distribution... */
  307. do_round_robin:
  308. raw_spin_lock_irqsave(&irq_rover_lock, flags);
  309. irq_rover = cpumask_next(irq_rover, cpu_online_mask);
  310. if (irq_rover >= nr_cpu_ids)
  311. irq_rover = cpumask_first(cpu_online_mask);
  312. cpuid = irq_rover;
  313. raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
  314. } else {
  315. cpuid = cpumask_first_and(mask, cpu_online_mask);
  316. if (cpuid >= nr_cpu_ids)
  317. goto do_round_robin;
  318. }
  319. return get_hard_smp_processor_id(cpuid);
  320. }
  321. #else
  322. int irq_choose_cpu(const struct cpumask *mask)
  323. {
  324. return hard_smp_processor_id();
  325. }
  326. #endif