eeh.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright IBM Corporation 2001, 2005, 2006
  4. * Copyright Dave Engebretsen & Todd Inglett 2001
  5. * Copyright Linas Vepstas 2005, 2006
  6. * Copyright 2001-2012 IBM Corporation.
  7. *
  8. * Please address comments and feedback to Linas Vepstas <[email protected]>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/sched.h>
  12. #include <linux/init.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/iommu.h>
  16. #include <linux/proc_fs.h>
  17. #include <linux/rbtree.h>
  18. #include <linux/reboot.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/export.h>
  22. #include <linux/of.h>
  23. #include <linux/debugfs.h>
  24. #include <linux/atomic.h>
  25. #include <asm/eeh.h>
  26. #include <asm/eeh_event.h>
  27. #include <asm/io.h>
  28. #include <asm/iommu.h>
  29. #include <asm/machdep.h>
  30. #include <asm/ppc-pci.h>
  31. #include <asm/rtas.h>
  32. #include <asm/pte-walk.h>
  33. /** Overview:
  34. * EEH, or "Enhanced Error Handling" is a PCI bridge technology for
  35. * dealing with PCI bus errors that can't be dealt with within the
  36. * usual PCI framework, except by check-stopping the CPU. Systems
  37. * that are designed for high-availability/reliability cannot afford
  38. * to crash due to a "mere" PCI error, thus the need for EEH.
  39. * An EEH-capable bridge operates by converting a detected error
  40. * into a "slot freeze", taking the PCI adapter off-line, making
  41. * the slot behave, from the OS'es point of view, as if the slot
  42. * were "empty": all reads return 0xff's and all writes are silently
  43. * ignored. EEH slot isolation events can be triggered by parity
  44. * errors on the address or data busses (e.g. during posted writes),
  45. * which in turn might be caused by low voltage on the bus, dust,
  46. * vibration, humidity, radioactivity or plain-old failed hardware.
  47. *
  48. * Note, however, that one of the leading causes of EEH slot
  49. * freeze events are buggy device drivers, buggy device microcode,
  50. * or buggy device hardware. This is because any attempt by the
  51. * device to bus-master data to a memory address that is not
  52. * assigned to the device will trigger a slot freeze. (The idea
  53. * is to prevent devices-gone-wild from corrupting system memory).
  54. * Buggy hardware/drivers will have a miserable time co-existing
  55. * with EEH.
  56. *
  57. * Ideally, a PCI device driver, when suspecting that an isolation
  58. * event has occurred (e.g. by reading 0xff's), will then ask EEH
  59. * whether this is the case, and then take appropriate steps to
  60. * reset the PCI slot, the PCI device, and then resume operations.
  61. * However, until that day, the checking is done here, with the
  62. * eeh_check_failure() routine embedded in the MMIO macros. If
  63. * the slot is found to be isolated, an "EEH Event" is synthesized
  64. * and sent out for processing.
  65. */
  66. /* If a device driver keeps reading an MMIO register in an interrupt
  67. * handler after a slot isolation event, it might be broken.
  68. * This sets the threshold for how many read attempts we allow
  69. * before printing an error message.
  70. */
  71. #define EEH_MAX_FAILS 2100000
  72. /* Time to wait for a PCI slot to report status, in milliseconds */
  73. #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
  74. /*
  75. * EEH probe mode support, which is part of the flags,
  76. * is to support multiple platforms for EEH. Some platforms
  77. * like pSeries do PCI emunation based on device tree.
  78. * However, other platforms like powernv probe PCI devices
  79. * from hardware. The flag is used to distinguish that.
  80. * In addition, struct eeh_ops::probe would be invoked for
  81. * particular OF node or PCI device so that the corresponding
  82. * PE would be created there.
  83. */
  84. int eeh_subsystem_flags;
  85. EXPORT_SYMBOL(eeh_subsystem_flags);
  86. /*
  87. * EEH allowed maximal frozen times. If one particular PE's
  88. * frozen count in last hour exceeds this limit, the PE will
  89. * be forced to be offline permanently.
  90. */
  91. u32 eeh_max_freezes = 5;
  92. /*
  93. * Controls whether a recovery event should be scheduled when an
  94. * isolated device is discovered. This is only really useful for
  95. * debugging problems with the EEH core.
  96. */
  97. bool eeh_debugfs_no_recover;
  98. /* Platform dependent EEH operations */
  99. struct eeh_ops *eeh_ops = NULL;
  100. /* Lock to avoid races due to multiple reports of an error */
  101. DEFINE_RAW_SPINLOCK(confirm_error_lock);
  102. EXPORT_SYMBOL_GPL(confirm_error_lock);
  103. /* Lock to protect passed flags */
  104. static DEFINE_MUTEX(eeh_dev_mutex);
  105. /* Buffer for reporting pci register dumps. Its here in BSS, and
  106. * not dynamically alloced, so that it ends up in RMO where RTAS
  107. * can access it.
  108. */
  109. #define EEH_PCI_REGS_LOG_LEN 8192
  110. static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
  111. /*
  112. * The struct is used to maintain the EEH global statistic
  113. * information. Besides, the EEH global statistics will be
  114. * exported to user space through procfs
  115. */
  116. struct eeh_stats {
  117. u64 no_device; /* PCI device not found */
  118. u64 no_dn; /* OF node not found */
  119. u64 no_cfg_addr; /* Config address not found */
  120. u64 ignored_check; /* EEH check skipped */
  121. u64 total_mmio_ffs; /* Total EEH checks */
  122. u64 false_positives; /* Unnecessary EEH checks */
  123. u64 slot_resets; /* PE reset */
  124. };
  125. static struct eeh_stats eeh_stats;
  126. static int __init eeh_setup(char *str)
  127. {
  128. if (!strcmp(str, "off"))
  129. eeh_add_flag(EEH_FORCE_DISABLED);
  130. else if (!strcmp(str, "early_log"))
  131. eeh_add_flag(EEH_EARLY_DUMP_LOG);
  132. return 1;
  133. }
  134. __setup("eeh=", eeh_setup);
  135. void eeh_show_enabled(void)
  136. {
  137. if (eeh_has_flag(EEH_FORCE_DISABLED))
  138. pr_info("EEH: Recovery disabled by kernel parameter.\n");
  139. else if (eeh_has_flag(EEH_ENABLED))
  140. pr_info("EEH: Capable adapter found: recovery enabled.\n");
  141. else
  142. pr_info("EEH: No capable adapters found: recovery disabled.\n");
  143. }
  144. /*
  145. * This routine captures assorted PCI configuration space data
  146. * for the indicated PCI device, and puts them into a buffer
  147. * for RTAS error logging.
  148. */
  149. static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
  150. {
  151. u32 cfg;
  152. int cap, i;
  153. int n = 0, l = 0;
  154. char buffer[128];
  155. n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
  156. edev->pe->phb->global_number, edev->bdfn >> 8,
  157. PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
  158. pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
  159. edev->pe->phb->global_number, edev->bdfn >> 8,
  160. PCI_SLOT(edev->bdfn), PCI_FUNC(edev->bdfn));
  161. eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
  162. n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
  163. pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
  164. eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
  165. n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
  166. pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
  167. /* Gather bridge-specific registers */
  168. if (edev->mode & EEH_DEV_BRIDGE) {
  169. eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
  170. n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
  171. pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
  172. eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
  173. n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
  174. pr_warn("EEH: Bridge control: %04x\n", cfg);
  175. }
  176. /* Dump out the PCI-X command and status regs */
  177. cap = edev->pcix_cap;
  178. if (cap) {
  179. eeh_ops->read_config(edev, cap, 4, &cfg);
  180. n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
  181. pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
  182. eeh_ops->read_config(edev, cap+4, 4, &cfg);
  183. n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
  184. pr_warn("EEH: PCI-X status: %08x\n", cfg);
  185. }
  186. /* If PCI-E capable, dump PCI-E cap 10 */
  187. cap = edev->pcie_cap;
  188. if (cap) {
  189. n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
  190. pr_warn("EEH: PCI-E capabilities and status follow:\n");
  191. for (i=0; i<=8; i++) {
  192. eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
  193. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  194. if ((i % 4) == 0) {
  195. if (i != 0)
  196. pr_warn("%s\n", buffer);
  197. l = scnprintf(buffer, sizeof(buffer),
  198. "EEH: PCI-E %02x: %08x ",
  199. 4*i, cfg);
  200. } else {
  201. l += scnprintf(buffer+l, sizeof(buffer)-l,
  202. "%08x ", cfg);
  203. }
  204. }
  205. pr_warn("%s\n", buffer);
  206. }
  207. /* If AER capable, dump it */
  208. cap = edev->aer_cap;
  209. if (cap) {
  210. n += scnprintf(buf+n, len-n, "pci-e AER:\n");
  211. pr_warn("EEH: PCI-E AER capability register set follows:\n");
  212. for (i=0; i<=13; i++) {
  213. eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
  214. n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
  215. if ((i % 4) == 0) {
  216. if (i != 0)
  217. pr_warn("%s\n", buffer);
  218. l = scnprintf(buffer, sizeof(buffer),
  219. "EEH: PCI-E AER %02x: %08x ",
  220. 4*i, cfg);
  221. } else {
  222. l += scnprintf(buffer+l, sizeof(buffer)-l,
  223. "%08x ", cfg);
  224. }
  225. }
  226. pr_warn("%s\n", buffer);
  227. }
  228. return n;
  229. }
  230. static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
  231. {
  232. struct eeh_dev *edev, *tmp;
  233. size_t *plen = flag;
  234. eeh_pe_for_each_dev(pe, edev, tmp)
  235. *plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
  236. EEH_PCI_REGS_LOG_LEN - *plen);
  237. return NULL;
  238. }
  239. /**
  240. * eeh_slot_error_detail - Generate combined log including driver log and error log
  241. * @pe: EEH PE
  242. * @severity: temporary or permanent error log
  243. *
  244. * This routine should be called to generate the combined log, which
  245. * is comprised of driver log and error log. The driver log is figured
  246. * out from the config space of the corresponding PCI device, while
  247. * the error log is fetched through platform dependent function call.
  248. */
  249. void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
  250. {
  251. size_t loglen = 0;
  252. /*
  253. * When the PHB is fenced or dead, it's pointless to collect
  254. * the data from PCI config space because it should return
  255. * 0xFF's. For ER, we still retrieve the data from the PCI
  256. * config space.
  257. *
  258. * For pHyp, we have to enable IO for log retrieval. Otherwise,
  259. * 0xFF's is always returned from PCI config space.
  260. *
  261. * When the @severity is EEH_LOG_PERM, the PE is going to be
  262. * removed. Prior to that, the drivers for devices included in
  263. * the PE will be closed. The drivers rely on working IO path
  264. * to bring the devices to quiet state. Otherwise, PCI traffic
  265. * from those devices after they are removed is like to cause
  266. * another unexpected EEH error.
  267. */
  268. if (!(pe->type & EEH_PE_PHB)) {
  269. if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
  270. severity == EEH_LOG_PERM)
  271. eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  272. /*
  273. * The config space of some PCI devices can't be accessed
  274. * when their PEs are in frozen state. Otherwise, fenced
  275. * PHB might be seen. Those PEs are identified with flag
  276. * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
  277. * is set automatically when the PE is put to EEH_PE_ISOLATED.
  278. *
  279. * Restoring BARs possibly triggers PCI config access in
  280. * (OPAL) firmware and then causes fenced PHB. If the
  281. * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
  282. * pointless to restore BARs and dump config space.
  283. */
  284. eeh_ops->configure_bridge(pe);
  285. if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
  286. eeh_pe_restore_bars(pe);
  287. pci_regs_buf[0] = 0;
  288. eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
  289. }
  290. }
  291. eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
  292. }
  293. /**
  294. * eeh_token_to_phys - Convert EEH address token to phys address
  295. * @token: I/O token, should be address in the form 0xA....
  296. *
  297. * This routine should be called to convert virtual I/O address
  298. * to physical one.
  299. */
  300. static inline unsigned long eeh_token_to_phys(unsigned long token)
  301. {
  302. return ppc_find_vmap_phys(token);
  303. }
  304. /*
  305. * On PowerNV platform, we might already have fenced PHB there.
  306. * For that case, it's meaningless to recover frozen PE. Intead,
  307. * We have to handle fenced PHB firstly.
  308. */
  309. static int eeh_phb_check_failure(struct eeh_pe *pe)
  310. {
  311. struct eeh_pe *phb_pe;
  312. unsigned long flags;
  313. int ret;
  314. if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
  315. return -EPERM;
  316. /* Find the PHB PE */
  317. phb_pe = eeh_phb_pe_get(pe->phb);
  318. if (!phb_pe) {
  319. pr_warn("%s Can't find PE for PHB#%x\n",
  320. __func__, pe->phb->global_number);
  321. return -EEXIST;
  322. }
  323. /* If the PHB has been in problematic state */
  324. eeh_serialize_lock(&flags);
  325. if (phb_pe->state & EEH_PE_ISOLATED) {
  326. ret = 0;
  327. goto out;
  328. }
  329. /* Check PHB state */
  330. ret = eeh_ops->get_state(phb_pe, NULL);
  331. if ((ret < 0) ||
  332. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  333. ret = 0;
  334. goto out;
  335. }
  336. /* Isolate the PHB and send event */
  337. eeh_pe_mark_isolated(phb_pe);
  338. eeh_serialize_unlock(flags);
  339. pr_debug("EEH: PHB#%x failure detected, location: %s\n",
  340. phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
  341. eeh_send_failure_event(phb_pe);
  342. return 1;
  343. out:
  344. eeh_serialize_unlock(flags);
  345. return ret;
  346. }
  347. static inline const char *eeh_driver_name(struct pci_dev *pdev)
  348. {
  349. if (pdev)
  350. return dev_driver_string(&pdev->dev);
  351. return "<null>";
  352. }
  353. /**
  354. * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  355. * @edev: eeh device
  356. *
  357. * Check for an EEH failure for the given device node. Call this
  358. * routine if the result of a read was all 0xff's and you want to
  359. * find out if this is due to an EEH slot freeze. This routine
  360. * will query firmware for the EEH status.
  361. *
  362. * Returns 0 if there has not been an EEH error; otherwise returns
  363. * a non-zero value and queues up a slot isolation event notification.
  364. *
  365. * It is safe to call this routine in an interrupt context.
  366. */
  367. int eeh_dev_check_failure(struct eeh_dev *edev)
  368. {
  369. int ret;
  370. unsigned long flags;
  371. struct device_node *dn;
  372. struct pci_dev *dev;
  373. struct eeh_pe *pe, *parent_pe;
  374. int rc = 0;
  375. const char *location = NULL;
  376. eeh_stats.total_mmio_ffs++;
  377. if (!eeh_enabled())
  378. return 0;
  379. if (!edev) {
  380. eeh_stats.no_dn++;
  381. return 0;
  382. }
  383. dev = eeh_dev_to_pci_dev(edev);
  384. pe = eeh_dev_to_pe(edev);
  385. /* Access to IO BARs might get this far and still not want checking. */
  386. if (!pe) {
  387. eeh_stats.ignored_check++;
  388. eeh_edev_dbg(edev, "Ignored check\n");
  389. return 0;
  390. }
  391. /*
  392. * On PowerNV platform, we might already have fenced PHB
  393. * there and we need take care of that firstly.
  394. */
  395. ret = eeh_phb_check_failure(pe);
  396. if (ret > 0)
  397. return ret;
  398. /*
  399. * If the PE isn't owned by us, we shouldn't check the
  400. * state. Instead, let the owner handle it if the PE has
  401. * been frozen.
  402. */
  403. if (eeh_pe_passed(pe))
  404. return 0;
  405. /* If we already have a pending isolation event for this
  406. * slot, we know it's bad already, we don't need to check.
  407. * Do this checking under a lock; as multiple PCI devices
  408. * in one slot might report errors simultaneously, and we
  409. * only want one error recovery routine running.
  410. */
  411. eeh_serialize_lock(&flags);
  412. rc = 1;
  413. if (pe->state & EEH_PE_ISOLATED) {
  414. pe->check_count++;
  415. if (pe->check_count == EEH_MAX_FAILS) {
  416. dn = pci_device_to_OF_node(dev);
  417. if (dn)
  418. location = of_get_property(dn, "ibm,loc-code",
  419. NULL);
  420. eeh_edev_err(edev, "%d reads ignored for recovering device at location=%s driver=%s\n",
  421. pe->check_count,
  422. location ? location : "unknown",
  423. eeh_driver_name(dev));
  424. eeh_edev_err(edev, "Might be infinite loop in %s driver\n",
  425. eeh_driver_name(dev));
  426. dump_stack();
  427. }
  428. goto dn_unlock;
  429. }
  430. /*
  431. * Now test for an EEH failure. This is VERY expensive.
  432. * Note that the eeh_config_addr may be a parent device
  433. * in the case of a device behind a bridge, or it may be
  434. * function zero of a multi-function device.
  435. * In any case they must share a common PHB.
  436. */
  437. ret = eeh_ops->get_state(pe, NULL);
  438. /* Note that config-io to empty slots may fail;
  439. * they are empty when they don't have children.
  440. * We will punt with the following conditions: Failure to get
  441. * PE's state, EEH not support and Permanently unavailable
  442. * state, PE is in good state.
  443. */
  444. if ((ret < 0) ||
  445. (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
  446. eeh_stats.false_positives++;
  447. pe->false_positives++;
  448. rc = 0;
  449. goto dn_unlock;
  450. }
  451. /*
  452. * It should be corner case that the parent PE has been
  453. * put into frozen state as well. We should take care
  454. * that at first.
  455. */
  456. parent_pe = pe->parent;
  457. while (parent_pe) {
  458. /* Hit the ceiling ? */
  459. if (parent_pe->type & EEH_PE_PHB)
  460. break;
  461. /* Frozen parent PE ? */
  462. ret = eeh_ops->get_state(parent_pe, NULL);
  463. if (ret > 0 && !eeh_state_active(ret)) {
  464. pe = parent_pe;
  465. pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
  466. pe->phb->global_number, pe->addr,
  467. pe->phb->global_number, parent_pe->addr);
  468. }
  469. /* Next parent level */
  470. parent_pe = parent_pe->parent;
  471. }
  472. eeh_stats.slot_resets++;
  473. /* Avoid repeated reports of this failure, including problems
  474. * with other functions on this device, and functions under
  475. * bridges.
  476. */
  477. eeh_pe_mark_isolated(pe);
  478. eeh_serialize_unlock(flags);
  479. /* Most EEH events are due to device driver bugs. Having
  480. * a stack trace will help the device-driver authors figure
  481. * out what happened. So print that out.
  482. */
  483. pr_debug("EEH: %s: Frozen PHB#%x-PE#%x detected\n",
  484. __func__, pe->phb->global_number, pe->addr);
  485. eeh_send_failure_event(pe);
  486. return 1;
  487. dn_unlock:
  488. eeh_serialize_unlock(flags);
  489. return rc;
  490. }
  491. EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
  492. /**
  493. * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
  494. * @token: I/O address
  495. *
  496. * Check for an EEH failure at the given I/O address. Call this
  497. * routine if the result of a read was all 0xff's and you want to
  498. * find out if this is due to an EEH slot freeze event. This routine
  499. * will query firmware for the EEH status.
  500. *
  501. * Note this routine is safe to call in an interrupt context.
  502. */
  503. int eeh_check_failure(const volatile void __iomem *token)
  504. {
  505. unsigned long addr;
  506. struct eeh_dev *edev;
  507. /* Finding the phys addr + pci device; this is pretty quick. */
  508. addr = eeh_token_to_phys((unsigned long __force) token);
  509. edev = eeh_addr_cache_get_dev(addr);
  510. if (!edev) {
  511. eeh_stats.no_device++;
  512. return 0;
  513. }
  514. return eeh_dev_check_failure(edev);
  515. }
  516. EXPORT_SYMBOL(eeh_check_failure);
  517. /**
  518. * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
  519. * @pe: EEH PE
  520. * @function: EEH option
  521. *
  522. * This routine should be called to reenable frozen MMIO or DMA
  523. * so that it would work correctly again. It's useful while doing
  524. * recovery or log collection on the indicated device.
  525. */
  526. int eeh_pci_enable(struct eeh_pe *pe, int function)
  527. {
  528. int active_flag, rc;
  529. /*
  530. * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
  531. * Also, it's pointless to enable them on unfrozen PE. So
  532. * we have to check before enabling IO or DMA.
  533. */
  534. switch (function) {
  535. case EEH_OPT_THAW_MMIO:
  536. active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
  537. break;
  538. case EEH_OPT_THAW_DMA:
  539. active_flag = EEH_STATE_DMA_ACTIVE;
  540. break;
  541. case EEH_OPT_DISABLE:
  542. case EEH_OPT_ENABLE:
  543. case EEH_OPT_FREEZE_PE:
  544. active_flag = 0;
  545. break;
  546. default:
  547. pr_warn("%s: Invalid function %d\n",
  548. __func__, function);
  549. return -EINVAL;
  550. }
  551. /*
  552. * Check if IO or DMA has been enabled before
  553. * enabling them.
  554. */
  555. if (active_flag) {
  556. rc = eeh_ops->get_state(pe, NULL);
  557. if (rc < 0)
  558. return rc;
  559. /* Needn't enable it at all */
  560. if (rc == EEH_STATE_NOT_SUPPORT)
  561. return 0;
  562. /* It's already enabled */
  563. if (rc & active_flag)
  564. return 0;
  565. }
  566. /* Issue the request */
  567. rc = eeh_ops->set_option(pe, function);
  568. if (rc)
  569. pr_warn("%s: Unexpected state change %d on "
  570. "PHB#%x-PE#%x, err=%d\n",
  571. __func__, function, pe->phb->global_number,
  572. pe->addr, rc);
  573. /* Check if the request is finished successfully */
  574. if (active_flag) {
  575. rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  576. if (rc < 0)
  577. return rc;
  578. if (rc & active_flag)
  579. return 0;
  580. return -EIO;
  581. }
  582. return rc;
  583. }
  584. static void eeh_disable_and_save_dev_state(struct eeh_dev *edev,
  585. void *userdata)
  586. {
  587. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  588. struct pci_dev *dev = userdata;
  589. /*
  590. * The caller should have disabled and saved the
  591. * state for the specified device
  592. */
  593. if (!pdev || pdev == dev)
  594. return;
  595. /* Ensure we have D0 power state */
  596. pci_set_power_state(pdev, PCI_D0);
  597. /* Save device state */
  598. pci_save_state(pdev);
  599. /*
  600. * Disable device to avoid any DMA traffic and
  601. * interrupt from the device
  602. */
  603. pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
  604. }
  605. static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
  606. {
  607. struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
  608. struct pci_dev *dev = userdata;
  609. if (!pdev)
  610. return;
  611. /* Apply customization from firmware */
  612. if (eeh_ops->restore_config)
  613. eeh_ops->restore_config(edev);
  614. /* The caller should restore state for the specified device */
  615. if (pdev != dev)
  616. pci_restore_state(pdev);
  617. }
  618. /**
  619. * pcibios_set_pcie_reset_state - Set PCI-E reset state
  620. * @dev: pci device struct
  621. * @state: reset state to enter
  622. *
  623. * Return value:
  624. * 0 if success
  625. */
  626. int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  627. {
  628. struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
  629. struct eeh_pe *pe = eeh_dev_to_pe(edev);
  630. if (!pe) {
  631. pr_err("%s: No PE found on PCI device %s\n",
  632. __func__, pci_name(dev));
  633. return -EINVAL;
  634. }
  635. switch (state) {
  636. case pcie_deassert_reset:
  637. eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
  638. eeh_unfreeze_pe(pe);
  639. if (!(pe->type & EEH_PE_VF))
  640. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  641. eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
  642. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
  643. break;
  644. case pcie_hot_reset:
  645. eeh_pe_mark_isolated(pe);
  646. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  647. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  648. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  649. if (!(pe->type & EEH_PE_VF))
  650. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  651. eeh_ops->reset(pe, EEH_RESET_HOT);
  652. break;
  653. case pcie_warm_reset:
  654. eeh_pe_mark_isolated(pe);
  655. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
  656. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  657. eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
  658. if (!(pe->type & EEH_PE_VF))
  659. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  660. eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
  661. break;
  662. default:
  663. eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
  664. return -EINVAL;
  665. }
  666. return 0;
  667. }
  668. /**
  669. * eeh_set_dev_freset - Check the required reset for the indicated device
  670. * @edev: EEH device
  671. * @flag: return value
  672. *
  673. * Each device might have its preferred reset type: fundamental or
  674. * hot reset. The routine is used to collected the information for
  675. * the indicated device and its children so that the bunch of the
  676. * devices could be reset properly.
  677. */
  678. static void eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
  679. {
  680. struct pci_dev *dev;
  681. unsigned int *freset = (unsigned int *)flag;
  682. dev = eeh_dev_to_pci_dev(edev);
  683. if (dev)
  684. *freset |= dev->needs_freset;
  685. }
  686. static void eeh_pe_refreeze_passed(struct eeh_pe *root)
  687. {
  688. struct eeh_pe *pe;
  689. int state;
  690. eeh_for_each_pe(root, pe) {
  691. if (eeh_pe_passed(pe)) {
  692. state = eeh_ops->get_state(pe, NULL);
  693. if (state &
  694. (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) {
  695. pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n",
  696. pe->phb->global_number, pe->addr);
  697. eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
  698. }
  699. }
  700. }
  701. }
  702. /**
  703. * eeh_pe_reset_full - Complete a full reset process on the indicated PE
  704. * @pe: EEH PE
  705. * @include_passed: include passed-through devices?
  706. *
  707. * This function executes a full reset procedure on a PE, including setting
  708. * the appropriate flags, performing a fundamental or hot reset, and then
  709. * deactivating the reset status. It is designed to be used within the EEH
  710. * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
  711. * only performs a single operation at a time.
  712. *
  713. * This function will attempt to reset a PE three times before failing.
  714. */
  715. int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
  716. {
  717. int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
  718. int type = EEH_RESET_HOT;
  719. unsigned int freset = 0;
  720. int i, state = 0, ret;
  721. /*
  722. * Determine the type of reset to perform - hot or fundamental.
  723. * Hot reset is the default operation, unless any device under the
  724. * PE requires a fundamental reset.
  725. */
  726. eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
  727. if (freset)
  728. type = EEH_RESET_FUNDAMENTAL;
  729. /* Mark the PE as in reset state and block config space accesses */
  730. eeh_pe_state_mark(pe, reset_state);
  731. /* Make three attempts at resetting the bus */
  732. for (i = 0; i < 3; i++) {
  733. ret = eeh_pe_reset(pe, type, include_passed);
  734. if (!ret)
  735. ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
  736. include_passed);
  737. if (ret) {
  738. ret = -EIO;
  739. pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n",
  740. state, pe->phb->global_number, pe->addr, i + 1);
  741. continue;
  742. }
  743. if (i)
  744. pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n",
  745. pe->phb->global_number, pe->addr, i + 1);
  746. /* Wait until the PE is in a functioning state */
  747. state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
  748. if (state < 0) {
  749. pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x",
  750. pe->phb->global_number, pe->addr);
  751. ret = -ENOTRECOVERABLE;
  752. break;
  753. }
  754. if (eeh_state_active(state))
  755. break;
  756. else
  757. pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n",
  758. pe->phb->global_number, pe->addr, state, i + 1);
  759. }
  760. /* Resetting the PE may have unfrozen child PEs. If those PEs have been
  761. * (potentially) passed through to a guest, re-freeze them:
  762. */
  763. if (!include_passed)
  764. eeh_pe_refreeze_passed(pe);
  765. eeh_pe_state_clear(pe, reset_state, true);
  766. return ret;
  767. }
  768. /**
  769. * eeh_save_bars - Save device bars
  770. * @edev: PCI device associated EEH device
  771. *
  772. * Save the values of the device bars. Unlike the restore
  773. * routine, this routine is *not* recursive. This is because
  774. * PCI devices are added individually; but, for the restore,
  775. * an entire slot is reset at a time.
  776. */
  777. void eeh_save_bars(struct eeh_dev *edev)
  778. {
  779. int i;
  780. if (!edev)
  781. return;
  782. for (i = 0; i < 16; i++)
  783. eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
  784. /*
  785. * For PCI bridges including root port, we need enable bus
  786. * master explicitly. Otherwise, it can't fetch IODA table
  787. * entries correctly. So we cache the bit in advance so that
  788. * we can restore it after reset, either PHB range or PE range.
  789. */
  790. if (edev->mode & EEH_DEV_BRIDGE)
  791. edev->config_space[1] |= PCI_COMMAND_MASTER;
  792. }
  793. static int eeh_reboot_notifier(struct notifier_block *nb,
  794. unsigned long action, void *unused)
  795. {
  796. eeh_clear_flag(EEH_ENABLED);
  797. return NOTIFY_DONE;
  798. }
  799. static struct notifier_block eeh_reboot_nb = {
  800. .notifier_call = eeh_reboot_notifier,
  801. };
  802. static int eeh_device_notifier(struct notifier_block *nb,
  803. unsigned long action, void *data)
  804. {
  805. struct device *dev = data;
  806. switch (action) {
  807. /*
  808. * Note: It's not possible to perform EEH device addition (i.e.
  809. * {pseries,pnv}_pcibios_bus_add_device()) here because it depends on
  810. * the device's resources, which have not yet been set up.
  811. */
  812. case BUS_NOTIFY_DEL_DEVICE:
  813. eeh_remove_device(to_pci_dev(dev));
  814. break;
  815. default:
  816. break;
  817. }
  818. return NOTIFY_DONE;
  819. }
  820. static struct notifier_block eeh_device_nb = {
  821. .notifier_call = eeh_device_notifier,
  822. };
  823. /**
  824. * eeh_init - System wide EEH initialization
  825. * @ops: struct to trace EEH operation callback functions
  826. *
  827. * It's the platform's job to call this from an arch_initcall().
  828. */
  829. int eeh_init(struct eeh_ops *ops)
  830. {
  831. struct pci_controller *hose, *tmp;
  832. int ret = 0;
  833. /* the platform should only initialise EEH once */
  834. if (WARN_ON(eeh_ops))
  835. return -EEXIST;
  836. if (WARN_ON(!ops))
  837. return -ENOENT;
  838. eeh_ops = ops;
  839. /* Register reboot notifier */
  840. ret = register_reboot_notifier(&eeh_reboot_nb);
  841. if (ret) {
  842. pr_warn("%s: Failed to register reboot notifier (%d)\n",
  843. __func__, ret);
  844. return ret;
  845. }
  846. ret = bus_register_notifier(&pci_bus_type, &eeh_device_nb);
  847. if (ret) {
  848. pr_warn("%s: Failed to register bus notifier (%d)\n",
  849. __func__, ret);
  850. return ret;
  851. }
  852. /* Initialize PHB PEs */
  853. list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
  854. eeh_phb_pe_create(hose);
  855. eeh_addr_cache_init();
  856. /* Initialize EEH event */
  857. return eeh_event_init();
  858. }
  859. /**
  860. * eeh_probe_device() - Perform EEH initialization for the indicated pci device
  861. * @dev: pci device for which to set up EEH
  862. *
  863. * This routine must be used to complete EEH initialization for PCI
  864. * devices that were added after system boot (e.g. hotplug, dlpar).
  865. */
  866. void eeh_probe_device(struct pci_dev *dev)
  867. {
  868. struct eeh_dev *edev;
  869. pr_debug("EEH: Adding device %s\n", pci_name(dev));
  870. /*
  871. * pci_dev_to_eeh_dev() can only work if eeh_probe_dev() was
  872. * already called for this device.
  873. */
  874. if (WARN_ON_ONCE(pci_dev_to_eeh_dev(dev))) {
  875. pci_dbg(dev, "Already bound to an eeh_dev!\n");
  876. return;
  877. }
  878. edev = eeh_ops->probe(dev);
  879. if (!edev) {
  880. pr_debug("EEH: Adding device failed\n");
  881. return;
  882. }
  883. /*
  884. * FIXME: We rely on pcibios_release_device() to remove the
  885. * existing EEH state. The release function is only called if
  886. * the pci_dev's refcount drops to zero so if something is
  887. * keeping a ref to a device (e.g. a filesystem) we need to
  888. * remove the old EEH state.
  889. *
  890. * FIXME: HEY MA, LOOK AT ME, NO LOCKING!
  891. */
  892. if (edev->pdev && edev->pdev != dev) {
  893. eeh_pe_tree_remove(edev);
  894. eeh_addr_cache_rmv_dev(edev->pdev);
  895. eeh_sysfs_remove_device(edev->pdev);
  896. /*
  897. * We definitely should have the PCI device removed
  898. * though it wasn't correctly. So we needn't call
  899. * into error handler afterwards.
  900. */
  901. edev->mode |= EEH_DEV_NO_HANDLER;
  902. }
  903. /* bind the pdev and the edev together */
  904. edev->pdev = dev;
  905. dev->dev.archdata.edev = edev;
  906. eeh_addr_cache_insert_dev(dev);
  907. eeh_sysfs_add_device(dev);
  908. }
  909. /**
  910. * eeh_remove_device - Undo EEH setup for the indicated pci device
  911. * @dev: pci device to be removed
  912. *
  913. * This routine should be called when a device is removed from
  914. * a running system (e.g. by hotplug or dlpar). It unregisters
  915. * the PCI device from the EEH subsystem. I/O errors affecting
  916. * this device will no longer be detected after this call; thus,
  917. * i/o errors affecting this slot may leave this device unusable.
  918. */
  919. void eeh_remove_device(struct pci_dev *dev)
  920. {
  921. struct eeh_dev *edev;
  922. if (!dev || !eeh_enabled())
  923. return;
  924. edev = pci_dev_to_eeh_dev(dev);
  925. /* Unregister the device with the EEH/PCI address search system */
  926. dev_dbg(&dev->dev, "EEH: Removing device\n");
  927. if (!edev || !edev->pdev || !edev->pe) {
  928. dev_dbg(&dev->dev, "EEH: Device not referenced!\n");
  929. return;
  930. }
  931. /*
  932. * During the hotplug for EEH error recovery, we need the EEH
  933. * device attached to the parent PE in order for BAR restore
  934. * a bit later. So we keep it for BAR restore and remove it
  935. * from the parent PE during the BAR resotre.
  936. */
  937. edev->pdev = NULL;
  938. /*
  939. * eeh_sysfs_remove_device() uses pci_dev_to_eeh_dev() so we need to
  940. * remove the sysfs files before clearing dev.archdata.edev
  941. */
  942. if (edev->mode & EEH_DEV_SYSFS)
  943. eeh_sysfs_remove_device(dev);
  944. /*
  945. * We're removing from the PCI subsystem, that means
  946. * the PCI device driver can't support EEH or not
  947. * well. So we rely on hotplug completely to do recovery
  948. * for the specific PCI device.
  949. */
  950. edev->mode |= EEH_DEV_NO_HANDLER;
  951. eeh_addr_cache_rmv_dev(dev);
  952. /*
  953. * The flag "in_error" is used to trace EEH devices for VFs
  954. * in error state or not. It's set in eeh_report_error(). If
  955. * it's not set, eeh_report_{reset,resume}() won't be called
  956. * for the VF EEH device.
  957. */
  958. edev->in_error = false;
  959. dev->dev.archdata.edev = NULL;
  960. if (!(edev->pe->state & EEH_PE_KEEP))
  961. eeh_pe_tree_remove(edev);
  962. else
  963. edev->mode |= EEH_DEV_DISCONNECTED;
  964. }
  965. int eeh_unfreeze_pe(struct eeh_pe *pe)
  966. {
  967. int ret;
  968. ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
  969. if (ret) {
  970. pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
  971. __func__, ret, pe->phb->global_number, pe->addr);
  972. return ret;
  973. }
  974. ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
  975. if (ret) {
  976. pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
  977. __func__, ret, pe->phb->global_number, pe->addr);
  978. return ret;
  979. }
  980. return ret;
  981. }
  982. static struct pci_device_id eeh_reset_ids[] = {
  983. { PCI_DEVICE(0x19a2, 0x0710) }, /* Emulex, BE */
  984. { PCI_DEVICE(0x10df, 0xe220) }, /* Emulex, Lancer */
  985. { PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
  986. { 0 }
  987. };
  988. static int eeh_pe_change_owner(struct eeh_pe *pe)
  989. {
  990. struct eeh_dev *edev, *tmp;
  991. struct pci_dev *pdev;
  992. struct pci_device_id *id;
  993. int ret;
  994. /* Check PE state */
  995. ret = eeh_ops->get_state(pe, NULL);
  996. if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
  997. return 0;
  998. /* Unfrozen PE, nothing to do */
  999. if (eeh_state_active(ret))
  1000. return 0;
  1001. /* Frozen PE, check if it needs PE level reset */
  1002. eeh_pe_for_each_dev(pe, edev, tmp) {
  1003. pdev = eeh_dev_to_pci_dev(edev);
  1004. if (!pdev)
  1005. continue;
  1006. for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
  1007. if (id->vendor != PCI_ANY_ID &&
  1008. id->vendor != pdev->vendor)
  1009. continue;
  1010. if (id->device != PCI_ANY_ID &&
  1011. id->device != pdev->device)
  1012. continue;
  1013. if (id->subvendor != PCI_ANY_ID &&
  1014. id->subvendor != pdev->subsystem_vendor)
  1015. continue;
  1016. if (id->subdevice != PCI_ANY_ID &&
  1017. id->subdevice != pdev->subsystem_device)
  1018. continue;
  1019. return eeh_pe_reset_and_recover(pe);
  1020. }
  1021. }
  1022. ret = eeh_unfreeze_pe(pe);
  1023. if (!ret)
  1024. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
  1025. return ret;
  1026. }
  1027. /**
  1028. * eeh_dev_open - Increase count of pass through devices for PE
  1029. * @pdev: PCI device
  1030. *
  1031. * Increase count of passed through devices for the indicated
  1032. * PE. In the result, the EEH errors detected on the PE won't be
  1033. * reported. The PE owner will be responsible for detection
  1034. * and recovery.
  1035. */
  1036. int eeh_dev_open(struct pci_dev *pdev)
  1037. {
  1038. struct eeh_dev *edev;
  1039. int ret = -ENODEV;
  1040. mutex_lock(&eeh_dev_mutex);
  1041. /* No PCI device ? */
  1042. if (!pdev)
  1043. goto out;
  1044. /* No EEH device or PE ? */
  1045. edev = pci_dev_to_eeh_dev(pdev);
  1046. if (!edev || !edev->pe)
  1047. goto out;
  1048. /*
  1049. * The PE might have been put into frozen state, but we
  1050. * didn't detect that yet. The passed through PCI devices
  1051. * in frozen PE won't work properly. Clear the frozen state
  1052. * in advance.
  1053. */
  1054. ret = eeh_pe_change_owner(edev->pe);
  1055. if (ret)
  1056. goto out;
  1057. /* Increase PE's pass through count */
  1058. atomic_inc(&edev->pe->pass_dev_cnt);
  1059. mutex_unlock(&eeh_dev_mutex);
  1060. return 0;
  1061. out:
  1062. mutex_unlock(&eeh_dev_mutex);
  1063. return ret;
  1064. }
  1065. EXPORT_SYMBOL_GPL(eeh_dev_open);
  1066. /**
  1067. * eeh_dev_release - Decrease count of pass through devices for PE
  1068. * @pdev: PCI device
  1069. *
  1070. * Decrease count of pass through devices for the indicated PE. If
  1071. * there is no passed through device in PE, the EEH errors detected
  1072. * on the PE will be reported and handled as usual.
  1073. */
  1074. void eeh_dev_release(struct pci_dev *pdev)
  1075. {
  1076. struct eeh_dev *edev;
  1077. mutex_lock(&eeh_dev_mutex);
  1078. /* No PCI device ? */
  1079. if (!pdev)
  1080. goto out;
  1081. /* No EEH device ? */
  1082. edev = pci_dev_to_eeh_dev(pdev);
  1083. if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
  1084. goto out;
  1085. /* Decrease PE's pass through count */
  1086. WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
  1087. eeh_pe_change_owner(edev->pe);
  1088. out:
  1089. mutex_unlock(&eeh_dev_mutex);
  1090. }
  1091. EXPORT_SYMBOL(eeh_dev_release);
  1092. #ifdef CONFIG_IOMMU_API
  1093. static int dev_has_iommu_table(struct device *dev, void *data)
  1094. {
  1095. struct pci_dev *pdev = to_pci_dev(dev);
  1096. struct pci_dev **ppdev = data;
  1097. if (!dev)
  1098. return 0;
  1099. if (device_iommu_mapped(dev)) {
  1100. *ppdev = pdev;
  1101. return 1;
  1102. }
  1103. return 0;
  1104. }
  1105. /**
  1106. * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
  1107. * @group: IOMMU group
  1108. *
  1109. * The routine is called to convert IOMMU group to EEH PE.
  1110. */
  1111. struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
  1112. {
  1113. struct pci_dev *pdev = NULL;
  1114. struct eeh_dev *edev;
  1115. int ret;
  1116. /* No IOMMU group ? */
  1117. if (!group)
  1118. return NULL;
  1119. ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
  1120. if (!ret || !pdev)
  1121. return NULL;
  1122. /* No EEH device or PE ? */
  1123. edev = pci_dev_to_eeh_dev(pdev);
  1124. if (!edev || !edev->pe)
  1125. return NULL;
  1126. return edev->pe;
  1127. }
  1128. EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
  1129. #endif /* CONFIG_IOMMU_API */
  1130. /**
  1131. * eeh_pe_set_option - Set options for the indicated PE
  1132. * @pe: EEH PE
  1133. * @option: requested option
  1134. *
  1135. * The routine is called to enable or disable EEH functionality
  1136. * on the indicated PE, to enable IO or DMA for the frozen PE.
  1137. */
  1138. int eeh_pe_set_option(struct eeh_pe *pe, int option)
  1139. {
  1140. int ret = 0;
  1141. /* Invalid PE ? */
  1142. if (!pe)
  1143. return -ENODEV;
  1144. /*
  1145. * EEH functionality could possibly be disabled, just
  1146. * return error for the case. And the EEH functionality
  1147. * isn't expected to be disabled on one specific PE.
  1148. */
  1149. switch (option) {
  1150. case EEH_OPT_ENABLE:
  1151. if (eeh_enabled()) {
  1152. ret = eeh_pe_change_owner(pe);
  1153. break;
  1154. }
  1155. ret = -EIO;
  1156. break;
  1157. case EEH_OPT_DISABLE:
  1158. break;
  1159. case EEH_OPT_THAW_MMIO:
  1160. case EEH_OPT_THAW_DMA:
  1161. case EEH_OPT_FREEZE_PE:
  1162. if (!eeh_ops || !eeh_ops->set_option) {
  1163. ret = -ENOENT;
  1164. break;
  1165. }
  1166. ret = eeh_pci_enable(pe, option);
  1167. break;
  1168. default:
  1169. pr_debug("%s: Option %d out of range (%d, %d)\n",
  1170. __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
  1171. ret = -EINVAL;
  1172. }
  1173. return ret;
  1174. }
  1175. EXPORT_SYMBOL_GPL(eeh_pe_set_option);
  1176. /**
  1177. * eeh_pe_get_state - Retrieve PE's state
  1178. * @pe: EEH PE
  1179. *
  1180. * Retrieve the PE's state, which includes 3 aspects: enabled
  1181. * DMA, enabled IO and asserted reset.
  1182. */
  1183. int eeh_pe_get_state(struct eeh_pe *pe)
  1184. {
  1185. int result, ret = 0;
  1186. bool rst_active, dma_en, mmio_en;
  1187. /* Existing PE ? */
  1188. if (!pe)
  1189. return -ENODEV;
  1190. if (!eeh_ops || !eeh_ops->get_state)
  1191. return -ENOENT;
  1192. /*
  1193. * If the parent PE is owned by the host kernel and is undergoing
  1194. * error recovery, we should return the PE state as temporarily
  1195. * unavailable so that the error recovery on the guest is suspended
  1196. * until the recovery completes on the host.
  1197. */
  1198. if (pe->parent &&
  1199. !(pe->state & EEH_PE_REMOVED) &&
  1200. (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
  1201. return EEH_PE_STATE_UNAVAIL;
  1202. result = eeh_ops->get_state(pe, NULL);
  1203. rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
  1204. dma_en = !!(result & EEH_STATE_DMA_ENABLED);
  1205. mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
  1206. if (rst_active)
  1207. ret = EEH_PE_STATE_RESET;
  1208. else if (dma_en && mmio_en)
  1209. ret = EEH_PE_STATE_NORMAL;
  1210. else if (!dma_en && !mmio_en)
  1211. ret = EEH_PE_STATE_STOPPED_IO_DMA;
  1212. else if (!dma_en && mmio_en)
  1213. ret = EEH_PE_STATE_STOPPED_DMA;
  1214. else
  1215. ret = EEH_PE_STATE_UNAVAIL;
  1216. return ret;
  1217. }
  1218. EXPORT_SYMBOL_GPL(eeh_pe_get_state);
  1219. static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
  1220. {
  1221. struct eeh_dev *edev, *tmp;
  1222. struct pci_dev *pdev;
  1223. int ret = 0;
  1224. eeh_pe_restore_bars(pe);
  1225. /*
  1226. * Reenable PCI devices as the devices passed
  1227. * through are always enabled before the reset.
  1228. */
  1229. eeh_pe_for_each_dev(pe, edev, tmp) {
  1230. pdev = eeh_dev_to_pci_dev(edev);
  1231. if (!pdev)
  1232. continue;
  1233. ret = pci_reenable_device(pdev);
  1234. if (ret) {
  1235. pr_warn("%s: Failure %d reenabling %s\n",
  1236. __func__, ret, pci_name(pdev));
  1237. return ret;
  1238. }
  1239. }
  1240. /* The PE is still in frozen state */
  1241. if (include_passed || !eeh_pe_passed(pe)) {
  1242. ret = eeh_unfreeze_pe(pe);
  1243. } else
  1244. pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n",
  1245. pe->phb->global_number, pe->addr);
  1246. if (!ret)
  1247. eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
  1248. return ret;
  1249. }
  1250. /**
  1251. * eeh_pe_reset - Issue PE reset according to specified type
  1252. * @pe: EEH PE
  1253. * @option: reset type
  1254. * @include_passed: include passed-through devices?
  1255. *
  1256. * The routine is called to reset the specified PE with the
  1257. * indicated type, either fundamental reset or hot reset.
  1258. * PE reset is the most important part for error recovery.
  1259. */
  1260. int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
  1261. {
  1262. int ret = 0;
  1263. /* Invalid PE ? */
  1264. if (!pe)
  1265. return -ENODEV;
  1266. if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
  1267. return -ENOENT;
  1268. switch (option) {
  1269. case EEH_RESET_DEACTIVATE:
  1270. ret = eeh_ops->reset(pe, option);
  1271. eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
  1272. if (ret)
  1273. break;
  1274. ret = eeh_pe_reenable_devices(pe, include_passed);
  1275. break;
  1276. case EEH_RESET_HOT:
  1277. case EEH_RESET_FUNDAMENTAL:
  1278. /*
  1279. * Proactively freeze the PE to drop all MMIO access
  1280. * during reset, which should be banned as it's always
  1281. * cause recursive EEH error.
  1282. */
  1283. eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
  1284. eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
  1285. ret = eeh_ops->reset(pe, option);
  1286. break;
  1287. default:
  1288. pr_debug("%s: Unsupported option %d\n",
  1289. __func__, option);
  1290. ret = -EINVAL;
  1291. }
  1292. return ret;
  1293. }
  1294. EXPORT_SYMBOL_GPL(eeh_pe_reset);
  1295. /**
  1296. * eeh_pe_configure - Configure PCI bridges after PE reset
  1297. * @pe: EEH PE
  1298. *
  1299. * The routine is called to restore the PCI config space for
  1300. * those PCI devices, especially PCI bridges affected by PE
  1301. * reset issued previously.
  1302. */
  1303. int eeh_pe_configure(struct eeh_pe *pe)
  1304. {
  1305. int ret = 0;
  1306. /* Invalid PE ? */
  1307. if (!pe)
  1308. return -ENODEV;
  1309. return ret;
  1310. }
  1311. EXPORT_SYMBOL_GPL(eeh_pe_configure);
  1312. /**
  1313. * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
  1314. * @pe: the indicated PE
  1315. * @type: error type
  1316. * @func: error function
  1317. * @addr: address
  1318. * @mask: address mask
  1319. *
  1320. * The routine is called to inject the specified PCI error, which
  1321. * is determined by @type and @func, to the indicated PE for
  1322. * testing purpose.
  1323. */
  1324. int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
  1325. unsigned long addr, unsigned long mask)
  1326. {
  1327. /* Invalid PE ? */
  1328. if (!pe)
  1329. return -ENODEV;
  1330. /* Unsupported operation ? */
  1331. if (!eeh_ops || !eeh_ops->err_inject)
  1332. return -ENOENT;
  1333. /* Check on PCI error type */
  1334. if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
  1335. return -EINVAL;
  1336. /* Check on PCI error function */
  1337. if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
  1338. return -EINVAL;
  1339. return eeh_ops->err_inject(pe, type, func, addr, mask);
  1340. }
  1341. EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
  1342. #ifdef CONFIG_PROC_FS
  1343. static int proc_eeh_show(struct seq_file *m, void *v)
  1344. {
  1345. if (!eeh_enabled()) {
  1346. seq_printf(m, "EEH Subsystem is globally disabled\n");
  1347. seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
  1348. } else {
  1349. seq_printf(m, "EEH Subsystem is enabled\n");
  1350. seq_printf(m,
  1351. "no device=%llu\n"
  1352. "no device node=%llu\n"
  1353. "no config address=%llu\n"
  1354. "check not wanted=%llu\n"
  1355. "eeh_total_mmio_ffs=%llu\n"
  1356. "eeh_false_positives=%llu\n"
  1357. "eeh_slot_resets=%llu\n",
  1358. eeh_stats.no_device,
  1359. eeh_stats.no_dn,
  1360. eeh_stats.no_cfg_addr,
  1361. eeh_stats.ignored_check,
  1362. eeh_stats.total_mmio_ffs,
  1363. eeh_stats.false_positives,
  1364. eeh_stats.slot_resets);
  1365. }
  1366. return 0;
  1367. }
  1368. #endif /* CONFIG_PROC_FS */
  1369. #ifdef CONFIG_DEBUG_FS
  1370. static struct pci_dev *eeh_debug_lookup_pdev(struct file *filp,
  1371. const char __user *user_buf,
  1372. size_t count, loff_t *ppos)
  1373. {
  1374. uint32_t domain, bus, dev, fn;
  1375. struct pci_dev *pdev;
  1376. char buf[20];
  1377. int ret;
  1378. memset(buf, 0, sizeof(buf));
  1379. ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
  1380. if (!ret)
  1381. return ERR_PTR(-EFAULT);
  1382. ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
  1383. if (ret != 4) {
  1384. pr_err("%s: expected 4 args, got %d\n", __func__, ret);
  1385. return ERR_PTR(-EINVAL);
  1386. }
  1387. pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
  1388. if (!pdev)
  1389. return ERR_PTR(-ENODEV);
  1390. return pdev;
  1391. }
  1392. static int eeh_enable_dbgfs_set(void *data, u64 val)
  1393. {
  1394. if (val)
  1395. eeh_clear_flag(EEH_FORCE_DISABLED);
  1396. else
  1397. eeh_add_flag(EEH_FORCE_DISABLED);
  1398. return 0;
  1399. }
  1400. static int eeh_enable_dbgfs_get(void *data, u64 *val)
  1401. {
  1402. if (eeh_enabled())
  1403. *val = 0x1ul;
  1404. else
  1405. *val = 0x0ul;
  1406. return 0;
  1407. }
  1408. DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
  1409. eeh_enable_dbgfs_set, "0x%llx\n");
  1410. static ssize_t eeh_force_recover_write(struct file *filp,
  1411. const char __user *user_buf,
  1412. size_t count, loff_t *ppos)
  1413. {
  1414. struct pci_controller *hose;
  1415. uint32_t phbid, pe_no;
  1416. struct eeh_pe *pe;
  1417. char buf[20];
  1418. int ret;
  1419. ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
  1420. if (!ret)
  1421. return -EFAULT;
  1422. /*
  1423. * When PE is NULL the event is a "special" event. Rather than
  1424. * recovering a specific PE it forces the EEH core to scan for failed
  1425. * PHBs and recovers each. This needs to be done before any device
  1426. * recoveries can occur.
  1427. */
  1428. if (!strncmp(buf, "hwcheck", 7)) {
  1429. __eeh_send_failure_event(NULL);
  1430. return count;
  1431. }
  1432. ret = sscanf(buf, "%x:%x", &phbid, &pe_no);
  1433. if (ret != 2)
  1434. return -EINVAL;
  1435. hose = pci_find_controller_for_domain(phbid);
  1436. if (!hose)
  1437. return -ENODEV;
  1438. /* Retrieve PE */
  1439. pe = eeh_pe_get(hose, pe_no);
  1440. if (!pe)
  1441. return -ENODEV;
  1442. /*
  1443. * We don't do any state checking here since the detection
  1444. * process is async to the recovery process. The recovery
  1445. * thread *should* not break even if we schedule a recovery
  1446. * from an odd state (e.g. PE removed, or recovery of a
  1447. * non-isolated PE)
  1448. */
  1449. __eeh_send_failure_event(pe);
  1450. return ret < 0 ? ret : count;
  1451. }
  1452. static const struct file_operations eeh_force_recover_fops = {
  1453. .open = simple_open,
  1454. .llseek = no_llseek,
  1455. .write = eeh_force_recover_write,
  1456. };
  1457. static ssize_t eeh_debugfs_dev_usage(struct file *filp,
  1458. char __user *user_buf,
  1459. size_t count, loff_t *ppos)
  1460. {
  1461. static const char usage[] = "input format: <domain>:<bus>:<dev>.<fn>\n";
  1462. return simple_read_from_buffer(user_buf, count, ppos,
  1463. usage, sizeof(usage) - 1);
  1464. }
  1465. static ssize_t eeh_dev_check_write(struct file *filp,
  1466. const char __user *user_buf,
  1467. size_t count, loff_t *ppos)
  1468. {
  1469. struct pci_dev *pdev;
  1470. struct eeh_dev *edev;
  1471. int ret;
  1472. pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
  1473. if (IS_ERR(pdev))
  1474. return PTR_ERR(pdev);
  1475. edev = pci_dev_to_eeh_dev(pdev);
  1476. if (!edev) {
  1477. pci_err(pdev, "No eeh_dev for this device!\n");
  1478. pci_dev_put(pdev);
  1479. return -ENODEV;
  1480. }
  1481. ret = eeh_dev_check_failure(edev);
  1482. pci_info(pdev, "eeh_dev_check_failure(%s) = %d\n",
  1483. pci_name(pdev), ret);
  1484. pci_dev_put(pdev);
  1485. return count;
  1486. }
  1487. static const struct file_operations eeh_dev_check_fops = {
  1488. .open = simple_open,
  1489. .llseek = no_llseek,
  1490. .write = eeh_dev_check_write,
  1491. .read = eeh_debugfs_dev_usage,
  1492. };
  1493. static int eeh_debugfs_break_device(struct pci_dev *pdev)
  1494. {
  1495. struct resource *bar = NULL;
  1496. void __iomem *mapped;
  1497. u16 old, bit;
  1498. int i, pos;
  1499. /* Do we have an MMIO BAR to disable? */
  1500. for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
  1501. struct resource *r = &pdev->resource[i];
  1502. if (!r->flags || !r->start)
  1503. continue;
  1504. if (r->flags & IORESOURCE_IO)
  1505. continue;
  1506. if (r->flags & IORESOURCE_UNSET)
  1507. continue;
  1508. bar = r;
  1509. break;
  1510. }
  1511. if (!bar) {
  1512. pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n");
  1513. return -ENXIO;
  1514. }
  1515. pci_err(pdev, "Going to break: %pR\n", bar);
  1516. if (pdev->is_virtfn) {
  1517. #ifndef CONFIG_PCI_IOV
  1518. return -ENXIO;
  1519. #else
  1520. /*
  1521. * VFs don't have a per-function COMMAND register, so the best
  1522. * we can do is clear the Memory Space Enable bit in the PF's
  1523. * SRIOV control reg.
  1524. *
  1525. * Unfortunately, this requires that we have a PF (i.e doesn't
  1526. * work for a passed-through VF) and it has the potential side
  1527. * effect of also causing an EEH on every other VF under the
  1528. * PF. Oh well.
  1529. */
  1530. pdev = pdev->physfn;
  1531. if (!pdev)
  1532. return -ENXIO; /* passed through VFs have no PF */
  1533. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1534. pos += PCI_SRIOV_CTRL;
  1535. bit = PCI_SRIOV_CTRL_MSE;
  1536. #endif /* !CONFIG_PCI_IOV */
  1537. } else {
  1538. bit = PCI_COMMAND_MEMORY;
  1539. pos = PCI_COMMAND;
  1540. }
  1541. /*
  1542. * Process here is:
  1543. *
  1544. * 1. Disable Memory space.
  1545. *
  1546. * 2. Perform an MMIO to the device. This should result in an error
  1547. * (CA / UR) being raised by the device which results in an EEH
  1548. * PE freeze. Using the in_8() accessor skips the eeh detection hook
  1549. * so the freeze hook so the EEH Detection machinery won't be
  1550. * triggered here. This is to match the usual behaviour of EEH
  1551. * where the HW will asynchronously freeze a PE and it's up to
  1552. * the kernel to notice and deal with it.
  1553. *
  1554. * 3. Turn Memory space back on. This is more important for VFs
  1555. * since recovery will probably fail if we don't. For normal
  1556. * the COMMAND register is reset as a part of re-initialising
  1557. * the device.
  1558. *
  1559. * Breaking stuff is the point so who cares if it's racy ;)
  1560. */
  1561. pci_read_config_word(pdev, pos, &old);
  1562. mapped = ioremap(bar->start, PAGE_SIZE);
  1563. if (!mapped) {
  1564. pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar);
  1565. return -ENXIO;
  1566. }
  1567. pci_write_config_word(pdev, pos, old & ~bit);
  1568. in_8(mapped);
  1569. pci_write_config_word(pdev, pos, old);
  1570. iounmap(mapped);
  1571. return 0;
  1572. }
  1573. static ssize_t eeh_dev_break_write(struct file *filp,
  1574. const char __user *user_buf,
  1575. size_t count, loff_t *ppos)
  1576. {
  1577. struct pci_dev *pdev;
  1578. int ret;
  1579. pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
  1580. if (IS_ERR(pdev))
  1581. return PTR_ERR(pdev);
  1582. ret = eeh_debugfs_break_device(pdev);
  1583. pci_dev_put(pdev);
  1584. if (ret < 0)
  1585. return ret;
  1586. return count;
  1587. }
  1588. static const struct file_operations eeh_dev_break_fops = {
  1589. .open = simple_open,
  1590. .llseek = no_llseek,
  1591. .write = eeh_dev_break_write,
  1592. .read = eeh_debugfs_dev_usage,
  1593. };
  1594. static ssize_t eeh_dev_can_recover(struct file *filp,
  1595. const char __user *user_buf,
  1596. size_t count, loff_t *ppos)
  1597. {
  1598. struct pci_driver *drv;
  1599. struct pci_dev *pdev;
  1600. size_t ret;
  1601. pdev = eeh_debug_lookup_pdev(filp, user_buf, count, ppos);
  1602. if (IS_ERR(pdev))
  1603. return PTR_ERR(pdev);
  1604. /*
  1605. * In order for error recovery to work the driver needs to implement
  1606. * .error_detected(), so it can quiesce IO to the device, and
  1607. * .slot_reset() so it can re-initialise the device after a reset.
  1608. *
  1609. * Ideally they'd implement .resume() too, but some drivers which
  1610. * we need to support (notably IPR) don't so I guess we can tolerate
  1611. * that.
  1612. *
  1613. * .mmio_enabled() is mostly there as a work-around for devices which
  1614. * take forever to re-init after a hot reset. Implementing that is
  1615. * strictly optional.
  1616. */
  1617. drv = pci_dev_driver(pdev);
  1618. if (drv &&
  1619. drv->err_handler &&
  1620. drv->err_handler->error_detected &&
  1621. drv->err_handler->slot_reset) {
  1622. ret = count;
  1623. } else {
  1624. ret = -EOPNOTSUPP;
  1625. }
  1626. pci_dev_put(pdev);
  1627. return ret;
  1628. }
  1629. static const struct file_operations eeh_dev_can_recover_fops = {
  1630. .open = simple_open,
  1631. .llseek = no_llseek,
  1632. .write = eeh_dev_can_recover,
  1633. .read = eeh_debugfs_dev_usage,
  1634. };
  1635. #endif
  1636. static int __init eeh_init_proc(void)
  1637. {
  1638. if (machine_is(pseries) || machine_is(powernv)) {
  1639. proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
  1640. #ifdef CONFIG_DEBUG_FS
  1641. debugfs_create_file_unsafe("eeh_enable", 0600,
  1642. arch_debugfs_dir, NULL,
  1643. &eeh_enable_dbgfs_ops);
  1644. debugfs_create_u32("eeh_max_freezes", 0600,
  1645. arch_debugfs_dir, &eeh_max_freezes);
  1646. debugfs_create_bool("eeh_disable_recovery", 0600,
  1647. arch_debugfs_dir,
  1648. &eeh_debugfs_no_recover);
  1649. debugfs_create_file_unsafe("eeh_dev_check", 0600,
  1650. arch_debugfs_dir, NULL,
  1651. &eeh_dev_check_fops);
  1652. debugfs_create_file_unsafe("eeh_dev_break", 0600,
  1653. arch_debugfs_dir, NULL,
  1654. &eeh_dev_break_fops);
  1655. debugfs_create_file_unsafe("eeh_force_recover", 0600,
  1656. arch_debugfs_dir, NULL,
  1657. &eeh_force_recover_fops);
  1658. debugfs_create_file_unsafe("eeh_dev_can_recover", 0600,
  1659. arch_debugfs_dir, NULL,
  1660. &eeh_dev_can_recover_fops);
  1661. eeh_cache_debugfs_init();
  1662. #endif
  1663. }
  1664. return 0;
  1665. }
  1666. __initcall(eeh_init_proc);