gamecube-head.S 2.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * arch/powerpc/boot/gamecube-head.S
  4. *
  5. * Nintendo GameCube bootwrapper entry.
  6. * Copyright (C) 2004-2009 The GameCube Linux Team
  7. * Copyright (C) 2008,2009 Albert Herranz
  8. */
  9. #include "ppc_asm.h"
  10. /*
  11. * The entry code does no assumptions regarding:
  12. * - if the data and instruction caches are enabled or not
  13. * - if the MMU is enabled or not
  14. *
  15. * We enable the caches if not already enabled, enable the MMU with an
  16. * identity mapping scheme and jump to the start code.
  17. */
  18. .text
  19. .globl _zimage_start
  20. _zimage_start:
  21. /* turn the MMU off */
  22. mfmsr 9
  23. rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */
  24. bcl 20, 31, 1f
  25. 1:
  26. mflr 8
  27. clrlwi 8, 8, 3 /* convert to a real address */
  28. addi 8, 8, _mmu_off - 1b
  29. mtsrr0 8
  30. mtsrr1 9
  31. rfi
  32. _mmu_off:
  33. /* MMU disabled */
  34. /* setup BATs */
  35. isync
  36. li 8, 0
  37. mtspr 0x210, 8 /* IBAT0U */
  38. mtspr 0x212, 8 /* IBAT1U */
  39. mtspr 0x214, 8 /* IBAT2U */
  40. mtspr 0x216, 8 /* IBAT3U */
  41. mtspr 0x218, 8 /* DBAT0U */
  42. mtspr 0x21a, 8 /* DBAT1U */
  43. mtspr 0x21c, 8 /* DBAT2U */
  44. mtspr 0x21e, 8 /* DBAT3U */
  45. li 8, 0x01ff /* first 16MiB */
  46. li 9, 0x0002 /* rw */
  47. mtspr 0x211, 9 /* IBAT0L */
  48. mtspr 0x210, 8 /* IBAT0U */
  49. mtspr 0x219, 9 /* DBAT0L */
  50. mtspr 0x218, 8 /* DBAT0U */
  51. lis 8, 0x0c00 /* I/O mem */
  52. ori 8, 8, 0x3ff /* 32MiB */
  53. lis 9, 0x0c00
  54. ori 9, 9, 0x002a /* uncached, guarded, rw */
  55. mtspr 0x21b, 9 /* DBAT1L */
  56. mtspr 0x21a, 8 /* DBAT1U */
  57. lis 8, 0x0100 /* next 8MiB */
  58. ori 8, 8, 0x00ff /* 8MiB */
  59. lis 9, 0x0100
  60. ori 9, 9, 0x0002 /* rw */
  61. mtspr 0x215, 9 /* IBAT2L */
  62. mtspr 0x214, 8 /* IBAT2U */
  63. mtspr 0x21d, 9 /* DBAT2L */
  64. mtspr 0x21c, 8 /* DBAT2U */
  65. /* enable and invalidate the caches if not already enabled */
  66. mfspr 8, 0x3f0 /* HID0 */
  67. andi. 0, 8, (1<<15) /* HID0_ICE */
  68. bne 1f
  69. ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/
  70. 1:
  71. andi. 0, 8, (1<<14) /* HID0_DCE */
  72. bne 1f
  73. ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/
  74. 1:
  75. mtspr 0x3f0, 8 /* HID0 */
  76. isync
  77. /* initialize arguments */
  78. li 3, 0
  79. li 4, 0
  80. li 5, 0
  81. /* turn the MMU on */
  82. bcl 20, 31, 1f
  83. 1:
  84. mflr 8
  85. addi 8, 8, _mmu_on - 1b
  86. mfmsr 9
  87. ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */
  88. mtsrr0 8
  89. mtsrr1 9
  90. sync
  91. rfi
  92. _mmu_on:
  93. b _zimage_start_lib