tqm8560.dts 8.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TQM 8560 Device Tree Source
  4. *
  5. * Copyright 2008 Freescale Semiconductor Inc.
  6. * Copyright 2008 Wolfgang Grandegger <[email protected]>
  7. */
  8. /dts-v1/;
  9. /include/ "fsl/e500v1_power_isa.dtsi"
  10. / {
  11. model = "tqc,tqm8560";
  12. compatible = "tqc,tqm8560";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. aliases {
  16. ethernet0 = &enet0;
  17. ethernet1 = &enet1;
  18. ethernet2 = &enet2;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8560@0 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. d-cache-line-size = <32>;
  30. i-cache-line-size = <32>;
  31. d-cache-size = <32768>;
  32. i-cache-size = <32768>;
  33. timebase-frequency = <0>;
  34. bus-frequency = <0>;
  35. clock-frequency = <0>;
  36. next-level-cache = <&L2>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x10000000>;
  42. };
  43. soc@e0000000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. device_type = "soc";
  47. ranges = <0x0 0xe0000000 0x100000>;
  48. bus-frequency = <0>;
  49. compatible = "fsl,mpc8560-immr", "simple-bus";
  50. ecm-law@0 {
  51. compatible = "fsl,ecm-law";
  52. reg = <0x0 0x1000>;
  53. fsl,num-laws = <8>;
  54. };
  55. ecm@1000 {
  56. compatible = "fsl,mpc8560-ecm", "fsl,ecm";
  57. reg = <0x1000 0x1000>;
  58. interrupts = <17 2>;
  59. interrupt-parent = <&mpic>;
  60. };
  61. memory-controller@2000 {
  62. compatible = "fsl,mpc8540-memory-controller";
  63. reg = <0x2000 0x1000>;
  64. interrupt-parent = <&mpic>;
  65. interrupts = <18 2>;
  66. };
  67. L2: l2-cache-controller@20000 {
  68. compatible = "fsl,mpc8540-l2-cache-controller";
  69. reg = <0x20000 0x1000>;
  70. cache-line-size = <32>;
  71. cache-size = <0x40000>; // L2, 256K
  72. interrupt-parent = <&mpic>;
  73. interrupts = <16 2>;
  74. };
  75. i2c@3000 {
  76. #address-cells = <1>;
  77. #size-cells = <0>;
  78. cell-index = <0>;
  79. compatible = "fsl-i2c";
  80. reg = <0x3000 0x100>;
  81. interrupts = <43 2>;
  82. interrupt-parent = <&mpic>;
  83. dfsrr;
  84. dtt@48 {
  85. compatible = "national,lm75";
  86. reg = <0x48>;
  87. };
  88. rtc@68 {
  89. compatible = "dallas,ds1337";
  90. reg = <0x68>;
  91. };
  92. };
  93. dma@21300 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  97. reg = <0x21300 0x4>;
  98. ranges = <0x0 0x21100 0x200>;
  99. cell-index = <0>;
  100. dma-channel@0 {
  101. compatible = "fsl,mpc8560-dma-channel",
  102. "fsl,eloplus-dma-channel";
  103. reg = <0x0 0x80>;
  104. cell-index = <0>;
  105. interrupt-parent = <&mpic>;
  106. interrupts = <20 2>;
  107. };
  108. dma-channel@80 {
  109. compatible = "fsl,mpc8560-dma-channel",
  110. "fsl,eloplus-dma-channel";
  111. reg = <0x80 0x80>;
  112. cell-index = <1>;
  113. interrupt-parent = <&mpic>;
  114. interrupts = <21 2>;
  115. };
  116. dma-channel@100 {
  117. compatible = "fsl,mpc8560-dma-channel",
  118. "fsl,eloplus-dma-channel";
  119. reg = <0x100 0x80>;
  120. cell-index = <2>;
  121. interrupt-parent = <&mpic>;
  122. interrupts = <22 2>;
  123. };
  124. dma-channel@180 {
  125. compatible = "fsl,mpc8560-dma-channel",
  126. "fsl,eloplus-dma-channel";
  127. reg = <0x180 0x80>;
  128. cell-index = <3>;
  129. interrupt-parent = <&mpic>;
  130. interrupts = <23 2>;
  131. };
  132. };
  133. enet0: ethernet@24000 {
  134. #address-cells = <1>;
  135. #size-cells = <1>;
  136. cell-index = <0>;
  137. device_type = "network";
  138. model = "TSEC";
  139. compatible = "gianfar";
  140. reg = <0x24000 0x1000>;
  141. ranges = <0x0 0x24000 0x1000>;
  142. local-mac-address = [ 00 00 00 00 00 00 ];
  143. interrupts = <29 2 30 2 34 2>;
  144. interrupt-parent = <&mpic>;
  145. tbi-handle = <&tbi0>;
  146. phy-handle = <&phy2>;
  147. mdio@520 {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. compatible = "fsl,gianfar-mdio";
  151. reg = <0x520 0x20>;
  152. phy1: ethernet-phy@1 {
  153. interrupt-parent = <&mpic>;
  154. interrupts = <8 1>;
  155. reg = <1>;
  156. };
  157. phy2: ethernet-phy@2 {
  158. interrupt-parent = <&mpic>;
  159. interrupts = <8 1>;
  160. reg = <2>;
  161. };
  162. phy3: ethernet-phy@3 {
  163. interrupt-parent = <&mpic>;
  164. interrupts = <8 1>;
  165. reg = <3>;
  166. };
  167. tbi0: tbi-phy@11 {
  168. reg = <0x11>;
  169. device_type = "tbi-phy";
  170. };
  171. };
  172. };
  173. enet1: ethernet@25000 {
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. cell-index = <1>;
  177. device_type = "network";
  178. model = "TSEC";
  179. compatible = "gianfar";
  180. reg = <0x25000 0x1000>;
  181. ranges = <0x0 0x25000 0x1000>;
  182. local-mac-address = [ 00 00 00 00 00 00 ];
  183. interrupts = <35 2 36 2 40 2>;
  184. interrupt-parent = <&mpic>;
  185. tbi-handle = <&tbi1>;
  186. phy-handle = <&phy1>;
  187. mdio@520 {
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. compatible = "fsl,gianfar-tbi";
  191. reg = <0x520 0x20>;
  192. tbi1: tbi-phy@11 {
  193. reg = <0x11>;
  194. device_type = "tbi-phy";
  195. };
  196. };
  197. };
  198. mpic: pic@40000 {
  199. interrupt-controller;
  200. #address-cells = <0>;
  201. #interrupt-cells = <2>;
  202. reg = <0x40000 0x40000>;
  203. device_type = "open-pic";
  204. compatible = "chrp,open-pic";
  205. };
  206. cpm@919c0 {
  207. #address-cells = <1>;
  208. #size-cells = <1>;
  209. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  210. reg = <0x919c0 0x30>;
  211. ranges;
  212. muram@80000 {
  213. #address-cells = <1>;
  214. #size-cells = <1>;
  215. ranges = <0 0x80000 0x10000>;
  216. data@0 {
  217. compatible = "fsl,cpm-muram-data";
  218. reg = <0 0x4000 0x9000 0x2000>;
  219. };
  220. };
  221. brg@919f0 {
  222. compatible = "fsl,mpc8560-brg",
  223. "fsl,cpm2-brg",
  224. "fsl,cpm-brg";
  225. reg = <0x919f0 0x10 0x915f0 0x10>;
  226. clock-frequency = <0>;
  227. };
  228. cpmpic: pic@90c00 {
  229. interrupt-controller;
  230. #address-cells = <0>;
  231. #interrupt-cells = <2>;
  232. interrupts = <46 2>;
  233. interrupt-parent = <&mpic>;
  234. reg = <0x90c00 0x80>;
  235. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  236. };
  237. serial0: serial@91a00 {
  238. device_type = "serial";
  239. compatible = "fsl,mpc8560-scc-uart",
  240. "fsl,cpm2-scc-uart";
  241. reg = <0x91a00 0x20 0x88000 0x100>;
  242. fsl,cpm-brg = <1>;
  243. fsl,cpm-command = <0x800000>;
  244. current-speed = <115200>;
  245. interrupts = <40 8>;
  246. interrupt-parent = <&cpmpic>;
  247. };
  248. serial1: serial@91a20 {
  249. device_type = "serial";
  250. compatible = "fsl,mpc8560-scc-uart",
  251. "fsl,cpm2-scc-uart";
  252. reg = <0x91a20 0x20 0x88100 0x100>;
  253. fsl,cpm-brg = <2>;
  254. fsl,cpm-command = <0x4a00000>;
  255. current-speed = <115200>;
  256. interrupts = <41 8>;
  257. interrupt-parent = <&cpmpic>;
  258. };
  259. enet2: ethernet@91340 {
  260. device_type = "network";
  261. compatible = "fsl,mpc8560-fcc-enet",
  262. "fsl,cpm2-fcc-enet";
  263. reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
  264. local-mac-address = [ 00 00 00 00 00 00 ];
  265. fsl,cpm-command = <0x1a400300>;
  266. interrupts = <34 8>;
  267. interrupt-parent = <&cpmpic>;
  268. phy-handle = <&phy3>;
  269. };
  270. };
  271. };
  272. localbus@e0005000 {
  273. compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
  274. "simple-bus";
  275. #address-cells = <2>;
  276. #size-cells = <1>;
  277. reg = <0xe0005000 0x100>; // BRx, ORx, etc.
  278. interrupt-parent = <&mpic>;
  279. interrupts = <19 2>;
  280. ranges = <
  281. 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
  282. 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
  283. 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
  284. >;
  285. flash@1,0 {
  286. #address-cells = <1>;
  287. #size-cells = <1>;
  288. compatible = "cfi-flash";
  289. reg = <1 0x0 0x8000000>;
  290. bank-width = <4>;
  291. device-width = <1>;
  292. partition@0 {
  293. label = "kernel";
  294. reg = <0x00000000 0x00200000>;
  295. };
  296. partition@200000 {
  297. label = "root";
  298. reg = <0x00200000 0x00300000>;
  299. };
  300. partition@500000 {
  301. label = "user";
  302. reg = <0x00500000 0x07a00000>;
  303. };
  304. partition@7f00000 {
  305. label = "env1";
  306. reg = <0x07f00000 0x00040000>;
  307. };
  308. partition@7f40000 {
  309. label = "env2";
  310. reg = <0x07f40000 0x00040000>;
  311. };
  312. partition@7f80000 {
  313. label = "u-boot";
  314. reg = <0x07f80000 0x00080000>;
  315. read-only;
  316. };
  317. };
  318. /* Note: CAN support needs be enabled in U-Boot */
  319. can0@2,0 {
  320. compatible = "intel,82527"; // Bosch CC770
  321. reg = <2 0x0 0x100>;
  322. interrupts = <4 1>;
  323. interrupt-parent = <&mpic>;
  324. };
  325. can1@2,100 {
  326. compatible = "intel,82527"; // Bosch CC770
  327. reg = <2 0x100 0x100>;
  328. interrupts = <4 1>;
  329. interrupt-parent = <&mpic>;
  330. };
  331. };
  332. pci0: pci@e0008000 {
  333. #interrupt-cells = <1>;
  334. #size-cells = <2>;
  335. #address-cells = <3>;
  336. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  337. device_type = "pci";
  338. reg = <0xe0008000 0x1000>;
  339. clock-frequency = <66666666>;
  340. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  341. interrupt-map = <
  342. /* IDSEL 28 */
  343. 0xe000 0 0 1 &mpic 2 1
  344. 0xe000 0 0 2 &mpic 3 1
  345. 0xe000 0 0 3 &mpic 6 1
  346. 0xe000 0 0 4 &mpic 5 1
  347. /* IDSEL 11 */
  348. 0x5800 0 0 1 &mpic 6 1
  349. 0x5800 0 0 2 &mpic 5 1
  350. >;
  351. interrupt-parent = <&mpic>;
  352. interrupts = <24 2>;
  353. bus-range = <0 0>;
  354. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  355. 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
  356. };
  357. };