tqm8540.dts 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TQM 8540 Device Tree Source
  4. *
  5. * Copyright 2008 Freescale Semiconductor Inc.
  6. */
  7. /dts-v1/;
  8. /include/ "fsl/e500v1_power_isa.dtsi"
  9. / {
  10. model = "tqc,tqm8540";
  11. compatible = "tqc,tqm8540";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. aliases {
  15. ethernet0 = &enet0;
  16. ethernet1 = &enet1;
  17. ethernet2 = &enet2;
  18. serial0 = &serial0;
  19. serial1 = &serial1;
  20. pci0 = &pci0;
  21. };
  22. cpus {
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. PowerPC,8540@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <32>;
  29. i-cache-line-size = <32>;
  30. d-cache-size = <32768>;
  31. i-cache-size = <32768>;
  32. timebase-frequency = <0>;
  33. bus-frequency = <0>;
  34. clock-frequency = <0>;
  35. next-level-cache = <&L2>;
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <0x00000000 0x10000000>;
  41. };
  42. soc@e0000000 {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. device_type = "soc";
  46. ranges = <0x0 0xe0000000 0x100000>;
  47. bus-frequency = <0>;
  48. compatible = "fsl,mpc8540-immr", "simple-bus";
  49. ecm-law@0 {
  50. compatible = "fsl,ecm-law";
  51. reg = <0x0 0x1000>;
  52. fsl,num-laws = <8>;
  53. };
  54. ecm@1000 {
  55. compatible = "fsl,mpc8540-ecm", "fsl,ecm";
  56. reg = <0x1000 0x1000>;
  57. interrupts = <17 2>;
  58. interrupt-parent = <&mpic>;
  59. };
  60. memory-controller@2000 {
  61. compatible = "fsl,mpc8540-memory-controller";
  62. reg = <0x2000 0x1000>;
  63. interrupt-parent = <&mpic>;
  64. interrupts = <18 2>;
  65. };
  66. L2: l2-cache-controller@20000 {
  67. compatible = "fsl,mpc8540-l2-cache-controller";
  68. reg = <0x20000 0x1000>;
  69. cache-line-size = <32>;
  70. cache-size = <0x40000>; // L2, 256K
  71. interrupt-parent = <&mpic>;
  72. interrupts = <16 2>;
  73. };
  74. i2c@3000 {
  75. #address-cells = <1>;
  76. #size-cells = <0>;
  77. cell-index = <0>;
  78. compatible = "fsl-i2c";
  79. reg = <0x3000 0x100>;
  80. interrupts = <43 2>;
  81. interrupt-parent = <&mpic>;
  82. dfsrr;
  83. dtt@48 {
  84. compatible = "national,lm75";
  85. reg = <0x48>;
  86. };
  87. rtc@68 {
  88. compatible = "dallas,ds1337";
  89. reg = <0x68>;
  90. };
  91. };
  92. dma@21300 {
  93. #address-cells = <1>;
  94. #size-cells = <1>;
  95. compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
  96. reg = <0x21300 0x4>;
  97. ranges = <0x0 0x21100 0x200>;
  98. cell-index = <0>;
  99. dma-channel@0 {
  100. compatible = "fsl,mpc8540-dma-channel",
  101. "fsl,eloplus-dma-channel";
  102. reg = <0x0 0x80>;
  103. cell-index = <0>;
  104. interrupt-parent = <&mpic>;
  105. interrupts = <20 2>;
  106. };
  107. dma-channel@80 {
  108. compatible = "fsl,mpc8540-dma-channel",
  109. "fsl,eloplus-dma-channel";
  110. reg = <0x80 0x80>;
  111. cell-index = <1>;
  112. interrupt-parent = <&mpic>;
  113. interrupts = <21 2>;
  114. };
  115. dma-channel@100 {
  116. compatible = "fsl,mpc8540-dma-channel",
  117. "fsl,eloplus-dma-channel";
  118. reg = <0x100 0x80>;
  119. cell-index = <2>;
  120. interrupt-parent = <&mpic>;
  121. interrupts = <22 2>;
  122. };
  123. dma-channel@180 {
  124. compatible = "fsl,mpc8540-dma-channel",
  125. "fsl,eloplus-dma-channel";
  126. reg = <0x180 0x80>;
  127. cell-index = <3>;
  128. interrupt-parent = <&mpic>;
  129. interrupts = <23 2>;
  130. };
  131. };
  132. enet0: ethernet@24000 {
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. cell-index = <0>;
  136. device_type = "network";
  137. model = "TSEC";
  138. compatible = "gianfar";
  139. reg = <0x24000 0x1000>;
  140. ranges = <0x0 0x24000 0x1000>;
  141. local-mac-address = [ 00 00 00 00 00 00 ];
  142. interrupts = <29 2 30 2 34 2>;
  143. interrupt-parent = <&mpic>;
  144. phy-handle = <&phy2>;
  145. mdio@520 {
  146. #address-cells = <1>;
  147. #size-cells = <0>;
  148. compatible = "fsl,gianfar-mdio";
  149. reg = <0x520 0x20>;
  150. phy1: ethernet-phy@1 {
  151. interrupt-parent = <&mpic>;
  152. interrupts = <8 1>;
  153. reg = <1>;
  154. };
  155. phy2: ethernet-phy@2 {
  156. interrupt-parent = <&mpic>;
  157. interrupts = <8 1>;
  158. reg = <2>;
  159. };
  160. phy3: ethernet-phy@3 {
  161. interrupt-parent = <&mpic>;
  162. interrupts = <8 1>;
  163. reg = <3>;
  164. };
  165. tbi0: tbi-phy@11 {
  166. reg = <0x11>;
  167. device_type = "tbi-phy";
  168. };
  169. };
  170. };
  171. enet1: ethernet@25000 {
  172. #address-cells = <1>;
  173. #size-cells = <1>;
  174. cell-index = <1>;
  175. device_type = "network";
  176. model = "TSEC";
  177. compatible = "gianfar";
  178. reg = <0x25000 0x1000>;
  179. ranges = <0x0 0x25000 0x1000>;
  180. local-mac-address = [ 00 00 00 00 00 00 ];
  181. interrupts = <35 2 36 2 40 2>;
  182. interrupt-parent = <&mpic>;
  183. phy-handle = <&phy1>;
  184. mdio@520 {
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. compatible = "fsl,gianfar-tbi";
  188. reg = <0x520 0x20>;
  189. tbi1: tbi-phy@11 {
  190. reg = <0x11>;
  191. device_type = "tbi-phy";
  192. };
  193. };
  194. };
  195. enet2: ethernet@26000 {
  196. #address-cells = <1>;
  197. #size-cells = <1>;
  198. cell-index = <2>;
  199. device_type = "network";
  200. model = "FEC";
  201. compatible = "gianfar";
  202. reg = <0x26000 0x1000>;
  203. ranges = <0x0 0x26000 0x1000>;
  204. local-mac-address = [ 00 00 00 00 00 00 ];
  205. interrupts = <41 2>;
  206. interrupt-parent = <&mpic>;
  207. phy-handle = <&phy3>;
  208. mdio@520 {
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. compatible = "fsl,gianfar-tbi";
  212. reg = <0x520 0x20>;
  213. tbi2: tbi-phy@11 {
  214. reg = <0x11>;
  215. device_type = "tbi-phy";
  216. };
  217. };
  218. };
  219. serial0: serial@4500 {
  220. cell-index = <0>;
  221. device_type = "serial";
  222. compatible = "fsl,ns16550", "ns16550";
  223. reg = <0x4500 0x100>; // reg base, size
  224. clock-frequency = <0>; // should we fill in in uboot?
  225. interrupts = <42 2>;
  226. interrupt-parent = <&mpic>;
  227. };
  228. serial1: serial@4600 {
  229. cell-index = <1>;
  230. device_type = "serial";
  231. compatible = "fsl,ns16550", "ns16550";
  232. reg = <0x4600 0x100>; // reg base, size
  233. clock-frequency = <0>; // should we fill in in uboot?
  234. interrupts = <42 2>;
  235. interrupt-parent = <&mpic>;
  236. };
  237. mpic: pic@40000 {
  238. interrupt-controller;
  239. #address-cells = <0>;
  240. #interrupt-cells = <2>;
  241. reg = <0x40000 0x40000>;
  242. device_type = "open-pic";
  243. compatible = "chrp,open-pic";
  244. };
  245. };
  246. localbus@e0005000 {
  247. #address-cells = <2>;
  248. #size-cells = <1>;
  249. compatible = "fsl,mpc8540-localbus", "fsl,pq3-localbus",
  250. "simple-bus";
  251. reg = <0xe0005000 0x1000>;
  252. interrupt-parent = <&mpic>;
  253. interrupts = <19 2>;
  254. ranges = <0x0 0x0 0xfe000000 0x02000000>;
  255. nor@0,0 {
  256. #address-cells = <1>;
  257. #size-cells = <1>;
  258. compatible = "cfi-flash";
  259. reg = <0x0 0x0 0x02000000>;
  260. bank-width = <4>;
  261. device-width = <2>;
  262. partition@0 {
  263. label = "kernel";
  264. reg = <0x00000000 0x00180000>;
  265. };
  266. partition@180000 {
  267. label = "root";
  268. reg = <0x00180000 0x01dc0000>;
  269. };
  270. partition@1f40000 {
  271. label = "env1";
  272. reg = <0x01f40000 0x00040000>;
  273. };
  274. partition@1f80000 {
  275. label = "env2";
  276. reg = <0x01f80000 0x00040000>;
  277. };
  278. partition@1fc0000 {
  279. label = "u-boot";
  280. reg = <0x01fc0000 0x00040000>;
  281. read-only;
  282. };
  283. };
  284. };
  285. pci0: pci@e0008000 {
  286. #interrupt-cells = <1>;
  287. #size-cells = <2>;
  288. #address-cells = <3>;
  289. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  290. device_type = "pci";
  291. reg = <0xe0008000 0x1000>;
  292. clock-frequency = <66666666>;
  293. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  294. interrupt-map = <
  295. /* IDSEL 28 */
  296. 0xe000 0 0 1 &mpic 2 1
  297. 0xe000 0 0 2 &mpic 3 1
  298. 0xe000 0 0 3 &mpic 6 1
  299. 0xe000 0 0 4 &mpic 5 1
  300. /* IDSEL 11 */
  301. 0x5800 0 0 1 &mpic 6 1
  302. 0x5800 0 0 2 &mpic 5 1
  303. >;
  304. interrupt-parent = <&mpic>;
  305. interrupts = <24 2>;
  306. bus-range = <0 0>;
  307. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  308. 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
  309. };
  310. };