tqm5200.dts 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TQM5200 board Device Tree Source
  4. *
  5. * Copyright (C) 2007 Semihalf
  6. * Marian Balakowicz <[email protected]>
  7. */
  8. /dts-v1/;
  9. / {
  10. model = "tqc,tqm5200";
  11. compatible = "tqc,tqm5200";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. interrupt-parent = <&mpc5200_pic>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. PowerPC,5200@0 {
  19. device_type = "cpu";
  20. reg = <0>;
  21. d-cache-line-size = <32>;
  22. i-cache-line-size = <32>;
  23. d-cache-size = <0x4000>; // L1, 16K
  24. i-cache-size = <0x4000>; // L1, 16K
  25. timebase-frequency = <0>; // from bootloader
  26. bus-frequency = <0>; // from bootloader
  27. clock-frequency = <0>; // from bootloader
  28. };
  29. };
  30. memory@0 {
  31. device_type = "memory";
  32. reg = <0x00000000 0x04000000>; // 64MB
  33. };
  34. soc5200@f0000000 {
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. compatible = "fsl,mpc5200-immr";
  38. ranges = <0 0xf0000000 0x0000c000>;
  39. reg = <0xf0000000 0x00000100>;
  40. bus-frequency = <0>; // from bootloader
  41. system-frequency = <0>; // from bootloader
  42. cdm@200 {
  43. compatible = "fsl,mpc5200-cdm";
  44. reg = <0x200 0x38>;
  45. };
  46. mpc5200_pic: interrupt-controller@500 {
  47. // 5200 interrupts are encoded into two levels;
  48. interrupt-controller;
  49. #interrupt-cells = <3>;
  50. compatible = "fsl,mpc5200-pic";
  51. reg = <0x500 0x80>;
  52. };
  53. timer@600 { // General Purpose Timer
  54. compatible = "fsl,mpc5200-gpt";
  55. reg = <0x600 0x10>;
  56. interrupts = <1 9 0>;
  57. fsl,has-wdt;
  58. };
  59. can@900 {
  60. compatible = "fsl,mpc5200-mscan";
  61. interrupts = <2 17 0>;
  62. reg = <0x900 0x80>;
  63. };
  64. can@980 {
  65. compatible = "fsl,mpc5200-mscan";
  66. interrupts = <2 18 0>;
  67. reg = <0x980 0x80>;
  68. };
  69. gpio_simple: gpio@b00 {
  70. compatible = "fsl,mpc5200-gpio";
  71. reg = <0xb00 0x40>;
  72. interrupts = <1 7 0>;
  73. gpio-controller;
  74. #gpio-cells = <2>;
  75. };
  76. usb@1000 {
  77. compatible = "fsl,mpc5200-ohci","ohci-be";
  78. reg = <0x1000 0xff>;
  79. interrupts = <2 6 0>;
  80. };
  81. dma-controller@1200 {
  82. compatible = "fsl,mpc5200-bestcomm";
  83. reg = <0x1200 0x80>;
  84. interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
  85. 3 4 0 3 5 0 3 6 0 3 7 0
  86. 3 8 0 3 9 0 3 10 0 3 11 0
  87. 3 12 0 3 13 0 3 14 0 3 15 0>;
  88. };
  89. xlb@1f00 {
  90. compatible = "fsl,mpc5200-xlb";
  91. reg = <0x1f00 0x100>;
  92. };
  93. serial@2000 { // PSC1
  94. compatible = "fsl,mpc5200-psc-uart";
  95. reg = <0x2000 0x100>;
  96. interrupts = <2 1 0>;
  97. };
  98. serial@2200 { // PSC2
  99. compatible = "fsl,mpc5200-psc-uart";
  100. reg = <0x2200 0x100>;
  101. interrupts = <2 2 0>;
  102. };
  103. serial@2400 { // PSC3
  104. compatible = "fsl,mpc5200-psc-uart";
  105. reg = <0x2400 0x100>;
  106. interrupts = <2 3 0>;
  107. };
  108. ethernet@3000 {
  109. compatible = "fsl,mpc5200-fec";
  110. reg = <0x3000 0x400>;
  111. local-mac-address = [ 00 00 00 00 00 00 ];
  112. interrupts = <2 5 0>;
  113. phy-handle = <&phy0>;
  114. };
  115. mdio@3000 {
  116. #address-cells = <1>;
  117. #size-cells = <0>;
  118. compatible = "fsl,mpc5200-mdio";
  119. reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
  120. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
  121. phy0: ethernet-phy@0 {
  122. reg = <0>;
  123. };
  124. };
  125. ata@3a00 {
  126. compatible = "fsl,mpc5200-ata";
  127. reg = <0x3a00 0x100>;
  128. interrupts = <2 7 0>;
  129. };
  130. i2c@3d40 {
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. compatible = "fsl,mpc5200-i2c","fsl-i2c";
  134. reg = <0x3d40 0x40>;
  135. interrupts = <2 16 0>;
  136. rtc@68 {
  137. compatible = "dallas,ds1307";
  138. reg = <0x68>;
  139. };
  140. };
  141. sram@8000 {
  142. compatible = "fsl,mpc5200-sram";
  143. reg = <0x8000 0x4000>;
  144. };
  145. };
  146. localbus {
  147. compatible = "fsl,mpc5200-lpb","simple-bus";
  148. #address-cells = <2>;
  149. #size-cells = <1>;
  150. ranges = <0 0 0xfc000000 0x02000000>;
  151. flash@0,0 {
  152. compatible = "cfi-flash";
  153. reg = <0 0 0x02000000>;
  154. bank-width = <4>;
  155. device-width = <2>;
  156. #size-cells = <1>;
  157. #address-cells = <1>;
  158. };
  159. };
  160. pci@f0000d00 {
  161. #interrupt-cells = <1>;
  162. #size-cells = <2>;
  163. #address-cells = <3>;
  164. device_type = "pci";
  165. compatible = "fsl,mpc5200-pci";
  166. reg = <0xf0000d00 0x100>;
  167. interrupt-map-mask = <0xf800 0 0 7>;
  168. interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
  169. 0xc000 0 0 2 &mpc5200_pic 0 0 3
  170. 0xc000 0 0 3 &mpc5200_pic 0 0 3
  171. 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
  172. clock-frequency = <0>; // From boot loader
  173. interrupts = <2 8 0 2 9 0 2 10 0>;
  174. bus-range = <0 0>;
  175. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
  176. <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
  177. <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
  178. };
  179. };