pq2fads.dts 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
  4. *
  5. * Copyright 2007,2008 Freescale Semiconductor Inc.
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "pq2fads";
  10. compatible = "fsl,pq2fads";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. ethernet0 = &enet0;
  15. ethernet1 = &enet1;
  16. serial0 = &serial0;
  17. serial1 = &serial1;
  18. pci0 = &pci0;
  19. };
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. cpu@0 {
  24. device_type = "cpu";
  25. reg = <0x0>;
  26. d-cache-line-size = <32>;
  27. i-cache-line-size = <32>;
  28. d-cache-size = <16384>;
  29. i-cache-size = <16384>;
  30. timebase-frequency = <0>;
  31. clock-frequency = <0>;
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <0x0 0x0>;
  37. };
  38. localbus@f0010100 {
  39. compatible = "fsl,mpc8280-localbus",
  40. "fsl,pq2-localbus";
  41. #address-cells = <2>;
  42. #size-cells = <1>;
  43. reg = <0xf0010100 0x60>;
  44. ranges = <0x0 0x0 0xff800000 0x800000
  45. 0x1 0x0 0xf4500000 0x8000
  46. 0x8 0x0 0xf8200000 0x8000>;
  47. flash@0,0 {
  48. compatible = "jedec-flash";
  49. reg = <0x0 0x0 0x800000>;
  50. bank-width = <4>;
  51. device-width = <1>;
  52. };
  53. bcsr@1,0 {
  54. reg = <0x1 0x0 0x20>;
  55. compatible = "fsl,pq2fads-bcsr";
  56. };
  57. PCI_PIC: pic@8,0 {
  58. #interrupt-cells = <1>;
  59. interrupt-controller;
  60. reg = <0x8 0x0 0x8>;
  61. compatible = "fsl,pq2ads-pci-pic";
  62. interrupt-parent = <&PIC>;
  63. interrupts = <24 8>;
  64. };
  65. };
  66. pci0: pci@f0010800 {
  67. device_type = "pci";
  68. reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
  69. compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
  70. #interrupt-cells = <1>;
  71. #size-cells = <2>;
  72. #address-cells = <3>;
  73. clock-frequency = <66000000>;
  74. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  75. interrupt-map = <
  76. /* IDSEL 0x16 */
  77. 0xb000 0x0 0x0 0x1 &PCI_PIC 0
  78. 0xb000 0x0 0x0 0x2 &PCI_PIC 1
  79. 0xb000 0x0 0x0 0x3 &PCI_PIC 2
  80. 0xb000 0x0 0x0 0x4 &PCI_PIC 3
  81. /* IDSEL 0x17 */
  82. 0xb800 0x0 0x0 0x1 &PCI_PIC 4
  83. 0xb800 0x0 0x0 0x2 &PCI_PIC 5
  84. 0xb800 0x0 0x0 0x3 &PCI_PIC 6
  85. 0xb800 0x0 0x0 0x4 &PCI_PIC 7
  86. /* IDSEL 0x18 */
  87. 0xc000 0x0 0x0 0x1 &PCI_PIC 8
  88. 0xc000 0x0 0x0 0x2 &PCI_PIC 9
  89. 0xc000 0x0 0x0 0x3 &PCI_PIC 10
  90. 0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
  91. interrupt-parent = <&PIC>;
  92. interrupts = <18 8>;
  93. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  94. 0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
  95. 0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
  96. };
  97. soc@f0000000 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. device_type = "soc";
  101. compatible = "fsl,mpc8280", "fsl,pq2-soc";
  102. ranges = <0x0 0xf0000000 0x53000>;
  103. // Temporary -- will go away once kernel uses ranges for get_immrbase().
  104. reg = <0xf0000000 0x53000>;
  105. cpm@119c0 {
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. #interrupt-cells = <2>;
  109. compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
  110. reg = <0x119c0 0x30>;
  111. ranges;
  112. muram@0 {
  113. #address-cells = <1>;
  114. #size-cells = <1>;
  115. ranges = <0x0 0x0 0x10000>;
  116. data@0 {
  117. compatible = "fsl,cpm-muram-data";
  118. reg = <0x0 0x2000 0x9800 0x800>;
  119. };
  120. };
  121. brg@119f0 {
  122. compatible = "fsl,mpc8280-brg",
  123. "fsl,cpm2-brg",
  124. "fsl,cpm-brg";
  125. reg = <0x119f0 0x10 0x115f0 0x10>;
  126. };
  127. serial0: serial@11a00 {
  128. device_type = "serial";
  129. compatible = "fsl,mpc8280-scc-uart",
  130. "fsl,cpm2-scc-uart";
  131. reg = <0x11a00 0x20 0x8000 0x100>;
  132. interrupts = <40 8>;
  133. interrupt-parent = <&PIC>;
  134. fsl,cpm-brg = <1>;
  135. fsl,cpm-command = <0x800000>;
  136. };
  137. serial1: serial@11a20 {
  138. device_type = "serial";
  139. compatible = "fsl,mpc8280-scc-uart",
  140. "fsl,cpm2-scc-uart";
  141. reg = <0x11a20 0x20 0x8100 0x100>;
  142. interrupts = <41 8>;
  143. interrupt-parent = <&PIC>;
  144. fsl,cpm-brg = <2>;
  145. fsl,cpm-command = <0x4a00000>;
  146. };
  147. enet0: ethernet@11320 {
  148. device_type = "network";
  149. compatible = "fsl,mpc8280-fcc-enet",
  150. "fsl,cpm2-fcc-enet";
  151. reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
  152. interrupts = <33 8>;
  153. interrupt-parent = <&PIC>;
  154. phy-handle = <&PHY0>;
  155. linux,network-index = <0>;
  156. fsl,cpm-command = <0x16200300>;
  157. };
  158. enet1: ethernet@11340 {
  159. device_type = "network";
  160. compatible = "fsl,mpc8280-fcc-enet",
  161. "fsl,cpm2-fcc-enet";
  162. reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
  163. interrupts = <34 8>;
  164. interrupt-parent = <&PIC>;
  165. phy-handle = <&PHY1>;
  166. linux,network-index = <1>;
  167. fsl,cpm-command = <0x1a400300>;
  168. local-mac-address = [00 e0 0c 00 79 01];
  169. };
  170. mdio@10d40 {
  171. compatible = "fsl,pq2fads-mdio-bitbang",
  172. "fsl,mpc8280-mdio-bitbang",
  173. "fsl,cpm2-mdio-bitbang";
  174. #address-cells = <1>;
  175. #size-cells = <0>;
  176. reg = <0x10d40 0x14>;
  177. fsl,mdio-pin = <9>;
  178. fsl,mdc-pin = <10>;
  179. PHY0: ethernet-phy@0 {
  180. interrupt-parent = <&PIC>;
  181. interrupts = <25 2>;
  182. reg = <0x0>;
  183. };
  184. PHY1: ethernet-phy@1 {
  185. interrupt-parent = <&PIC>;
  186. interrupts = <25 2>;
  187. reg = <0x3>;
  188. };
  189. };
  190. usb@11b60 {
  191. #address-cells = <1>;
  192. #size-cells = <0>;
  193. compatible = "fsl,mpc8280-usb",
  194. "fsl,cpm2-usb";
  195. reg = <0x11b60 0x18 0x8b00 0x100>;
  196. interrupt-parent = <&PIC>;
  197. interrupts = <11 8>;
  198. fsl,cpm-command = <0x2e600000>;
  199. };
  200. };
  201. PIC: interrupt-controller@10c00 {
  202. #interrupt-cells = <2>;
  203. interrupt-controller;
  204. reg = <0x10c00 0x80>;
  205. compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
  206. };
  207. };
  208. chosen {
  209. stdout-path = "/soc/cpm/serial@11a00";
  210. };
  211. };