mgcoge.dts 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Device Tree for the MGCOGE plattform from keymile
  4. *
  5. * Copyright 2008 DENX Software Engineering GmbH
  6. * Heiko Schocher <[email protected]>
  7. */
  8. /dts-v1/;
  9. / {
  10. model = "MGCOGE";
  11. compatible = "keymile,km82xx";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. aliases {
  15. ethernet0 = &eth0;
  16. serial0 = &smc2;
  17. };
  18. cpus {
  19. #address-cells = <1>;
  20. #size-cells = <0>;
  21. PowerPC,8247@0 {
  22. device_type = "cpu";
  23. reg = <0>;
  24. d-cache-line-size = <32>;
  25. i-cache-line-size = <32>;
  26. d-cache-size = <16384>;
  27. i-cache-size = <16384>;
  28. timebase-frequency = <0>; /* Filled in by U-Boot */
  29. clock-frequency = <0>; /* Filled in by U-Boot */
  30. bus-frequency = <0>; /* Filled in by U-Boot */
  31. };
  32. };
  33. localbus@f0010100 {
  34. compatible = "fsl,mpc8247-localbus",
  35. "fsl,pq2-localbus",
  36. "simple-bus";
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. reg = <0xf0010100 0x40>;
  40. ranges = <0 0 0xfe000000 0x00400000
  41. 1 0 0x30000000 0x00010000
  42. 2 0 0x40000000 0x00010000
  43. 5 0 0x50000000 0x04000000
  44. >;
  45. flash@0,0 {
  46. compatible = "cfi-flash";
  47. reg = <0 0x0 0x400000>;
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. bank-width = <1>;
  51. device-width = <1>;
  52. partition@0 {
  53. label = "u-boot";
  54. reg = <0x00000 0xC0000>;
  55. };
  56. partition@1 {
  57. label = "env";
  58. reg = <0xC0000 0x20000>;
  59. };
  60. partition@2 {
  61. label = "envred";
  62. reg = <0xE0000 0x20000>;
  63. };
  64. partition@3 {
  65. label = "free";
  66. reg = <0x100000 0x300000>;
  67. };
  68. };
  69. flash@5,0 {
  70. compatible = "cfi-flash";
  71. reg = <5 0x00000000 0x02000000
  72. 5 0x02000000 0x02000000>;
  73. #address-cells = <1>;
  74. #size-cells = <1>;
  75. bank-width = <2>;
  76. partition@app { /* 64 MBytes */
  77. label = "ubi0";
  78. reg = <0x00000000 0x04000000>;
  79. };
  80. };
  81. };
  82. memory {
  83. device_type = "memory";
  84. reg = <0 0>; /* Filled in by U-Boot */
  85. };
  86. soc@f0000000 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "fsl,mpc8247-immr", "fsl,pq2-soc", "simple-bus";
  90. ranges = <0x00000000 0xf0000000 0x00053000>;
  91. // Temporary until code stops depending on it.
  92. device_type = "soc";
  93. cpm@119c0 {
  94. #address-cells = <1>;
  95. #size-cells = <1>;
  96. #interrupt-cells = <2>;
  97. compatible = "fsl,mpc8247-cpm", "fsl,cpm2",
  98. "simple-bus";
  99. reg = <0x119c0 0x30>;
  100. ranges;
  101. muram {
  102. compatible = "fsl,cpm-muram";
  103. #address-cells = <1>;
  104. #size-cells = <1>;
  105. ranges = <0 0 0x10000>;
  106. data@0 {
  107. compatible = "fsl,cpm-muram-data";
  108. reg = <0x80 0x1f80 0x9800 0x800>;
  109. };
  110. };
  111. brg@119f0 {
  112. compatible = "fsl,mpc8247-brg",
  113. "fsl,cpm2-brg",
  114. "fsl,cpm-brg";
  115. reg = <0x119f0 0x10 0x115f0 0x10>;
  116. };
  117. /* Monitor port/SMC2 */
  118. smc2: serial@11a90 {
  119. device_type = "serial";
  120. compatible = "fsl,mpc8247-smc-uart",
  121. "fsl,cpm2-smc-uart";
  122. reg = <0x11a90 0x20 0x88fc 0x02>;
  123. interrupts = <5 8>;
  124. interrupt-parent = <&PIC>;
  125. fsl,cpm-brg = <2>;
  126. fsl,cpm-command = <0x21200000>;
  127. current-speed = <0>; /* Filled in by U-Boot */
  128. };
  129. eth0: ethernet@11a60 {
  130. device_type = "network";
  131. compatible = "fsl,mpc8247-scc-enet",
  132. "fsl,cpm2-scc-enet";
  133. reg = <0x11a60 0x20 0x8300 0x100 0x11390 1>;
  134. local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */
  135. interrupts = <43 8>;
  136. interrupt-parent = <&PIC>;
  137. linux,network-index = <0>;
  138. fsl,cpm-command = <0xce00000>;
  139. fixed-link = <0 0 10 0 0>;
  140. };
  141. i2c@11860 {
  142. compatible = "fsl,mpc8272-i2c",
  143. "fsl,cpm2-i2c";
  144. reg = <0x11860 0x20 0x8afc 0x2>;
  145. interrupts = <1 8>;
  146. interrupt-parent = <&PIC>;
  147. fsl,cpm-command = <0x29600000>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. };
  151. mdio@10d40 {
  152. compatible = "fsl,cpm2-mdio-bitbang";
  153. reg = <0x10d00 0x14>;
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. fsl,mdio-pin = <12>;
  157. fsl,mdc-pin = <13>;
  158. phy0: ethernet-phy@0 {
  159. reg = <0x0>;
  160. };
  161. phy1: ethernet-phy@1 {
  162. reg = <0x1>;
  163. };
  164. };
  165. /* FCC1 management to switch */
  166. ethernet@11300 {
  167. device_type = "network";
  168. compatible = "fsl,cpm2-fcc-enet";
  169. reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
  170. local-mac-address = [ 00 01 02 03 04 07 ];
  171. interrupts = <32 8>;
  172. interrupt-parent = <&PIC>;
  173. phy-handle = <&phy0>;
  174. linux,network-index = <1>;
  175. fsl,cpm-command = <0x12000300>;
  176. };
  177. /* FCC2 to redundant core unit over backplane */
  178. ethernet@11320 {
  179. device_type = "network";
  180. compatible = "fsl,cpm2-fcc-enet";
  181. reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
  182. local-mac-address = [ 00 01 02 03 04 08 ];
  183. interrupts = <33 8>;
  184. interrupt-parent = <&PIC>;
  185. phy-handle = <&phy1>;
  186. linux,network-index = <2>;
  187. fsl,cpm-command = <0x16200300>;
  188. };
  189. usb@11b60 {
  190. compatible = "fsl,mpc8272-cpm-usb";
  191. mode = "peripheral";
  192. reg = <0x11b60 0x40 0x8b00 0x100>;
  193. interrupts = <11 8>;
  194. interrupt-parent = <&PIC>;
  195. usb-clock = <5>;
  196. };
  197. spi@11aa0 {
  198. cell-index = <0>;
  199. compatible = "fsl,spi", "fsl,cpm2-spi";
  200. reg = <0x11a80 0x40 0x89fc 0x2>;
  201. interrupts = <2 8>;
  202. interrupt-parent = <&PIC>;
  203. cs-gpios = < &cpm2_pio_d 19 0>;
  204. };
  205. };
  206. cpm2_pio_d: gpio-controller@10d60 {
  207. #gpio-cells = <2>;
  208. compatible = "fsl,cpm2-pario-bank";
  209. reg = <0x10d60 0x14>;
  210. gpio-controller;
  211. };
  212. cpm2_pio_c: gpio-controller@10d40 {
  213. #gpio-cells = <2>;
  214. compatible = "fsl,cpm2-pario-bank";
  215. reg = <0x10d40 0x14>;
  216. gpio-controller;
  217. };
  218. PIC: interrupt-controller@10c00 {
  219. #interrupt-cells = <2>;
  220. interrupt-controller;
  221. reg = <0x10c00 0x80>;
  222. compatible = "fsl,mpc8247-pic", "fsl,pq2-pic";
  223. };
  224. };
  225. };