asp834x-redboot.dts 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Analogue & Micro ASP8347 Device Tree Source
  4. *
  5. * Copyright 2008 Codehermit
  6. */
  7. /dts-v1/;
  8. / {
  9. model = "Analogue & Micro ASP8347E";
  10. compatible = "analogue-and-micro,asp8347e";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. ethernet0 = &enet0;
  15. ethernet1 = &enet1;
  16. serial0 = &serial0;
  17. serial1 = &serial1;
  18. };
  19. cpus {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. PowerPC,8347@0 {
  23. device_type = "cpu";
  24. reg = <0x0>;
  25. d-cache-line-size = <32>;
  26. i-cache-line-size = <32>;
  27. d-cache-size = <32768>;
  28. i-cache-size = <32768>;
  29. timebase-frequency = <0>; // from bootloader
  30. bus-frequency = <0>; // from bootloader
  31. clock-frequency = <0>; // from bootloader
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <0x00000000 0x8000000>; // 128MB at 0
  37. };
  38. localbus@ff005000 {
  39. #address-cells = <2>;
  40. #size-cells = <1>;
  41. compatible = "fsl,mpc8347e-localbus",
  42. "fsl,pq2pro-localbus",
  43. "simple-bus";
  44. reg = <0xff005000 0x1000>;
  45. interrupts = <77 0x8>;
  46. interrupt-parent = <&ipic>;
  47. ranges = <
  48. 0 0 0xf0000000 0x02000000
  49. >;
  50. flash@0,0 {
  51. compatible = "cfi-flash";
  52. reg = <0 0 0x02000000>;
  53. bank-width = <2>;
  54. device-width = <2>;
  55. };
  56. };
  57. soc8349@ff000000 {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. device_type = "soc";
  61. ranges = <0x0 0xff000000 0x00100000>;
  62. reg = <0xff000000 0x00000200>;
  63. bus-frequency = <0>;
  64. wdt@200 {
  65. device_type = "watchdog";
  66. compatible = "mpc83xx_wdt";
  67. reg = <0x200 0x100>;
  68. };
  69. i2c@3000 {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. cell-index = <0>;
  73. compatible = "fsl-i2c";
  74. reg = <0x3000 0x100>;
  75. interrupts = <14 0x8>;
  76. interrupt-parent = <&ipic>;
  77. dfsrr;
  78. rtc@68 {
  79. compatible = "dallas,ds1374";
  80. reg = <0x68>;
  81. };
  82. };
  83. i2c@3100 {
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. cell-index = <1>;
  87. compatible = "fsl-i2c";
  88. reg = <0x3100 0x100>;
  89. interrupts = <15 0x8>;
  90. interrupt-parent = <&ipic>;
  91. dfsrr;
  92. };
  93. spi@7000 {
  94. cell-index = <0>;
  95. compatible = "fsl,spi";
  96. reg = <0x7000 0x1000>;
  97. interrupts = <16 0x8>;
  98. interrupt-parent = <&ipic>;
  99. mode = "cpu";
  100. };
  101. dma@82a8 {
  102. #address-cells = <1>;
  103. #size-cells = <1>;
  104. compatible = "fsl,mpc8347-dma", "fsl,elo-dma";
  105. reg = <0x82a8 4>;
  106. ranges = <0 0x8100 0x1a8>;
  107. interrupt-parent = <&ipic>;
  108. interrupts = <71 8>;
  109. cell-index = <0>;
  110. dma-channel@0 {
  111. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  112. reg = <0 0x80>;
  113. cell-index = <0>;
  114. interrupt-parent = <&ipic>;
  115. interrupts = <71 8>;
  116. };
  117. dma-channel@80 {
  118. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  119. reg = <0x80 0x80>;
  120. cell-index = <1>;
  121. interrupt-parent = <&ipic>;
  122. interrupts = <71 8>;
  123. };
  124. dma-channel@100 {
  125. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  126. reg = <0x100 0x80>;
  127. cell-index = <2>;
  128. interrupt-parent = <&ipic>;
  129. interrupts = <71 8>;
  130. };
  131. dma-channel@180 {
  132. compatible = "fsl,mpc8347-dma-channel", "fsl,elo-dma-channel";
  133. reg = <0x180 0x28>;
  134. cell-index = <3>;
  135. interrupt-parent = <&ipic>;
  136. interrupts = <71 8>;
  137. };
  138. };
  139. /* phy type (ULPI or SERIAL) are only types supported for MPH */
  140. /* port = 0 or 1 */
  141. usb@22000 {
  142. compatible = "fsl-usb2-mph";
  143. reg = <0x22000 0x1000>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. interrupt-parent = <&ipic>;
  147. interrupts = <39 0x8>;
  148. phy_type = "ulpi";
  149. port0;
  150. };
  151. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  152. usb@23000 {
  153. compatible = "fsl-usb2-dr";
  154. reg = <0x23000 0x1000>;
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. interrupt-parent = <&ipic>;
  158. interrupts = <38 0x8>;
  159. dr_mode = "otg";
  160. phy_type = "ulpi";
  161. };
  162. enet0: ethernet@24000 {
  163. #address-cells = <1>;
  164. #size-cells = <1>;
  165. cell-index = <0>;
  166. device_type = "network";
  167. model = "TSEC";
  168. compatible = "gianfar";
  169. reg = <0x24000 0x1000>;
  170. ranges = <0x0 0x24000 0x1000>;
  171. local-mac-address = [ 00 08 e5 11 32 33 ];
  172. interrupts = <32 0x8 33 0x8 34 0x8>;
  173. interrupt-parent = <&ipic>;
  174. tbi-handle = <&tbi0>;
  175. phy-handle = <&phy0>;
  176. linux,network-index = <0>;
  177. mdio@520 {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. compatible = "fsl,gianfar-mdio";
  181. reg = <0x520 0x20>;
  182. phy0: ethernet-phy@0 {
  183. interrupt-parent = <&ipic>;
  184. interrupts = <17 0x8>;
  185. reg = <0x1>;
  186. };
  187. phy1: ethernet-phy@1 {
  188. interrupt-parent = <&ipic>;
  189. interrupts = <18 0x8>;
  190. reg = <0x2>;
  191. };
  192. tbi0: tbi-phy@11 {
  193. reg = <0x11>;
  194. device_type = "tbi-phy";
  195. };
  196. };
  197. };
  198. enet1: ethernet@25000 {
  199. #address-cells = <1>;
  200. #size-cells = <1>;
  201. cell-index = <1>;
  202. device_type = "network";
  203. model = "TSEC";
  204. compatible = "gianfar";
  205. reg = <0x25000 0x1000>;
  206. ranges = <0x0 0x25000 0x1000>;
  207. local-mac-address = [ 00 08 e5 11 32 34 ];
  208. interrupts = <35 0x8 36 0x8 37 0x8>;
  209. interrupt-parent = <&ipic>;
  210. tbi-handle = <&tbi1>;
  211. phy-handle = <&phy1>;
  212. linux,network-index = <1>;
  213. mdio@520 {
  214. #address-cells = <1>;
  215. #size-cells = <0>;
  216. compatible = "fsl,gianfar-tbi";
  217. reg = <0x520 0x20>;
  218. tbi1: tbi-phy@11 {
  219. reg = <0x11>;
  220. device_type = "tbi-phy";
  221. };
  222. };
  223. };
  224. serial0: serial@4500 {
  225. cell-index = <0>;
  226. device_type = "serial";
  227. compatible = "fsl,ns16550", "ns16550";
  228. reg = <0x4500 0x100>;
  229. clock-frequency = <400000000>;
  230. interrupts = <9 0x8>;
  231. interrupt-parent = <&ipic>;
  232. };
  233. serial1: serial@4600 {
  234. cell-index = <1>;
  235. device_type = "serial";
  236. compatible = "fsl,ns16550", "ns16550";
  237. reg = <0x4600 0x100>;
  238. clock-frequency = <400000000>;
  239. interrupts = <10 0x8>;
  240. interrupt-parent = <&ipic>;
  241. };
  242. /* May need to remove if on a part without crypto engine */
  243. crypto@30000 {
  244. device_type = "crypto";
  245. model = "SEC2";
  246. compatible = "talitos";
  247. reg = <0x30000 0x10000>;
  248. interrupts = <11 0x8>;
  249. interrupt-parent = <&ipic>;
  250. num-channels = <4>;
  251. channel-fifo-len = <24>;
  252. exec-units-mask = <0x0000007e>;
  253. /* desc mask is for rev2.0,
  254. * we need runtime fixup for >2.0 */
  255. descriptor-types-mask = <0x01010ebf>;
  256. };
  257. /* IPIC
  258. * interrupts cell = <intr #, sense>
  259. * sense values match linux IORESOURCE_IRQ_* defines:
  260. * sense == 8: Level, low assertion
  261. * sense == 2: Edge, high-to-low change
  262. */
  263. ipic: pic@700 {
  264. interrupt-controller;
  265. #address-cells = <0>;
  266. #interrupt-cells = <2>;
  267. reg = <0x700 0x100>;
  268. device_type = "ipic";
  269. };
  270. };
  271. chosen {
  272. bootargs = "console=ttyS0,38400 root=/dev/mtdblock3 rootfstype=jffs2";
  273. stdout-path = &serial0;
  274. };
  275. };