arches.dts 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Device Tree Source for AMCC Arches (dual 460GT board)
  4. *
  5. * (C) Copyright 2008 Applied Micro Circuits Corporation
  6. * Victor Gallardo <[email protected]>
  7. * Adam Graham <[email protected]>
  8. *
  9. * Based on the glacier.dts file
  10. * Stefan Roese <[email protected]>
  11. * Copyright 2008 DENX Software Engineering
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. */
  16. /dts-v1/;
  17. / {
  18. #address-cells = <2>;
  19. #size-cells = <1>;
  20. model = "amcc,arches";
  21. compatible = "amcc,arches";
  22. dcr-parent = <&{/cpus/cpu@0}>;
  23. aliases {
  24. ethernet0 = &EMAC0;
  25. ethernet1 = &EMAC1;
  26. ethernet2 = &EMAC2;
  27. serial0 = &UART0;
  28. };
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. cpu@0 {
  33. device_type = "cpu";
  34. model = "PowerPC,460GT";
  35. reg = <0x00000000>;
  36. clock-frequency = <0>; /* Filled in by U-Boot */
  37. timebase-frequency = <0>; /* Filled in by U-Boot */
  38. i-cache-line-size = <32>;
  39. d-cache-line-size = <32>;
  40. i-cache-size = <32768>;
  41. d-cache-size = <32768>;
  42. dcr-controller;
  43. dcr-access-method = "native";
  44. next-level-cache = <&L2C0>;
  45. };
  46. };
  47. memory {
  48. device_type = "memory";
  49. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  50. };
  51. UIC0: interrupt-controller0 {
  52. compatible = "ibm,uic-460gt","ibm,uic";
  53. interrupt-controller;
  54. cell-index = <0>;
  55. dcr-reg = <0x0c0 0x009>;
  56. #address-cells = <0>;
  57. #size-cells = <0>;
  58. #interrupt-cells = <2>;
  59. };
  60. UIC1: interrupt-controller1 {
  61. compatible = "ibm,uic-460gt","ibm,uic";
  62. interrupt-controller;
  63. cell-index = <1>;
  64. dcr-reg = <0x0d0 0x009>;
  65. #address-cells = <0>;
  66. #size-cells = <0>;
  67. #interrupt-cells = <2>;
  68. interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
  69. interrupt-parent = <&UIC0>;
  70. };
  71. UIC2: interrupt-controller2 {
  72. compatible = "ibm,uic-460gt","ibm,uic";
  73. interrupt-controller;
  74. cell-index = <2>;
  75. dcr-reg = <0x0e0 0x009>;
  76. #address-cells = <0>;
  77. #size-cells = <0>;
  78. #interrupt-cells = <2>;
  79. interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
  80. interrupt-parent = <&UIC0>;
  81. };
  82. UIC3: interrupt-controller3 {
  83. compatible = "ibm,uic-460gt","ibm,uic";
  84. interrupt-controller;
  85. cell-index = <3>;
  86. dcr-reg = <0x0f0 0x009>;
  87. #address-cells = <0>;
  88. #size-cells = <0>;
  89. #interrupt-cells = <2>;
  90. interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
  91. interrupt-parent = <&UIC0>;
  92. };
  93. SDR0: sdr {
  94. compatible = "ibm,sdr-460gt";
  95. dcr-reg = <0x00e 0x002>;
  96. };
  97. CPR0: cpr {
  98. compatible = "ibm,cpr-460gt";
  99. dcr-reg = <0x00c 0x002>;
  100. };
  101. L2C0: l2c {
  102. compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
  103. dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
  104. 0x030 0x008>; /* L2 cache DCR's */
  105. cache-line-size = <32>; /* 32 bytes */
  106. cache-size = <262144>; /* L2, 256K */
  107. interrupt-parent = <&UIC1>;
  108. interrupts = <11 1>;
  109. };
  110. plb {
  111. compatible = "ibm,plb-460gt", "ibm,plb4";
  112. #address-cells = <2>;
  113. #size-cells = <1>;
  114. ranges;
  115. clock-frequency = <0>; /* Filled in by U-Boot */
  116. SDRAM0: sdram {
  117. compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
  118. dcr-reg = <0x010 0x002>;
  119. };
  120. CRYPTO: crypto@180000 {
  121. compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
  122. reg = <4 0x00180000 0x80400>;
  123. interrupt-parent = <&UIC0>;
  124. interrupts = <0x1d 0x4>;
  125. };
  126. MAL0: mcmal {
  127. compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
  128. dcr-reg = <0x180 0x062>;
  129. num-tx-chans = <3>;
  130. num-rx-chans = <24>;
  131. #address-cells = <0>;
  132. #size-cells = <0>;
  133. interrupt-parent = <&UIC2>;
  134. interrupts = < /*TXEOB*/ 0x6 0x4
  135. /*RXEOB*/ 0x7 0x4
  136. /*SERR*/ 0x3 0x4
  137. /*TXDE*/ 0x4 0x4
  138. /*RXDE*/ 0x5 0x4>;
  139. desc-base-addr-high = <0x8>;
  140. };
  141. POB0: opb {
  142. compatible = "ibm,opb-460gt", "ibm,opb";
  143. #address-cells = <1>;
  144. #size-cells = <1>;
  145. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  146. clock-frequency = <0>; /* Filled in by U-Boot */
  147. EBC0: ebc {
  148. compatible = "ibm,ebc-460gt", "ibm,ebc";
  149. dcr-reg = <0x012 0x002>;
  150. #address-cells = <2>;
  151. #size-cells = <1>;
  152. clock-frequency = <0>; /* Filled in by U-Boot */
  153. /* ranges property is supplied by U-Boot */
  154. interrupts = <0x6 0x4>;
  155. interrupt-parent = <&UIC1>;
  156. nor_flash@0,0 {
  157. compatible = "amd,s29gl256n", "cfi-flash";
  158. bank-width = <2>;
  159. reg = <0x00000000 0x00000000 0x02000000>;
  160. #address-cells = <1>;
  161. #size-cells = <1>;
  162. partition@0 {
  163. label = "kernel";
  164. reg = <0x00000000 0x001e0000>;
  165. };
  166. partition@1e0000 {
  167. label = "dtb";
  168. reg = <0x001e0000 0x00020000>;
  169. };
  170. partition@200000 {
  171. label = "root";
  172. reg = <0x00200000 0x00200000>;
  173. };
  174. partition@400000 {
  175. label = "user";
  176. reg = <0x00400000 0x01b60000>;
  177. };
  178. partition@1f60000 {
  179. label = "env";
  180. reg = <0x01f60000 0x00040000>;
  181. };
  182. partition@1fa0000 {
  183. label = "u-boot";
  184. reg = <0x01fa0000 0x00060000>;
  185. };
  186. };
  187. };
  188. UART0: serial@ef600300 {
  189. device_type = "serial";
  190. compatible = "ns16550";
  191. reg = <0xef600300 0x00000008>;
  192. virtual-reg = <0xef600300>;
  193. clock-frequency = <0>; /* Filled in by U-Boot */
  194. current-speed = <0>; /* Filled in by U-Boot */
  195. interrupt-parent = <&UIC1>;
  196. interrupts = <0x1 0x4>;
  197. };
  198. IIC0: i2c@ef600700 {
  199. compatible = "ibm,iic-460gt", "ibm,iic";
  200. reg = <0xef600700 0x00000014>;
  201. interrupt-parent = <&UIC0>;
  202. interrupts = <0x2 0x4>;
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. sttm@4a {
  206. compatible = "ad,ad7414";
  207. reg = <0x4a>;
  208. interrupt-parent = <&UIC1>;
  209. interrupts = <0x0 0x8>;
  210. };
  211. };
  212. IIC1: i2c@ef600800 {
  213. compatible = "ibm,iic-460gt", "ibm,iic";
  214. reg = <0xef600800 0x00000014>;
  215. interrupt-parent = <&UIC0>;
  216. interrupts = <0x3 0x4>;
  217. };
  218. TAH0: emac-tah@ef601350 {
  219. compatible = "ibm,tah-460gt", "ibm,tah";
  220. reg = <0xef601350 0x00000030>;
  221. };
  222. TAH1: emac-tah@ef601450 {
  223. compatible = "ibm,tah-460gt", "ibm,tah";
  224. reg = <0xef601450 0x00000030>;
  225. };
  226. EMAC0: ethernet@ef600e00 {
  227. device_type = "network";
  228. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  229. interrupt-parent = <&EMAC0>;
  230. interrupts = <0x0 0x1>;
  231. #interrupt-cells = <1>;
  232. #address-cells = <0>;
  233. #size-cells = <0>;
  234. interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
  235. /*Wake*/ 0x1 &UIC2 0x14 0x4>;
  236. reg = <0xef600e00 0x000000c4>;
  237. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  238. mal-device = <&MAL0>;
  239. mal-tx-channel = <0>;
  240. mal-rx-channel = <0>;
  241. cell-index = <0>;
  242. max-frame-size = <9000>;
  243. rx-fifo-size = <4096>;
  244. tx-fifo-size = <2048>;
  245. rx-fifo-size-gige = <16384>;
  246. phy-mode = "sgmii";
  247. phy-map = <0xffffffff>;
  248. gpcs-address = <0x0000000a>;
  249. tah-device = <&TAH0>;
  250. tah-channel = <0>;
  251. has-inverted-stacr-oc;
  252. has-new-stacr-staopc;
  253. };
  254. EMAC1: ethernet@ef600f00 {
  255. device_type = "network";
  256. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  257. interrupt-parent = <&EMAC1>;
  258. interrupts = <0x0 0x1>;
  259. #interrupt-cells = <1>;
  260. #address-cells = <0>;
  261. #size-cells = <0>;
  262. interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
  263. /*Wake*/ 0x1 &UIC2 0x15 0x4>;
  264. reg = <0xef600f00 0x000000c4>;
  265. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  266. mal-device = <&MAL0>;
  267. mal-tx-channel = <1>;
  268. mal-rx-channel = <8>;
  269. cell-index = <1>;
  270. max-frame-size = <9000>;
  271. rx-fifo-size = <4096>;
  272. tx-fifo-size = <2048>;
  273. rx-fifo-size-gige = <16384>;
  274. phy-mode = "sgmii";
  275. phy-map = <0x00000000>;
  276. gpcs-address = <0x0000000b>;
  277. tah-device = <&TAH1>;
  278. tah-channel = <1>;
  279. has-inverted-stacr-oc;
  280. has-new-stacr-staopc;
  281. mdio-device = <&EMAC0>;
  282. };
  283. EMAC2: ethernet@ef601100 {
  284. device_type = "network";
  285. compatible = "ibm,emac-460gt", "ibm,emac4sync";
  286. interrupt-parent = <&EMAC2>;
  287. interrupts = <0x0 0x1>;
  288. #interrupt-cells = <1>;
  289. #address-cells = <0>;
  290. #size-cells = <0>;
  291. interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
  292. /*Wake*/ 0x1 &UIC2 0x16 0x4>;
  293. reg = <0xef601100 0x000000c4>;
  294. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  295. mal-device = <&MAL0>;
  296. mal-tx-channel = <2>;
  297. mal-rx-channel = <16>;
  298. cell-index = <2>;
  299. max-frame-size = <9000>;
  300. rx-fifo-size = <4096>;
  301. tx-fifo-size = <2048>;
  302. rx-fifo-size-gige = <16384>;
  303. tx-fifo-size-gige = <16384>; /* emac2&3 only */
  304. phy-mode = "sgmii";
  305. phy-map = <0x00000001>;
  306. gpcs-address = <0x0000000C>;
  307. has-inverted-stacr-oc;
  308. has-new-stacr-staopc;
  309. mdio-device = <&EMAC0>;
  310. };
  311. };
  312. };
  313. };