ac14xx.dts 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Device Tree Source for the MPC5121e based ac14xx board
  4. *
  5. * Copyright 2012 Anatolij Gustschin <[email protected]>
  6. */
  7. #include "mpc5121.dtsi"
  8. / {
  9. model = "ac14xx";
  10. compatible = "ifm,ac14xx", "fsl,mpc5121";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. aliases {
  14. serial0 = &serial0;
  15. serial1 = &serial7;
  16. spi4 = &spi4;
  17. spi5 = &spi5;
  18. };
  19. cpus {
  20. PowerPC,5121@0 {
  21. timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
  22. bus-frequency = <160000000>; /* 160 MHz csb bus */
  23. clock-frequency = <400000000>; /* 400 MHz ppc core */
  24. };
  25. };
  26. memory {
  27. reg = <0x00000000 0x10000000>; /* 256MB at 0 */
  28. };
  29. nfc@40000000 {
  30. status = "disabled";
  31. };
  32. localbus@80000020 {
  33. ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
  34. 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
  35. 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
  36. 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
  37. 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
  38. 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
  39. flash@0,0 {
  40. compatible = "cfi-flash";
  41. reg = <0 0x00000000 0x04000000>;
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. bank-width = <2>;
  45. device-width = <2>;
  46. partition@0 {
  47. label = "dtb-kernel-production";
  48. reg = <0x00000000 0x00400000>;
  49. };
  50. partition@1 {
  51. label = "filesystem-production";
  52. reg = <0x00400000 0x03400000>;
  53. };
  54. partition@2 {
  55. label = "recovery";
  56. reg = <0x03800000 0x00700000>;
  57. };
  58. partition@3 {
  59. label = "uboot-code";
  60. reg = <0x03f00000 0x00040000>;
  61. };
  62. partition@4 {
  63. label = "uboot-env1";
  64. reg = <0x03f40000 0x00020000>;
  65. };
  66. partition@5 {
  67. label = "uboot-env2";
  68. reg = <0x03f60000 0x00020000>;
  69. };
  70. };
  71. fram@1,0 {
  72. compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
  73. reg = <1 0x00000000 0x00010000>;
  74. };
  75. asi@2,0 {
  76. /* masters mapping: CS, CS offset, size */
  77. reg = <2 0x00000000 0x00080000
  78. 6 0x00000000 0x00080000>;
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "ifm,ac14xx-asi-fpga";
  82. gpios = <
  83. &gpio_pic 26 0 /* prog */
  84. &gpio_pic 27 0 /* done */
  85. &gpio_pic 10 0 /* reset */
  86. >;
  87. master@1 {
  88. interrupts = <20 0x2>;
  89. interrupt-parent = <&gpio_pic>;
  90. chipselect = <2 0x00009000 0x00009100>;
  91. label = "AS-i master 1";
  92. };
  93. master@2 {
  94. interrupts = <21 0x2>;
  95. interrupt-parent = <&gpio_pic>;
  96. chipselect = <6 0x00009000 0x00009100>;
  97. label = "AS-i master 2";
  98. };
  99. };
  100. netx@3,0 {
  101. compatible = "ifm,netx";
  102. reg = <0x3 0x00000000 0x00020000>;
  103. chipselect = <3 0x00101140 0x00203100>;
  104. interrupts = <17 0x8>;
  105. gpios = <&gpio_pic 15 0>;
  106. };
  107. safety@5,0 {
  108. compatible = "ifm,safety";
  109. reg = <0x5 0x00000000 0x00010000>;
  110. chipselect = <5 0x00009000 0x00009100>;
  111. interrupts = <22 0x2>;
  112. interrupt-parent = <&gpio_pic>;
  113. gpios = <
  114. &gpio_pic 12 0 /* prog */
  115. &gpio_pic 11 0 /* done */
  116. >;
  117. };
  118. };
  119. clocks {
  120. osc {
  121. clock-frequency = <25000000>;
  122. };
  123. };
  124. soc@80000000 {
  125. bus-frequency = <80000000>; /* 80 MHz ips bus */
  126. clock@f00 {
  127. compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
  128. };
  129. /*
  130. * GPIO PIC:
  131. * interrupts cell = <pin nr, sense>
  132. * sense == 8: Level, low assertion
  133. * sense == 2: Edge, high-to-low change
  134. */
  135. gpio_pic: gpio@1100 {
  136. gpio-controller;
  137. #gpio-cells = <2>;
  138. interrupt-controller;
  139. #interrupt-cells = <2>;
  140. };
  141. sdhc@1500 {
  142. cd-gpios = <&gpio_pic 23 0>; /* card detect */
  143. wp-gpios = <&gpio_pic 24 0>; /* write protect */
  144. wp-inverted; /* WP active high */
  145. };
  146. i2c@1700 {
  147. /* use Fast-mode */
  148. clock-frequency = <400000>;
  149. at24@30 {
  150. compatible = "atmel,24c01";
  151. reg = <0x30>;
  152. };
  153. at24@31 {
  154. compatible = "atmel,24c01";
  155. reg = <0x31>;
  156. };
  157. temp@48 {
  158. compatible = "ad,ad7414";
  159. reg = <0x48>;
  160. };
  161. at24@50 {
  162. compatible = "atmel,24c01";
  163. reg = <0x50>;
  164. };
  165. at24@51 {
  166. compatible = "atmel,24c01";
  167. reg = <0x51>;
  168. };
  169. at24@52 {
  170. compatible = "atmel,24c01";
  171. reg = <0x52>;
  172. };
  173. at24@53 {
  174. compatible = "atmel,24c01";
  175. reg = <0x53>;
  176. };
  177. at24@54 {
  178. compatible = "atmel,24c01";
  179. reg = <0x54>;
  180. };
  181. at24@55 {
  182. compatible = "atmel,24c01";
  183. reg = <0x55>;
  184. };
  185. at24@56 {
  186. compatible = "atmel,24c01";
  187. reg = <0x56>;
  188. };
  189. at24@57 {
  190. compatible = "atmel,24c01";
  191. reg = <0x57>;
  192. };
  193. rtc@68 {
  194. compatible = "st,m41t00";
  195. reg = <0x68>;
  196. };
  197. };
  198. axe_pic: axe-base@2000 {
  199. compatible = "fsl,mpc5121-axe-base";
  200. reg = <0x2000 0x100>;
  201. interrupts = <42 0x8>;
  202. interrupt-controller;
  203. #interrupt-cells = <2>;
  204. };
  205. axe-app {
  206. compatible = "fsl,mpc5121-axe-app";
  207. interrupt-parent = <&axe_pic>;
  208. interrupts = <
  209. /* soft interrupts */
  210. 0 0x0 1 0x0 2 0x0 3 0x0
  211. 4 0x0 5 0x0 6 0x0 7 0x0
  212. /* fifo interrupts */
  213. 8 0x0 9 0x0 10 0x0 11 0x0
  214. >;
  215. };
  216. display@2100 {
  217. edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
  218. 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
  219. 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
  220. 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
  221. 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
  222. 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
  223. 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
  224. 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
  225. };
  226. can@2300 {
  227. status = "disabled";
  228. };
  229. can@2380 {
  230. status = "disabled";
  231. };
  232. viu@2400 {
  233. status = "disabled";
  234. };
  235. mdio@2800 {
  236. phy0: ethernet-phy@1f {
  237. compatible = "smsc,lan8700";
  238. reg = <0x1f>;
  239. };
  240. };
  241. enet: ethernet@2800 {
  242. phy-handle = <&phy0>;
  243. };
  244. usb@3000 {
  245. status = "disabled";
  246. };
  247. usb@4000 {
  248. status = "disabled";
  249. };
  250. /* PSC3 serial port A, aka ttyPSC0 */
  251. serial0: psc@11300 {
  252. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  253. fsl,rx-fifo-size = <512>;
  254. fsl,tx-fifo-size = <512>;
  255. };
  256. /* PSC4 in SPI mode */
  257. spi4: psc@11400 {
  258. compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
  259. fsl,rx-fifo-size = <768>;
  260. fsl,tx-fifo-size = <768>;
  261. #address-cells = <1>;
  262. #size-cells = <0>;
  263. num-cs = <1>;
  264. cs-gpios = <&gpio_pic 25 0>;
  265. flash: m25p128@0 {
  266. compatible = "st,m25p128";
  267. spi-max-frequency = <20000000>;
  268. reg = <0>;
  269. #address-cells = <1>;
  270. #size-cells = <1>;
  271. partition@0 {
  272. label = "spi-flash0";
  273. reg = <0x00000000 0x01000000>;
  274. };
  275. };
  276. };
  277. /* PSC5 in SPI mode */
  278. spi5: psc@11500 {
  279. compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
  280. fsl,mode = "spi-master";
  281. fsl,rx-fifo-size = <128>;
  282. fsl,tx-fifo-size = <128>;
  283. #address-cells = <1>;
  284. #size-cells = <0>;
  285. lcd@0 {
  286. compatible = "ilitek,ili922x";
  287. reg = <0>;
  288. spi-max-frequency = <100000>;
  289. spi-cpol;
  290. spi-cpha;
  291. };
  292. };
  293. /* PSC7 serial port C, aka ttyPSC2 */
  294. serial7: psc@11700 {
  295. compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
  296. fsl,rx-fifo-size = <512>;
  297. fsl,tx-fifo-size = <512>;
  298. };
  299. matrix_keypad@0 {
  300. compatible = "gpio-matrix-keypad";
  301. debounce-delay-ms = <5>;
  302. col-scan-delay-us = <1>;
  303. gpio-activelow;
  304. col-gpios-binary;
  305. col-switch-delay-ms = <200>;
  306. col-gpios = <&gpio_pic 1 0>; /* pin1 */
  307. row-gpios = <&gpio_pic 2 0 /* pin2 */
  308. &gpio_pic 3 0 /* pin3 */
  309. &gpio_pic 4 0>; /* pin4 */
  310. linux,keymap = <0x0000006e /* FN LEFT */
  311. 0x01000067 /* UP */
  312. 0x02000066 /* FN RIGHT */
  313. 0x00010069 /* LEFT */
  314. 0x0101006a /* DOWN */
  315. 0x0201006c>; /* RIGHT */
  316. };
  317. };
  318. leds {
  319. compatible = "gpio-leds";
  320. backlight {
  321. label = "backlight";
  322. gpios = <&gpio_pic 0 0>;
  323. default-state = "keep";
  324. };
  325. green {
  326. label = "green";
  327. gpios = <&gpio_pic 18 0>;
  328. default-state = "keep";
  329. };
  330. red {
  331. label = "red";
  332. gpios = <&gpio_pic 19 0>;
  333. default-state = "keep";
  334. };
  335. };
  336. };