a4m072.dts 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * a4m072 board Device Tree Source
  4. *
  5. * Copyright (C) 2011 DENX Software Engineering GmbH
  6. * Heiko Schocher <[email protected]>
  7. *
  8. * Copyright (C) 2007 Semihalf
  9. * Marian Balakowicz <[email protected]>
  10. */
  11. /include/ "mpc5200b.dtsi"
  12. &gpt0 { fsl,has-wdt; };
  13. &gpt3 { gpio-controller; };
  14. &gpt4 { gpio-controller; };
  15. &gpt5 { gpio-controller; };
  16. / {
  17. model = "anonymous,a4m072";
  18. compatible = "anonymous,a4m072";
  19. soc5200@f0000000 {
  20. #address-cells = <1>;
  21. #size-cells = <1>;
  22. compatible = "fsl,mpc5200b-immr";
  23. ranges = <0 0xf0000000 0x0000c000>;
  24. reg = <0xf0000000 0x00000100>;
  25. bus-frequency = <0>; /* From boot loader */
  26. system-frequency = <0>; /* From boot loader */
  27. cdm@200 {
  28. fsl,init-ext-48mhz-en = <0x0>;
  29. fsl,init-fd-enable = <0x01>;
  30. fsl,init-fd-counters = <0x3333>;
  31. };
  32. spi@f00 {
  33. status = "disabled";
  34. };
  35. psc@2000 {
  36. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  37. reg = <0x2000 0x100>;
  38. interrupts = <2 1 0>;
  39. };
  40. psc@2200 {
  41. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  42. reg = <0x2200 0x100>;
  43. interrupts = <2 2 0>;
  44. };
  45. psc@2400 {
  46. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  47. reg = <0x2400 0x100>;
  48. interrupts = <2 3 0>;
  49. };
  50. psc@2600 {
  51. status = "disabled";
  52. };
  53. psc@2800 {
  54. status = "disabled";
  55. };
  56. psc@2c00 {
  57. compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
  58. reg = <0x2c00 0x100>;
  59. interrupts = <2 4 0>;
  60. };
  61. ethernet@3000 {
  62. phy-handle = <&phy0>;
  63. };
  64. mdio@3000 {
  65. phy0: ethernet-phy@1f {
  66. reg = <0x1f>;
  67. interrupts = <1 2 0>; /* IRQ 2 active low */
  68. };
  69. };
  70. i2c@3d00 {
  71. status = "disabled";
  72. };
  73. i2c@3d40 {
  74. hwmon@2e {
  75. compatible = "nsc,lm87";
  76. reg = <0x2e>;
  77. };
  78. rtc@51 {
  79. compatible = "nxp,rtc8564";
  80. reg = <0x51>;
  81. };
  82. };
  83. };
  84. localbus {
  85. compatible = "fsl,mpc5200b-lpb","simple-bus";
  86. #address-cells = <2>;
  87. #size-cells = <1>;
  88. ranges = <0 0 0xfe000000 0x02000000
  89. 1 0 0x62000000 0x00400000
  90. 2 0 0x64000000 0x00200000
  91. 3 0 0x66000000 0x01000000
  92. 6 0 0x68000000 0x01000000
  93. 7 0 0x6a000000 0x00000004>;
  94. flash@0,0 {
  95. compatible = "cfi-flash";
  96. reg = <0 0 0x02000000>;
  97. bank-width = <2>;
  98. #size-cells = <1>;
  99. #address-cells = <1>;
  100. };
  101. sram0@1,0 {
  102. compatible = "mtd-ram";
  103. reg = <1 0x00000 0x00400000>;
  104. bank-width = <2>;
  105. };
  106. };
  107. pci@f0000d00 {
  108. #interrupt-cells = <1>;
  109. #size-cells = <2>;
  110. #address-cells = <3>;
  111. device_type = "pci";
  112. compatible = "fsl,mpc5200-pci";
  113. reg = <0xf0000d00 0x100>;
  114. interrupt-map-mask = <0xf800 0 0 7>;
  115. interrupt-map = <
  116. /* IDSEL 0x16 */
  117. 0xc000 0 0 1 &mpc5200_pic 1 3 3
  118. 0xc000 0 0 2 &mpc5200_pic 1 3 3
  119. 0xc000 0 0 3 &mpc5200_pic 1 3 3
  120. 0xc000 0 0 4 &mpc5200_pic 1 3 3>;
  121. clock-frequency = <0>; /* From boot loader */
  122. interrupts = <2 8 0 2 9 0 2 10 0>;
  123. bus-range = <0 0>;
  124. ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
  125. <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
  126. <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
  127. };
  128. };