time.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/parisc/kernel/time.c
  4. *
  5. * Copyright (C) 1991, 1992, 1995 Linus Torvalds
  6. * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
  7. * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, [email protected])
  8. *
  9. * 1994-07-02 Alan Modra
  10. * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
  11. * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
  12. * "A Kernel Model for Precision Timekeeping" by Dave Mills
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/module.h>
  16. #include <linux/rtc.h>
  17. #include <linux/sched.h>
  18. #include <linux/sched/clock.h>
  19. #include <linux/sched_clock.h>
  20. #include <linux/kernel.h>
  21. #include <linux/param.h>
  22. #include <linux/string.h>
  23. #include <linux/mm.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/time.h>
  26. #include <linux/init.h>
  27. #include <linux/smp.h>
  28. #include <linux/profile.h>
  29. #include <linux/clocksource.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/ftrace.h>
  32. #include <linux/uaccess.h>
  33. #include <asm/io.h>
  34. #include <asm/irq.h>
  35. #include <asm/page.h>
  36. #include <asm/param.h>
  37. #include <asm/pdc.h>
  38. #include <asm/led.h>
  39. #include <linux/timex.h>
  40. int time_keeper_id __read_mostly; /* CPU used for timekeeping. */
  41. static unsigned long clocktick __ro_after_init; /* timer cycles per tick */
  42. /*
  43. * We keep time on PA-RISC Linux by using the Interval Timer which is
  44. * a pair of registers; one is read-only and one is write-only; both
  45. * accessed through CR16. The read-only register is 32 or 64 bits wide,
  46. * and increments by 1 every CPU clock tick. The architecture only
  47. * guarantees us a rate between 0.5 and 2, but all implementations use a
  48. * rate of 1. The write-only register is 32-bits wide. When the lowest
  49. * 32 bits of the read-only register compare equal to the write-only
  50. * register, it raises a maskable external interrupt. Each processor has
  51. * an Interval Timer of its own and they are not synchronised.
  52. *
  53. * We want to generate an interrupt every 1/HZ seconds. So we program
  54. * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
  55. * is programmed with the intended time of the next tick. We can be
  56. * held off for an arbitrarily long period of time by interrupts being
  57. * disabled, so we may miss one or more ticks.
  58. */
  59. irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
  60. {
  61. unsigned long now;
  62. unsigned long next_tick;
  63. unsigned long ticks_elapsed = 0;
  64. unsigned int cpu = smp_processor_id();
  65. struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
  66. /* gcc can optimize for "read-only" case with a local clocktick */
  67. unsigned long cpt = clocktick;
  68. /* Initialize next_tick to the old expected tick time. */
  69. next_tick = cpuinfo->it_value;
  70. /* Calculate how many ticks have elapsed. */
  71. now = mfctl(16);
  72. do {
  73. ++ticks_elapsed;
  74. next_tick += cpt;
  75. } while (next_tick - now > cpt);
  76. /* Store (in CR16 cycles) up to when we are accounting right now. */
  77. cpuinfo->it_value = next_tick;
  78. /* Go do system house keeping. */
  79. if (IS_ENABLED(CONFIG_SMP) && (cpu != time_keeper_id))
  80. ticks_elapsed = 0;
  81. legacy_timer_tick(ticks_elapsed);
  82. /* Skip clockticks on purpose if we know we would miss those.
  83. * The new CR16 must be "later" than current CR16 otherwise
  84. * itimer would not fire until CR16 wrapped - e.g 4 seconds
  85. * later on a 1Ghz processor. We'll account for the missed
  86. * ticks on the next timer interrupt.
  87. * We want IT to fire modulo clocktick even if we miss/skip some.
  88. * But those interrupts don't in fact get delivered that regularly.
  89. *
  90. * "next_tick - now" will always give the difference regardless
  91. * if one or the other wrapped. If "now" is "bigger" we'll end up
  92. * with a very large unsigned number.
  93. */
  94. now = mfctl(16);
  95. while (next_tick - now > cpt)
  96. next_tick += cpt;
  97. /* Program the IT when to deliver the next interrupt.
  98. * Only bottom 32-bits of next_tick are writable in CR16!
  99. * Timer interrupt will be delivered at least a few hundred cycles
  100. * after the IT fires, so if we are too close (<= 8000 cycles) to the
  101. * next cycle, simply skip it.
  102. */
  103. if (next_tick - now <= 8000)
  104. next_tick += cpt;
  105. mtctl(next_tick, 16);
  106. return IRQ_HANDLED;
  107. }
  108. unsigned long profile_pc(struct pt_regs *regs)
  109. {
  110. unsigned long pc = instruction_pointer(regs);
  111. if (regs->gr[0] & PSW_N)
  112. pc -= 4;
  113. #ifdef CONFIG_SMP
  114. if (in_lock_functions(pc))
  115. pc = regs->gr[2];
  116. #endif
  117. return pc;
  118. }
  119. EXPORT_SYMBOL(profile_pc);
  120. /* clock source code */
  121. static u64 notrace read_cr16(struct clocksource *cs)
  122. {
  123. return get_cycles();
  124. }
  125. static struct clocksource clocksource_cr16 = {
  126. .name = "cr16",
  127. .rating = 300,
  128. .read = read_cr16,
  129. .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
  130. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  131. };
  132. void start_cpu_itimer(void)
  133. {
  134. unsigned int cpu = smp_processor_id();
  135. unsigned long next_tick = mfctl(16) + clocktick;
  136. mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
  137. per_cpu(cpu_data, cpu).it_value = next_tick;
  138. }
  139. #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
  140. static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
  141. {
  142. struct pdc_tod tod_data;
  143. memset(tm, 0, sizeof(*tm));
  144. if (pdc_tod_read(&tod_data) < 0)
  145. return -EOPNOTSUPP;
  146. /* we treat tod_sec as unsigned, so this can work until year 2106 */
  147. rtc_time64_to_tm(tod_data.tod_sec, tm);
  148. return 0;
  149. }
  150. static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
  151. {
  152. time64_t secs = rtc_tm_to_time64(tm);
  153. int ret;
  154. /* hppa has Y2K38 problem: pdc_tod_set() takes an u32 value! */
  155. ret = pdc_tod_set(secs, 0);
  156. if (ret != 0) {
  157. pr_warn("pdc_tod_set(%lld) returned error %d\n", secs, ret);
  158. if (ret == PDC_INVALID_ARG)
  159. return -EINVAL;
  160. return -EOPNOTSUPP;
  161. }
  162. return 0;
  163. }
  164. static const struct rtc_class_ops rtc_generic_ops = {
  165. .read_time = rtc_generic_get_time,
  166. .set_time = rtc_generic_set_time,
  167. };
  168. static int __init rtc_init(void)
  169. {
  170. struct platform_device *pdev;
  171. pdev = platform_device_register_data(NULL, "rtc-generic", -1,
  172. &rtc_generic_ops,
  173. sizeof(rtc_generic_ops));
  174. return PTR_ERR_OR_ZERO(pdev);
  175. }
  176. device_initcall(rtc_init);
  177. #endif
  178. void read_persistent_clock64(struct timespec64 *ts)
  179. {
  180. static struct pdc_tod tod_data;
  181. if (pdc_tod_read(&tod_data) == 0) {
  182. ts->tv_sec = tod_data.tod_sec;
  183. ts->tv_nsec = tod_data.tod_usec * 1000;
  184. } else {
  185. printk(KERN_ERR "Error reading tod clock\n");
  186. ts->tv_sec = 0;
  187. ts->tv_nsec = 0;
  188. }
  189. }
  190. static u64 notrace read_cr16_sched_clock(void)
  191. {
  192. return get_cycles();
  193. }
  194. /*
  195. * timer interrupt and sched_clock() initialization
  196. */
  197. void __init time_init(void)
  198. {
  199. unsigned long cr16_hz;
  200. clocktick = (100 * PAGE0->mem_10msec) / HZ;
  201. start_cpu_itimer(); /* get CPU 0 started */
  202. cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */
  203. /* register as sched_clock source */
  204. sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
  205. }
  206. static int __init init_cr16_clocksource(void)
  207. {
  208. /*
  209. * The cr16 interval timers are not synchronized across CPUs.
  210. */
  211. if (num_online_cpus() > 1 && !running_on_qemu) {
  212. clocksource_cr16.name = "cr16_unstable";
  213. clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
  214. clocksource_cr16.rating = 0;
  215. }
  216. /* register at clocksource framework */
  217. clocksource_register_hz(&clocksource_cr16,
  218. 100 * PAGE0->mem_10msec);
  219. return 0;
  220. }
  221. device_initcall(init_cr16_clocksource);