pci.c 6.9 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1997, 1998 Ralf Baechle
  7. * Copyright (C) 1999 SuSE GmbH
  8. * Copyright (C) 1999-2001 Hewlett-Packard Company
  9. * Copyright (C) 1999-2001 Grant Grundler
  10. */
  11. #include <linux/eisa.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/pci.h>
  16. #include <linux/types.h>
  17. #include <asm/io.h>
  18. #include <asm/superio.h>
  19. #define DEBUG_RESOURCES 0
  20. #define DEBUG_CONFIG 0
  21. #if DEBUG_CONFIG
  22. # define DBGC(x...) printk(KERN_DEBUG x)
  23. #else
  24. # define DBGC(x...)
  25. #endif
  26. #if DEBUG_RESOURCES
  27. #define DBG_RES(x...) printk(KERN_DEBUG x)
  28. #else
  29. #define DBG_RES(x...)
  30. #endif
  31. struct pci_port_ops *pci_port __ro_after_init;
  32. struct pci_bios_ops *pci_bios __ro_after_init;
  33. static int pci_hba_count __ro_after_init;
  34. /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */
  35. #define PCI_HBA_MAX 32
  36. static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __ro_after_init;
  37. /********************************************************************
  38. **
  39. ** I/O port space support
  40. **
  41. *********************************************************************/
  42. /* EISA port numbers and PCI port numbers share the same interface. Some
  43. * machines have both EISA and PCI adapters installed. Rather than turn
  44. * pci_port into an array, we reserve bus 0 for EISA and call the EISA
  45. * routines if the access is to a port on bus 0. We don't want to fix
  46. * EISA and ISA drivers which assume port space is <= 0xffff.
  47. */
  48. #ifdef CONFIG_EISA
  49. #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr)
  50. #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr)
  51. #else
  52. #define EISA_IN(size)
  53. #define EISA_OUT(size)
  54. #endif
  55. #define PCI_PORT_IN(type, size) \
  56. u##size in##type (int addr) \
  57. { \
  58. int b = PCI_PORT_HBA(addr); \
  59. EISA_IN(size); \
  60. if (!parisc_pci_hba[b]) return (u##size) -1; \
  61. return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
  62. } \
  63. EXPORT_SYMBOL(in##type);
  64. PCI_PORT_IN(b, 8)
  65. PCI_PORT_IN(w, 16)
  66. PCI_PORT_IN(l, 32)
  67. #define PCI_PORT_OUT(type, size) \
  68. void out##type (u##size d, int addr) \
  69. { \
  70. int b = PCI_PORT_HBA(addr); \
  71. EISA_OUT(size); \
  72. if (!parisc_pci_hba[b]) return; \
  73. pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \
  74. } \
  75. EXPORT_SYMBOL(out##type);
  76. PCI_PORT_OUT(b, 8)
  77. PCI_PORT_OUT(w, 16)
  78. PCI_PORT_OUT(l, 32)
  79. /*
  80. * BIOS32 replacement.
  81. */
  82. static int __init pcibios_init(void)
  83. {
  84. if (!pci_bios)
  85. return -1;
  86. if (pci_bios->init) {
  87. pci_bios->init();
  88. } else {
  89. printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
  90. }
  91. /* Set the CLS for PCI as early as possible. */
  92. pci_cache_line_size = pci_dfl_cache_line_size;
  93. return 0;
  94. }
  95. /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */
  96. void pcibios_fixup_bus(struct pci_bus *bus)
  97. {
  98. if (pci_bios->fixup_bus) {
  99. pci_bios->fixup_bus(bus);
  100. } else {
  101. printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n");
  102. }
  103. }
  104. /*
  105. * Called by pci_set_master() - a driver interface.
  106. *
  107. * Legacy PDC guarantees to set:
  108. * Map Memory BAR's into PA IO space.
  109. * Map Expansion ROM BAR into one common PA IO space per bus.
  110. * Map IO BAR's into PCI IO space.
  111. * Command (see below)
  112. * Cache Line Size
  113. * Latency Timer
  114. * Interrupt Line
  115. * PPB: secondary latency timer, io/mmio base/limit,
  116. * bus numbers, bridge control
  117. *
  118. */
  119. void pcibios_set_master(struct pci_dev *dev)
  120. {
  121. u8 lat;
  122. /* If someone already mucked with this, don't touch it. */
  123. pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
  124. if (lat >= 16) return;
  125. /*
  126. ** HP generally has fewer devices on the bus than other architectures.
  127. ** upper byte is PCI_LATENCY_TIMER.
  128. */
  129. pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
  130. (0x80 << 8) | pci_cache_line_size);
  131. }
  132. /*
  133. * pcibios_init_bridge() initializes cache line and default latency
  134. * for pci controllers and pci-pci bridges
  135. */
  136. void __ref pcibios_init_bridge(struct pci_dev *dev)
  137. {
  138. unsigned short bridge_ctl, bridge_ctl_new;
  139. /* We deal only with pci controllers and pci-pci bridges. */
  140. if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
  141. return;
  142. /* PCI-PCI bridge - set the cache line and default latency
  143. * (32) for primary and secondary buses.
  144. */
  145. pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
  146. pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
  147. bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
  148. PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
  149. dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
  150. bridge_ctl, bridge_ctl_new);
  151. pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
  152. }
  153. /*
  154. * pcibios align resources() is called every time generic PCI code
  155. * wants to generate a new address. The process of looking for
  156. * an available address, each candidate is first "aligned" and
  157. * then checked if the resource is available until a match is found.
  158. *
  159. * Since we are just checking candidates, don't use any fields other
  160. * than res->start.
  161. */
  162. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  163. resource_size_t size, resource_size_t alignment)
  164. {
  165. resource_size_t mask, align, start = res->start;
  166. DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
  167. pci_name(((struct pci_dev *) data)),
  168. res->parent, res->start, res->end,
  169. (int) res->flags, size, alignment);
  170. /* If it's not IO, then it's gotta be MEM */
  171. align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
  172. /* Align to largest of MIN or input size */
  173. mask = max(alignment, align) - 1;
  174. start += mask;
  175. start &= ~mask;
  176. return start;
  177. }
  178. /*
  179. * A driver is enabling the device. We make sure that all the appropriate
  180. * bits are set to allow the device to operate as the driver is expecting.
  181. * We enable the port IO and memory IO bits if the device has any BARs of
  182. * that type, and we enable the PERR and SERR bits unconditionally.
  183. * Drivers that do not need parity (eg graphics and possibly networking)
  184. * can clear these bits if they want.
  185. */
  186. int pcibios_enable_device(struct pci_dev *dev, int mask)
  187. {
  188. int err;
  189. u16 cmd, old_cmd;
  190. err = pci_enable_resources(dev, mask);
  191. if (err < 0)
  192. return err;
  193. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  194. old_cmd = cmd;
  195. cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  196. #if 0
  197. /* If bridge/bus controller has FBB enabled, child must too. */
  198. if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
  199. cmd |= PCI_COMMAND_FAST_BACK;
  200. #endif
  201. if (cmd != old_cmd) {
  202. dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
  203. old_cmd, cmd);
  204. pci_write_config_word(dev, PCI_COMMAND, cmd);
  205. }
  206. return 0;
  207. }
  208. /* PA-RISC specific */
  209. void pcibios_register_hba(struct pci_hba_data *hba)
  210. {
  211. if (pci_hba_count >= PCI_HBA_MAX) {
  212. printk(KERN_ERR "PCI: Too many Host Bus Adapters\n");
  213. return;
  214. }
  215. parisc_pci_hba[pci_hba_count] = hba;
  216. hba->hba_num = pci_hba_count++;
  217. }
  218. subsys_initcall(pcibios_init);