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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * Linux/PA-RISC Project (http://www.parisc-linux.org/)
  4. *
  5. * kernel entry points (interruptions, system call wrappers)
  6. * Copyright (C) 1999,2000 Philipp Rumpf
  7. * Copyright (C) 1999 SuSE GmbH Nuernberg
  8. * Copyright (C) 2000 Hewlett-Packard (John Marvin)
  9. * Copyright (C) 1999 Hewlett-Packard (Frank Rowand)
  10. */
  11. #include <asm/asm-offsets.h>
  12. /* we have the following possibilities to act on an interruption:
  13. * - handle in assembly and use shadowed registers only
  14. * - save registers to kernel stack and handle in assembly or C */
  15. #include <asm/psw.h>
  16. #include <asm/cache.h> /* for L1_CACHE_SHIFT */
  17. #include <asm/assembly.h> /* for LDREG/STREG defines */
  18. #include <asm/signal.h>
  19. #include <asm/unistd.h>
  20. #include <asm/ldcw.h>
  21. #include <asm/traps.h>
  22. #include <asm/thread_info.h>
  23. #include <asm/alternative.h>
  24. #include <linux/linkage.h>
  25. #include <linux/pgtable.h>
  26. #ifdef CONFIG_64BIT
  27. .level 2.0w
  28. #else
  29. .level 2.0
  30. #endif
  31. /* Get aligned page_table_lock address for this mm from cr28/tr4 */
  32. .macro get_ptl reg
  33. mfctl %cr28,\reg
  34. .endm
  35. /* space_to_prot macro creates a prot id from a space id */
  36. #if (SPACEID_SHIFT) == 0
  37. .macro space_to_prot spc prot
  38. depd,z \spc,62,31,\prot
  39. .endm
  40. #else
  41. .macro space_to_prot spc prot
  42. extrd,u \spc,(64 - (SPACEID_SHIFT)),32,\prot
  43. .endm
  44. #endif
  45. /*
  46. * The "get_stack" macros are responsible for determining the
  47. * kernel stack value.
  48. *
  49. * If sr7 == 0
  50. * Already using a kernel stack, so call the
  51. * get_stack_use_r30 macro to push a pt_regs structure
  52. * on the stack, and store registers there.
  53. * else
  54. * Need to set up a kernel stack, so call the
  55. * get_stack_use_cr30 macro to set up a pointer
  56. * to the pt_regs structure contained within the
  57. * task pointer pointed to by cr30. Load the stack
  58. * pointer from the task structure.
  59. *
  60. * Note that we use shadowed registers for temps until
  61. * we can save %r26 and %r29. %r26 is used to preserve
  62. * %r8 (a shadowed register) which temporarily contained
  63. * either the fault type ("code") or the eirr. We need
  64. * to use a non-shadowed register to carry the value over
  65. * the rfir in virt_map. We use %r26 since this value winds
  66. * up being passed as the argument to either do_cpu_irq_mask
  67. * or handle_interruption. %r29 is used to hold a pointer
  68. * the register save area, and once again, it needs to
  69. * be a non-shadowed register so that it survives the rfir.
  70. */
  71. .macro get_stack_use_cr30
  72. /* we save the registers in the task struct */
  73. copy %r30, %r17
  74. mfctl %cr30, %r1
  75. tophys %r1,%r9 /* task_struct */
  76. LDREG TASK_STACK(%r9),%r30
  77. ldo PT_SZ_ALGN(%r30),%r30
  78. mtsp %r0,%sr7 /* clear sr7 after kernel stack was set! */
  79. mtsp %r16,%sr3
  80. ldo TASK_REGS(%r9),%r9
  81. STREG %r17,PT_GR30(%r9)
  82. STREG %r29,PT_GR29(%r9)
  83. STREG %r26,PT_GR26(%r9)
  84. STREG %r16,PT_SR7(%r9)
  85. copy %r9,%r29
  86. .endm
  87. .macro get_stack_use_r30
  88. /* we put a struct pt_regs on the stack and save the registers there */
  89. tophys %r30,%r9
  90. copy %r30,%r1
  91. ldo PT_SZ_ALGN(%r30),%r30
  92. STREG %r1,PT_GR30(%r9)
  93. STREG %r29,PT_GR29(%r9)
  94. STREG %r26,PT_GR26(%r9)
  95. STREG %r16,PT_SR7(%r9)
  96. copy %r9,%r29
  97. .endm
  98. .macro rest_stack
  99. LDREG PT_GR1(%r29), %r1
  100. LDREG PT_GR30(%r29),%r30
  101. LDREG PT_GR29(%r29),%r29
  102. .endm
  103. /* default interruption handler
  104. * (calls traps.c:handle_interruption) */
  105. .macro def code
  106. b intr_save
  107. ldi \code, %r8
  108. .align 32
  109. .endm
  110. /* Interrupt interruption handler
  111. * (calls irq.c:do_cpu_irq_mask) */
  112. .macro extint code
  113. b intr_extint
  114. mfsp %sr7,%r16
  115. .align 32
  116. .endm
  117. .import os_hpmc, code
  118. /* HPMC handler */
  119. .macro hpmc code
  120. nop /* must be a NOP, will be patched later */
  121. load32 PA(os_hpmc), %r3
  122. bv,n 0(%r3)
  123. nop
  124. .word 0 /* checksum (will be patched) */
  125. .word 0 /* address of handler */
  126. .word 0 /* length of handler */
  127. .endm
  128. /*
  129. * Performance Note: Instructions will be moved up into
  130. * this part of the code later on, once we are sure
  131. * that the tlb miss handlers are close to final form.
  132. */
  133. /* Register definitions for tlb miss handler macros */
  134. va = r8 /* virtual address for which the trap occurred */
  135. spc = r24 /* space for which the trap occurred */
  136. #ifndef CONFIG_64BIT
  137. /*
  138. * itlb miss interruption handler (parisc 1.1 - 32 bit)
  139. */
  140. .macro itlb_11 code
  141. mfctl %pcsq, spc
  142. b itlb_miss_11
  143. mfctl %pcoq, va
  144. .align 32
  145. .endm
  146. #endif
  147. /*
  148. * itlb miss interruption handler (parisc 2.0)
  149. */
  150. .macro itlb_20 code
  151. mfctl %pcsq, spc
  152. #ifdef CONFIG_64BIT
  153. b itlb_miss_20w
  154. #else
  155. b itlb_miss_20
  156. #endif
  157. mfctl %pcoq, va
  158. .align 32
  159. .endm
  160. #ifndef CONFIG_64BIT
  161. /*
  162. * naitlb miss interruption handler (parisc 1.1 - 32 bit)
  163. */
  164. .macro naitlb_11 code
  165. mfctl %isr,spc
  166. b naitlb_miss_11
  167. mfctl %ior,va
  168. .align 32
  169. .endm
  170. #endif
  171. /*
  172. * naitlb miss interruption handler (parisc 2.0)
  173. */
  174. .macro naitlb_20 code
  175. mfctl %isr,spc
  176. #ifdef CONFIG_64BIT
  177. b naitlb_miss_20w
  178. #else
  179. b naitlb_miss_20
  180. #endif
  181. mfctl %ior,va
  182. .align 32
  183. .endm
  184. #ifndef CONFIG_64BIT
  185. /*
  186. * dtlb miss interruption handler (parisc 1.1 - 32 bit)
  187. */
  188. .macro dtlb_11 code
  189. mfctl %isr, spc
  190. b dtlb_miss_11
  191. mfctl %ior, va
  192. .align 32
  193. .endm
  194. #endif
  195. /*
  196. * dtlb miss interruption handler (parisc 2.0)
  197. */
  198. .macro dtlb_20 code
  199. mfctl %isr, spc
  200. #ifdef CONFIG_64BIT
  201. b dtlb_miss_20w
  202. #else
  203. b dtlb_miss_20
  204. #endif
  205. mfctl %ior, va
  206. .align 32
  207. .endm
  208. #ifndef CONFIG_64BIT
  209. /* nadtlb miss interruption handler (parisc 1.1 - 32 bit) */
  210. .macro nadtlb_11 code
  211. mfctl %isr,spc
  212. b nadtlb_miss_11
  213. mfctl %ior,va
  214. .align 32
  215. .endm
  216. #endif
  217. /* nadtlb miss interruption handler (parisc 2.0) */
  218. .macro nadtlb_20 code
  219. mfctl %isr,spc
  220. #ifdef CONFIG_64BIT
  221. b nadtlb_miss_20w
  222. #else
  223. b nadtlb_miss_20
  224. #endif
  225. mfctl %ior,va
  226. .align 32
  227. .endm
  228. #ifndef CONFIG_64BIT
  229. /*
  230. * dirty bit trap interruption handler (parisc 1.1 - 32 bit)
  231. */
  232. .macro dbit_11 code
  233. mfctl %isr,spc
  234. b dbit_trap_11
  235. mfctl %ior,va
  236. .align 32
  237. .endm
  238. #endif
  239. /*
  240. * dirty bit trap interruption handler (parisc 2.0)
  241. */
  242. .macro dbit_20 code
  243. mfctl %isr,spc
  244. #ifdef CONFIG_64BIT
  245. b dbit_trap_20w
  246. #else
  247. b dbit_trap_20
  248. #endif
  249. mfctl %ior,va
  250. .align 32
  251. .endm
  252. /* In LP64, the space contains part of the upper 32 bits of the
  253. * fault. We have to extract this and place it in the va,
  254. * zeroing the corresponding bits in the space register */
  255. .macro space_adjust spc,va,tmp
  256. #ifdef CONFIG_64BIT
  257. extrd,u \spc,63,SPACEID_SHIFT,\tmp
  258. depd %r0,63,SPACEID_SHIFT,\spc
  259. depd \tmp,31,SPACEID_SHIFT,\va
  260. #endif
  261. .endm
  262. .import swapper_pg_dir,code
  263. /* Get the pgd. For faults on space zero (kernel space), this
  264. * is simply swapper_pg_dir. For user space faults, the
  265. * pgd is stored in %cr25 */
  266. .macro get_pgd spc,reg
  267. ldil L%PA(swapper_pg_dir),\reg
  268. ldo R%PA(swapper_pg_dir)(\reg),\reg
  269. or,COND(=) %r0,\spc,%r0
  270. mfctl %cr25,\reg
  271. .endm
  272. /*
  273. space_check(spc,tmp,fault)
  274. spc - The space we saw the fault with.
  275. tmp - The place to store the current space.
  276. fault - Function to call on failure.
  277. Only allow faults on different spaces from the
  278. currently active one if we're the kernel
  279. */
  280. .macro space_check spc,tmp,fault
  281. mfsp %sr7,\tmp
  282. /* check against %r0 which is same value as LINUX_GATEWAY_SPACE */
  283. or,COND(<>) %r0,\spc,%r0 /* user may execute gateway page
  284. * as kernel, so defeat the space
  285. * check if it is */
  286. copy \spc,\tmp
  287. or,COND(=) %r0,\tmp,%r0 /* nullify if executing as kernel */
  288. cmpb,COND(<>),n \tmp,\spc,\fault
  289. .endm
  290. /* Look up a PTE in a 2-Level scheme (faulting at each
  291. * level if the entry isn't present
  292. *
  293. * NOTE: we use ldw even for LP64, since the short pointers
  294. * can address up to 1TB
  295. */
  296. .macro L2_ptep pmd,pte,index,va,fault
  297. #if CONFIG_PGTABLE_LEVELS == 3
  298. extru_safe \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
  299. #else
  300. extru_safe \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
  301. #endif
  302. dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
  303. #if CONFIG_PGTABLE_LEVELS < 3
  304. copy %r0,\pte
  305. #endif
  306. ldw,s \index(\pmd),\pmd
  307. bb,>=,n \pmd,_PxD_PRESENT_BIT,\fault
  308. dep %r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
  309. SHLREG \pmd,PxD_VALUE_SHIFT,\pmd
  310. extru_safe \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
  311. dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
  312. shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd /* pmd is now pte */
  313. .endm
  314. /* Look up PTE in a 3-Level scheme. */
  315. .macro L3_ptep pgd,pte,index,va,fault
  316. #if CONFIG_PGTABLE_LEVELS == 3
  317. copy %r0,\pte
  318. extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
  319. ldw,s \index(\pgd),\pgd
  320. bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
  321. shld \pgd,PxD_VALUE_SHIFT,\pgd
  322. #endif
  323. L2_ptep \pgd,\pte,\index,\va,\fault
  324. .endm
  325. /* Acquire page_table_lock and check page is present. */
  326. .macro ptl_lock spc,ptp,pte,tmp,tmp1,fault
  327. #ifdef CONFIG_TLB_PTLOCK
  328. 98: cmpib,COND(=),n 0,\spc,2f
  329. get_ptl \tmp
  330. 1: LDCW 0(\tmp),\tmp1
  331. cmpib,COND(=) 0,\tmp1,1b
  332. nop
  333. LDREG 0(\ptp),\pte
  334. bb,<,n \pte,_PAGE_PRESENT_BIT,3f
  335. b \fault
  336. stw \spc,0(\tmp)
  337. 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
  338. #endif
  339. 2: LDREG 0(\ptp),\pte
  340. bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault
  341. 3:
  342. .endm
  343. /* Release page_table_lock without reloading lock address.
  344. Note that the values in the register spc are limited to
  345. NR_SPACE_IDS (262144). Thus, the stw instruction always
  346. stores a nonzero value even when register spc is 64 bits.
  347. We use an ordered store to ensure all prior accesses are
  348. performed prior to releasing the lock. */
  349. .macro ptl_unlock0 spc,tmp
  350. #ifdef CONFIG_TLB_PTLOCK
  351. 98: or,COND(=) %r0,\spc,%r0
  352. stw,ma \spc,0(\tmp)
  353. 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
  354. #endif
  355. .endm
  356. /* Release page_table_lock. */
  357. .macro ptl_unlock1 spc,tmp
  358. #ifdef CONFIG_TLB_PTLOCK
  359. 98: get_ptl \tmp
  360. ptl_unlock0 \spc,\tmp
  361. 99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
  362. #endif
  363. .endm
  364. /* Set the _PAGE_ACCESSED bit of the PTE. Be clever and
  365. * don't needlessly dirty the cache line if it was already set */
  366. .macro update_accessed ptp,pte,tmp,tmp1
  367. ldi _PAGE_ACCESSED,\tmp1
  368. or \tmp1,\pte,\tmp
  369. and,COND(<>) \tmp1,\pte,%r0
  370. STREG \tmp,0(\ptp)
  371. .endm
  372. /* Set the dirty bit (and accessed bit). No need to be
  373. * clever, this is only used from the dirty fault */
  374. .macro update_dirty ptp,pte,tmp
  375. ldi _PAGE_ACCESSED|_PAGE_DIRTY,\tmp
  376. or \tmp,\pte,\pte
  377. STREG \pte,0(\ptp)
  378. .endm
  379. /* We have (depending on the page size):
  380. * - 38 to 52-bit Physical Page Number
  381. * - 12 to 26-bit page offset
  382. */
  383. /* bitshift difference between a PFN (based on kernel's PAGE_SIZE)
  384. * to a CPU TLB 4k PFN (4k => 12 bits to shift) */
  385. #define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
  386. #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12)
  387. #define PFN_START_BIT (63-ASM_PFN_PTE_SHIFT+(63-58)-PAGE_ADD_SHIFT)
  388. /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
  389. .macro convert_for_tlb_insert20 pte,tmp
  390. #ifdef CONFIG_HUGETLB_PAGE
  391. copy \pte,\tmp
  392. extrd,u \tmp,PFN_START_BIT,PFN_START_BIT+1,\pte
  393. depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
  394. (63-58)+PAGE_ADD_SHIFT,\pte
  395. extrd,u,*= \tmp,_PAGE_HPAGE_BIT+32,1,%r0
  396. depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\
  397. (63-58)+PAGE_ADD_HUGE_SHIFT,\pte
  398. #else /* Huge pages disabled */
  399. extrd,u \pte,PFN_START_BIT,PFN_START_BIT+1,\pte
  400. depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\
  401. (63-58)+PAGE_ADD_SHIFT,\pte
  402. #endif
  403. .endm
  404. /* Convert the pte and prot to tlb insertion values. How
  405. * this happens is quite subtle, read below */
  406. .macro make_insert_tlb spc,pte,prot,tmp
  407. space_to_prot \spc \prot /* create prot id from space */
  408. /* The following is the real subtlety. This is depositing
  409. * T <-> _PAGE_REFTRAP
  410. * D <-> _PAGE_DIRTY
  411. * B <-> _PAGE_DMB (memory break)
  412. *
  413. * Then incredible subtlety: The access rights are
  414. * _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE
  415. * See 3-14 of the parisc 2.0 manual
  416. *
  417. * Finally, _PAGE_READ goes in the top bit of PL1 (so we
  418. * trigger an access rights trap in user space if the user
  419. * tries to read an unreadable page */
  420. #if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT
  421. /* need to drop DMB bit, as it's used as SPECIAL flag */
  422. depi 0,_PAGE_SPECIAL_BIT,1,\pte
  423. #endif
  424. depd \pte,8,7,\prot
  425. /* PAGE_USER indicates the page can be read with user privileges,
  426. * so deposit X1|11 to PL1|PL2 (remember the upper bit of PL1
  427. * contains _PAGE_READ) */
  428. extrd,u,*= \pte,_PAGE_USER_BIT+32,1,%r0
  429. depdi 7,11,3,\prot
  430. /* If we're a gateway page, drop PL2 back to zero for promotion
  431. * to kernel privilege (so we can execute the page as kernel).
  432. * Any privilege promotion page always denys read and write */
  433. extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
  434. depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
  435. /* Enforce uncacheable pages.
  436. * This should ONLY be use for MMIO on PA 2.0 machines.
  437. * Memory/DMA is cache coherent on all PA2.0 machines we support
  438. * (that means T-class is NOT supported) and the memory controllers
  439. * on most of those machines only handles cache transactions.
  440. */
  441. extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
  442. depdi 1,12,1,\prot
  443. /* Drop prot bits and convert to page addr for iitlbt and idtlbt */
  444. convert_for_tlb_insert20 \pte \tmp
  445. .endm
  446. /* Identical macro to make_insert_tlb above, except it
  447. * makes the tlb entry for the differently formatted pa11
  448. * insertion instructions */
  449. .macro make_insert_tlb_11 spc,pte,prot
  450. #if _PAGE_SPECIAL_BIT == _PAGE_DMB_BIT
  451. /* need to drop DMB bit, as it's used as SPECIAL flag */
  452. depi 0,_PAGE_SPECIAL_BIT,1,\pte
  453. #endif
  454. zdep \spc,30,15,\prot
  455. dep \pte,8,7,\prot
  456. extru,= \pte,_PAGE_NO_CACHE_BIT,1,%r0
  457. depi 1,12,1,\prot
  458. extru,= \pte,_PAGE_USER_BIT,1,%r0
  459. depi 7,11,3,\prot /* Set for user space (1 rsvd for read) */
  460. extru,= \pte,_PAGE_GATEWAY_BIT,1,%r0
  461. depi 0,11,2,\prot /* If Gateway, Set PL2 to 0 */
  462. /* Get rid of prot bits and convert to page addr for iitlba */
  463. depi 0,31,ASM_PFN_PTE_SHIFT,\pte
  464. SHRREG \pte,(ASM_PFN_PTE_SHIFT-(31-26)),\pte
  465. .endm
  466. /* This is for ILP32 PA2.0 only. The TLB insertion needs
  467. * to extend into I/O space if the address is 0xfXXXXXXX
  468. * so we extend the f's into the top word of the pte in
  469. * this case */
  470. .macro f_extend pte,tmp
  471. extrd,s \pte,42,4,\tmp
  472. addi,<> 1,\tmp,%r0
  473. extrd,s \pte,63,25,\pte
  474. .endm
  475. /* The alias region is comprised of a pair of 4 MB regions
  476. * aligned to 8 MB. It is used to clear/copy/flush user pages
  477. * using kernel virtual addresses congruent with the user
  478. * virtual address.
  479. *
  480. * To use the alias page, you set %r26 up with the to TLB
  481. * entry (identifying the physical page) and %r23 up with
  482. * the from tlb entry (or nothing if only a to entry---for
  483. * clear_user_page_asm) */
  484. .macro do_alias spc,tmp,tmp1,va,pte,prot,fault,patype
  485. cmpib,COND(<>),n 0,\spc,\fault
  486. ldil L%(TMPALIAS_MAP_START),\tmp
  487. copy \va,\tmp1
  488. depi_safe 0,31,TMPALIAS_SIZE_BITS+1,\tmp1
  489. cmpb,COND(<>),n \tmp,\tmp1,\fault
  490. mfctl %cr19,\tmp /* iir */
  491. /* get the opcode (first six bits) into \tmp */
  492. extrw,u \tmp,5,6,\tmp
  493. /*
  494. * Only setting the T bit prevents data cache movein
  495. * Setting access rights to zero prevents instruction cache movein
  496. *
  497. * Note subtlety here: _PAGE_GATEWAY, _PAGE_EXEC and _PAGE_WRITE go
  498. * to type field and _PAGE_READ goes to top bit of PL1
  499. */
  500. ldi (_PAGE_REFTRAP|_PAGE_READ|_PAGE_WRITE),\prot
  501. /*
  502. * so if the opcode is one (i.e. this is a memory management
  503. * instruction) nullify the next load so \prot is only T.
  504. * Otherwise this is a normal data operation
  505. */
  506. cmpiclr,= 0x01,\tmp,%r0
  507. ldi (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
  508. .ifc \patype,20
  509. depd,z \prot,8,7,\prot
  510. .else
  511. .ifc \patype,11
  512. depw,z \prot,8,7,\prot
  513. .else
  514. .error "undefined PA type to do_alias"
  515. .endif
  516. .endif
  517. /*
  518. * OK, it is in the temp alias region, check whether "from" or "to".
  519. * Check "subtle" note in pacache.S re: r23/r26.
  520. */
  521. extrw,u,= \va,31-TMPALIAS_SIZE_BITS,1,%r0
  522. or,COND(tr) %r23,%r0,\pte
  523. or %r26,%r0,\pte
  524. /* convert phys addr in \pte (from r23 or r26) to tlb insert format */
  525. SHRREG \pte,PAGE_SHIFT+PAGE_ADD_SHIFT-5, \pte
  526. depi_safe _PAGE_SIZE_ENCODING_DEFAULT, 31,5, \pte
  527. .endm
  528. /*
  529. * Fault_vectors are architecturally required to be aligned on a 2K
  530. * boundary
  531. */
  532. .section .text.hot
  533. .align 2048
  534. ENTRY(fault_vector_20)
  535. /* First vector is invalid (0) */
  536. .ascii "cows can fly"
  537. .byte 0
  538. .align 32
  539. hpmc 1
  540. def 2
  541. def 3
  542. extint 4
  543. def 5
  544. itlb_20 PARISC_ITLB_TRAP
  545. def 7
  546. def 8
  547. def 9
  548. def 10
  549. def 11
  550. def 12
  551. def 13
  552. def 14
  553. dtlb_20 15
  554. naitlb_20 16
  555. nadtlb_20 17
  556. def 18
  557. def 19
  558. dbit_20 20
  559. def 21
  560. def 22
  561. def 23
  562. def 24
  563. def 25
  564. def 26
  565. def 27
  566. def 28
  567. def 29
  568. def 30
  569. def 31
  570. END(fault_vector_20)
  571. #ifndef CONFIG_64BIT
  572. .align 2048
  573. ENTRY(fault_vector_11)
  574. /* First vector is invalid (0) */
  575. .ascii "cows can fly"
  576. .byte 0
  577. .align 32
  578. hpmc 1
  579. def 2
  580. def 3
  581. extint 4
  582. def 5
  583. itlb_11 PARISC_ITLB_TRAP
  584. def 7
  585. def 8
  586. def 9
  587. def 10
  588. def 11
  589. def 12
  590. def 13
  591. def 14
  592. dtlb_11 15
  593. naitlb_11 16
  594. nadtlb_11 17
  595. def 18
  596. def 19
  597. dbit_11 20
  598. def 21
  599. def 22
  600. def 23
  601. def 24
  602. def 25
  603. def 26
  604. def 27
  605. def 28
  606. def 29
  607. def 30
  608. def 31
  609. END(fault_vector_11)
  610. #endif
  611. /* Fault vector is separately protected and *must* be on its own page */
  612. .align PAGE_SIZE
  613. .import handle_interruption,code
  614. .import do_cpu_irq_mask,code
  615. /*
  616. * Child Returns here
  617. *
  618. * copy_thread moved args into task save area.
  619. */
  620. ENTRY(ret_from_kernel_thread)
  621. /* Call schedule_tail first though */
  622. BL schedule_tail, %r2
  623. nop
  624. mfctl %cr30,%r1 /* task_struct */
  625. LDREG TASK_PT_GR25(%r1), %r26
  626. #ifdef CONFIG_64BIT
  627. LDREG TASK_PT_GR27(%r1), %r27
  628. #endif
  629. LDREG TASK_PT_GR26(%r1), %r1
  630. ble 0(%sr7, %r1)
  631. copy %r31, %r2
  632. b finish_child_return
  633. nop
  634. END(ret_from_kernel_thread)
  635. /*
  636. * struct task_struct *_switch_to(struct task_struct *prev,
  637. * struct task_struct *next)
  638. *
  639. * switch kernel stacks and return prev */
  640. ENTRY_CFI(_switch_to)
  641. STREG %r2, -RP_OFFSET(%r30)
  642. callee_save_float
  643. callee_save
  644. load32 _switch_to_ret, %r2
  645. STREG %r2, TASK_PT_KPC(%r26)
  646. LDREG TASK_PT_KPC(%r25), %r2
  647. STREG %r30, TASK_PT_KSP(%r26)
  648. LDREG TASK_PT_KSP(%r25), %r30
  649. bv %r0(%r2)
  650. mtctl %r25,%cr30
  651. ENTRY(_switch_to_ret)
  652. mtctl %r0, %cr0 /* Needed for single stepping */
  653. callee_rest
  654. callee_rest_float
  655. LDREG -RP_OFFSET(%r30), %r2
  656. bv %r0(%r2)
  657. copy %r26, %r28
  658. ENDPROC_CFI(_switch_to)
  659. /*
  660. * Common rfi return path for interruptions, kernel execve, and
  661. * sys_rt_sigreturn (sometimes). The sys_rt_sigreturn syscall will
  662. * return via this path if the signal was received when the process
  663. * was running; if the process was blocked on a syscall then the
  664. * normal syscall_exit path is used. All syscalls for traced
  665. * proceses exit via intr_restore.
  666. *
  667. * XXX If any syscalls that change a processes space id ever exit
  668. * this way, then we will need to copy %sr3 in to PT_SR[3..7], and
  669. * adjust IASQ[0..1].
  670. *
  671. */
  672. .align PAGE_SIZE
  673. ENTRY_CFI(syscall_exit_rfi)
  674. mfctl %cr30,%r16 /* task_struct */
  675. ldo TASK_REGS(%r16),%r16
  676. /* Force iaoq to userspace, as the user has had access to our current
  677. * context via sigcontext. Also Filter the PSW for the same reason.
  678. */
  679. LDREG PT_IAOQ0(%r16),%r19
  680. depi PRIV_USER,31,2,%r19
  681. STREG %r19,PT_IAOQ0(%r16)
  682. LDREG PT_IAOQ1(%r16),%r19
  683. depi PRIV_USER,31,2,%r19
  684. STREG %r19,PT_IAOQ1(%r16)
  685. LDREG PT_PSW(%r16),%r19
  686. load32 USER_PSW_MASK,%r1
  687. #ifdef CONFIG_64BIT
  688. load32 USER_PSW_HI_MASK,%r20
  689. depd %r20,31,32,%r1
  690. #endif
  691. and %r19,%r1,%r19 /* Mask out bits that user shouldn't play with */
  692. load32 USER_PSW,%r1
  693. or %r19,%r1,%r19 /* Make sure default USER_PSW bits are set */
  694. STREG %r19,PT_PSW(%r16)
  695. /*
  696. * If we aren't being traced, we never saved space registers
  697. * (we don't store them in the sigcontext), so set them
  698. * to "proper" values now (otherwise we'll wind up restoring
  699. * whatever was last stored in the task structure, which might
  700. * be inconsistent if an interrupt occurred while on the gateway
  701. * page). Note that we may be "trashing" values the user put in
  702. * them, but we don't support the user changing them.
  703. */
  704. STREG %r0,PT_SR2(%r16)
  705. mfsp %sr3,%r19
  706. STREG %r19,PT_SR0(%r16)
  707. STREG %r19,PT_SR1(%r16)
  708. STREG %r19,PT_SR3(%r16)
  709. STREG %r19,PT_SR4(%r16)
  710. STREG %r19,PT_SR5(%r16)
  711. STREG %r19,PT_SR6(%r16)
  712. STREG %r19,PT_SR7(%r16)
  713. ENTRY(intr_return)
  714. /* check for reschedule */
  715. mfctl %cr30,%r1
  716. LDREG TASK_TI_FLAGS(%r1),%r19 /* sched.h: TIF_NEED_RESCHED */
  717. bb,<,n %r19,31-TIF_NEED_RESCHED,intr_do_resched /* forward */
  718. .import do_notify_resume,code
  719. intr_check_sig:
  720. /* As above */
  721. mfctl %cr30,%r1
  722. LDREG TASK_TI_FLAGS(%r1),%r19
  723. ldi (_TIF_USER_WORK_MASK & ~_TIF_NEED_RESCHED), %r20
  724. and,COND(<>) %r19, %r20, %r0
  725. b,n intr_restore /* skip past if we've nothing to do */
  726. /* This check is critical to having LWS
  727. * working. The IASQ is zero on the gateway
  728. * page and we cannot deliver any signals until
  729. * we get off the gateway page.
  730. *
  731. * Only do signals if we are returning to user space
  732. */
  733. LDREG PT_IASQ0(%r16), %r20
  734. cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* forward */
  735. LDREG PT_IASQ1(%r16), %r20
  736. cmpib,COND(=),n LINUX_GATEWAY_SPACE, %r20, intr_restore /* forward */
  737. copy %r0, %r25 /* long in_syscall = 0 */
  738. #ifdef CONFIG_64BIT
  739. ldo -16(%r30),%r29 /* Reference param save area */
  740. #endif
  741. /* NOTE: We need to enable interrupts if we have to deliver
  742. * signals. We used to do this earlier but it caused kernel
  743. * stack overflows. */
  744. ssm PSW_SM_I, %r0
  745. BL do_notify_resume,%r2
  746. copy %r16, %r26 /* struct pt_regs *regs */
  747. b,n intr_check_sig
  748. intr_restore:
  749. copy %r16,%r29
  750. ldo PT_FR31(%r29),%r1
  751. rest_fp %r1
  752. rest_general %r29
  753. /* inverse of virt_map */
  754. pcxt_ssm_bug
  755. rsm PSW_SM_QUIET,%r0 /* prepare for rfi */
  756. tophys_r1 %r29
  757. /* Restore space id's and special cr's from PT_REGS
  758. * structure pointed to by r29
  759. */
  760. rest_specials %r29
  761. /* IMPORTANT: rest_stack restores r29 last (we are using it)!
  762. * It also restores r1 and r30.
  763. */
  764. rest_stack
  765. rfi
  766. nop
  767. #ifndef CONFIG_PREEMPTION
  768. # define intr_do_preempt intr_restore
  769. #endif /* !CONFIG_PREEMPTION */
  770. .import schedule,code
  771. intr_do_resched:
  772. /* Only call schedule on return to userspace. If we're returning
  773. * to kernel space, we may schedule if CONFIG_PREEMPTION, otherwise
  774. * we jump back to intr_restore.
  775. */
  776. LDREG PT_IASQ0(%r16), %r20
  777. cmpib,COND(=) 0, %r20, intr_do_preempt
  778. nop
  779. LDREG PT_IASQ1(%r16), %r20
  780. cmpib,COND(=) 0, %r20, intr_do_preempt
  781. nop
  782. /* NOTE: We need to enable interrupts if we schedule. We used
  783. * to do this earlier but it caused kernel stack overflows. */
  784. ssm PSW_SM_I, %r0
  785. #ifdef CONFIG_64BIT
  786. ldo -16(%r30),%r29 /* Reference param save area */
  787. #endif
  788. ldil L%intr_check_sig, %r2
  789. #ifndef CONFIG_64BIT
  790. b schedule
  791. #else
  792. load32 schedule, %r20
  793. bv %r0(%r20)
  794. #endif
  795. ldo R%intr_check_sig(%r2), %r2
  796. /* preempt the current task on returning to kernel
  797. * mode from an interrupt, iff need_resched is set,
  798. * and preempt_count is 0. otherwise, we continue on
  799. * our merry way back to the current running task.
  800. */
  801. #ifdef CONFIG_PREEMPTION
  802. .import preempt_schedule_irq,code
  803. intr_do_preempt:
  804. rsm PSW_SM_I, %r0 /* disable interrupts */
  805. /* current_thread_info()->preempt_count */
  806. mfctl %cr30, %r1
  807. ldw TI_PRE_COUNT(%r1), %r19
  808. cmpib,<> 0, %r19, intr_restore /* if preempt_count > 0 */
  809. nop /* prev insn branched backwards */
  810. /* check if we interrupted a critical path */
  811. LDREG PT_PSW(%r16), %r20
  812. bb,<,n %r20, 31 - PSW_SM_I, intr_restore
  813. nop
  814. /* ssm PSW_SM_I done later in intr_restore */
  815. #ifdef CONFIG_MLONGCALLS
  816. ldil L%intr_restore, %r2
  817. load32 preempt_schedule_irq, %r1
  818. bv %r0(%r1)
  819. ldo R%intr_restore(%r2), %r2
  820. #else
  821. ldil L%intr_restore, %r1
  822. BL preempt_schedule_irq, %r2
  823. ldo R%intr_restore(%r1), %r2
  824. #endif
  825. #endif /* CONFIG_PREEMPTION */
  826. /*
  827. * External interrupts.
  828. */
  829. intr_extint:
  830. cmpib,COND(=),n 0,%r16,1f
  831. get_stack_use_cr30
  832. b,n 2f
  833. 1:
  834. get_stack_use_r30
  835. 2:
  836. save_specials %r29
  837. virt_map
  838. save_general %r29
  839. ldo PT_FR0(%r29), %r24
  840. save_fp %r24
  841. loadgp
  842. copy %r29, %r26 /* arg0 is pt_regs */
  843. copy %r29, %r16 /* save pt_regs */
  844. ldil L%intr_return, %r2
  845. #ifdef CONFIG_64BIT
  846. ldo -16(%r30),%r29 /* Reference param save area */
  847. #endif
  848. b do_cpu_irq_mask
  849. ldo R%intr_return(%r2), %r2 /* return to intr_return, not here */
  850. ENDPROC_CFI(syscall_exit_rfi)
  851. /* Generic interruptions (illegal insn, unaligned, page fault, etc) */
  852. ENTRY_CFI(intr_save) /* for os_hpmc */
  853. mfsp %sr7,%r16
  854. cmpib,COND(=),n 0,%r16,1f
  855. get_stack_use_cr30
  856. b 2f
  857. copy %r8,%r26
  858. 1:
  859. get_stack_use_r30
  860. copy %r8,%r26
  861. 2:
  862. save_specials %r29
  863. /* If this trap is a itlb miss, skip saving/adjusting isr/ior */
  864. cmpib,COND(=),n PARISC_ITLB_TRAP,%r26,skip_save_ior
  865. mfctl %isr, %r16
  866. nop /* serialize mfctl on PA 2.0 to avoid 4 cycle penalty */
  867. mfctl %ior, %r17
  868. #ifdef CONFIG_64BIT
  869. /*
  870. * If the interrupted code was running with W bit off (32 bit),
  871. * clear the b bits (bits 0 & 1) in the ior.
  872. * save_specials left ipsw value in r8 for us to test.
  873. */
  874. extrd,u,*<> %r8,PSW_W_BIT,1,%r0
  875. depdi 0,1,2,%r17
  876. /* adjust isr/ior: get high bits from isr and deposit in ior */
  877. space_adjust %r16,%r17,%r1
  878. #endif
  879. STREG %r16, PT_ISR(%r29)
  880. STREG %r17, PT_IOR(%r29)
  881. #if 0 && defined(CONFIG_64BIT)
  882. /* Revisit when we have 64-bit code above 4Gb */
  883. b,n intr_save2
  884. skip_save_ior:
  885. /* We have a itlb miss, and when executing code above 4 Gb on ILP64, we
  886. * need to adjust iasq/iaoq here in the same way we adjusted isr/ior
  887. * above.
  888. */
  889. extrd,u,* %r8,PSW_W_BIT,1,%r1
  890. cmpib,COND(=),n 1,%r1,intr_save2
  891. LDREG PT_IASQ0(%r29), %r16
  892. LDREG PT_IAOQ0(%r29), %r17
  893. /* adjust iasq/iaoq */
  894. space_adjust %r16,%r17,%r1
  895. STREG %r16, PT_IASQ0(%r29)
  896. STREG %r17, PT_IAOQ0(%r29)
  897. #else
  898. skip_save_ior:
  899. #endif
  900. intr_save2:
  901. virt_map
  902. save_general %r29
  903. ldo PT_FR0(%r29), %r25
  904. save_fp %r25
  905. loadgp
  906. copy %r29, %r25 /* arg1 is pt_regs */
  907. #ifdef CONFIG_64BIT
  908. ldo -16(%r30),%r29 /* Reference param save area */
  909. #endif
  910. ldil L%intr_check_sig, %r2
  911. copy %r25, %r16 /* save pt_regs */
  912. b handle_interruption
  913. ldo R%intr_check_sig(%r2), %r2
  914. ENDPROC_CFI(intr_save)
  915. /*
  916. * Note for all tlb miss handlers:
  917. *
  918. * cr24 contains a pointer to the kernel address space
  919. * page directory.
  920. *
  921. * cr25 contains a pointer to the current user address
  922. * space page directory.
  923. *
  924. * sr3 will contain the space id of the user address space
  925. * of the current running thread while that thread is
  926. * running in the kernel.
  927. */
  928. /*
  929. * register number allocations. Note that these are all
  930. * in the shadowed registers
  931. */
  932. t0 = r1 /* temporary register 0 */
  933. va = r8 /* virtual address for which the trap occurred */
  934. t1 = r9 /* temporary register 1 */
  935. pte = r16 /* pte/phys page # */
  936. prot = r17 /* prot bits */
  937. spc = r24 /* space for which the trap occurred */
  938. ptp = r25 /* page directory/page table pointer */
  939. #ifdef CONFIG_64BIT
  940. dtlb_miss_20w:
  941. space_adjust spc,va,t0
  942. get_pgd spc,ptp
  943. space_check spc,t0,dtlb_fault
  944. L3_ptep ptp,pte,t0,va,dtlb_check_alias_20w
  945. ptl_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20w
  946. update_accessed ptp,pte,t0,t1
  947. make_insert_tlb spc,pte,prot,t1
  948. idtlbt pte,prot
  949. ptl_unlock1 spc,t0
  950. rfir
  951. nop
  952. dtlb_check_alias_20w:
  953. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
  954. idtlbt pte,prot
  955. rfir
  956. nop
  957. nadtlb_miss_20w:
  958. space_adjust spc,va,t0
  959. get_pgd spc,ptp
  960. space_check spc,t0,nadtlb_fault
  961. L3_ptep ptp,pte,t0,va,nadtlb_check_alias_20w
  962. ptl_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20w
  963. update_accessed ptp,pte,t0,t1
  964. make_insert_tlb spc,pte,prot,t1
  965. idtlbt pte,prot
  966. ptl_unlock1 spc,t0
  967. rfir
  968. nop
  969. nadtlb_check_alias_20w:
  970. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
  971. idtlbt pte,prot
  972. rfir
  973. nop
  974. #else
  975. dtlb_miss_11:
  976. get_pgd spc,ptp
  977. space_check spc,t0,dtlb_fault
  978. L2_ptep ptp,pte,t0,va,dtlb_check_alias_11
  979. ptl_lock spc,ptp,pte,t0,t1,dtlb_check_alias_11
  980. update_accessed ptp,pte,t0,t1
  981. make_insert_tlb_11 spc,pte,prot
  982. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  983. mtsp spc,%sr1
  984. idtlba pte,(%sr1,va)
  985. idtlbp prot,(%sr1,va)
  986. mtsp t1, %sr1 /* Restore sr1 */
  987. ptl_unlock1 spc,t0
  988. rfir
  989. nop
  990. dtlb_check_alias_11:
  991. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,11
  992. idtlba pte,(va)
  993. idtlbp prot,(va)
  994. rfir
  995. nop
  996. nadtlb_miss_11:
  997. get_pgd spc,ptp
  998. space_check spc,t0,nadtlb_fault
  999. L2_ptep ptp,pte,t0,va,nadtlb_check_alias_11
  1000. ptl_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_11
  1001. update_accessed ptp,pte,t0,t1
  1002. make_insert_tlb_11 spc,pte,prot
  1003. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  1004. mtsp spc,%sr1
  1005. idtlba pte,(%sr1,va)
  1006. idtlbp prot,(%sr1,va)
  1007. mtsp t1, %sr1 /* Restore sr1 */
  1008. ptl_unlock1 spc,t0
  1009. rfir
  1010. nop
  1011. nadtlb_check_alias_11:
  1012. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,11
  1013. idtlba pte,(va)
  1014. idtlbp prot,(va)
  1015. rfir
  1016. nop
  1017. dtlb_miss_20:
  1018. space_adjust spc,va,t0
  1019. get_pgd spc,ptp
  1020. space_check spc,t0,dtlb_fault
  1021. L2_ptep ptp,pte,t0,va,dtlb_check_alias_20
  1022. ptl_lock spc,ptp,pte,t0,t1,dtlb_check_alias_20
  1023. update_accessed ptp,pte,t0,t1
  1024. make_insert_tlb spc,pte,prot,t1
  1025. f_extend pte,t1
  1026. idtlbt pte,prot
  1027. ptl_unlock1 spc,t0
  1028. rfir
  1029. nop
  1030. dtlb_check_alias_20:
  1031. do_alias spc,t0,t1,va,pte,prot,dtlb_fault,20
  1032. idtlbt pte,prot
  1033. rfir
  1034. nop
  1035. nadtlb_miss_20:
  1036. get_pgd spc,ptp
  1037. space_check spc,t0,nadtlb_fault
  1038. L2_ptep ptp,pte,t0,va,nadtlb_check_alias_20
  1039. ptl_lock spc,ptp,pte,t0,t1,nadtlb_check_alias_20
  1040. update_accessed ptp,pte,t0,t1
  1041. make_insert_tlb spc,pte,prot,t1
  1042. f_extend pte,t1
  1043. idtlbt pte,prot
  1044. ptl_unlock1 spc,t0
  1045. rfir
  1046. nop
  1047. nadtlb_check_alias_20:
  1048. do_alias spc,t0,t1,va,pte,prot,nadtlb_emulate,20
  1049. idtlbt pte,prot
  1050. rfir
  1051. nop
  1052. #endif
  1053. nadtlb_emulate:
  1054. /*
  1055. * Non-access misses can be caused by fdc,fic,pdc,lpa,probe and
  1056. * probei instructions. The kernel no longer faults doing flushes.
  1057. * Use of lpa and probe instructions is rare. Given the issue
  1058. * with shadow registers, we defer everything to the "slow" path.
  1059. */
  1060. b,n nadtlb_fault
  1061. #ifdef CONFIG_64BIT
  1062. itlb_miss_20w:
  1063. /*
  1064. * I miss is a little different, since we allow users to fault
  1065. * on the gateway page which is in the kernel address space.
  1066. */
  1067. space_adjust spc,va,t0
  1068. get_pgd spc,ptp
  1069. space_check spc,t0,itlb_fault
  1070. L3_ptep ptp,pte,t0,va,itlb_fault
  1071. ptl_lock spc,ptp,pte,t0,t1,itlb_fault
  1072. update_accessed ptp,pte,t0,t1
  1073. make_insert_tlb spc,pte,prot,t1
  1074. iitlbt pte,prot
  1075. ptl_unlock1 spc,t0
  1076. rfir
  1077. nop
  1078. naitlb_miss_20w:
  1079. /*
  1080. * I miss is a little different, since we allow users to fault
  1081. * on the gateway page which is in the kernel address space.
  1082. */
  1083. space_adjust spc,va,t0
  1084. get_pgd spc,ptp
  1085. space_check spc,t0,naitlb_fault
  1086. L3_ptep ptp,pte,t0,va,naitlb_check_alias_20w
  1087. ptl_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20w
  1088. update_accessed ptp,pte,t0,t1
  1089. make_insert_tlb spc,pte,prot,t1
  1090. iitlbt pte,prot
  1091. ptl_unlock1 spc,t0
  1092. rfir
  1093. nop
  1094. naitlb_check_alias_20w:
  1095. do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
  1096. iitlbt pte,prot
  1097. rfir
  1098. nop
  1099. #else
  1100. itlb_miss_11:
  1101. get_pgd spc,ptp
  1102. space_check spc,t0,itlb_fault
  1103. L2_ptep ptp,pte,t0,va,itlb_fault
  1104. ptl_lock spc,ptp,pte,t0,t1,itlb_fault
  1105. update_accessed ptp,pte,t0,t1
  1106. make_insert_tlb_11 spc,pte,prot
  1107. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  1108. mtsp spc,%sr1
  1109. iitlba pte,(%sr1,va)
  1110. iitlbp prot,(%sr1,va)
  1111. mtsp t1, %sr1 /* Restore sr1 */
  1112. ptl_unlock1 spc,t0
  1113. rfir
  1114. nop
  1115. naitlb_miss_11:
  1116. get_pgd spc,ptp
  1117. space_check spc,t0,naitlb_fault
  1118. L2_ptep ptp,pte,t0,va,naitlb_check_alias_11
  1119. ptl_lock spc,ptp,pte,t0,t1,naitlb_check_alias_11
  1120. update_accessed ptp,pte,t0,t1
  1121. make_insert_tlb_11 spc,pte,prot
  1122. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  1123. mtsp spc,%sr1
  1124. iitlba pte,(%sr1,va)
  1125. iitlbp prot,(%sr1,va)
  1126. mtsp t1, %sr1 /* Restore sr1 */
  1127. ptl_unlock1 spc,t0
  1128. rfir
  1129. nop
  1130. naitlb_check_alias_11:
  1131. do_alias spc,t0,t1,va,pte,prot,itlb_fault,11
  1132. iitlba pte,(%sr0, va)
  1133. iitlbp prot,(%sr0, va)
  1134. rfir
  1135. nop
  1136. itlb_miss_20:
  1137. get_pgd spc,ptp
  1138. space_check spc,t0,itlb_fault
  1139. L2_ptep ptp,pte,t0,va,itlb_fault
  1140. ptl_lock spc,ptp,pte,t0,t1,itlb_fault
  1141. update_accessed ptp,pte,t0,t1
  1142. make_insert_tlb spc,pte,prot,t1
  1143. f_extend pte,t1
  1144. iitlbt pte,prot
  1145. ptl_unlock1 spc,t0
  1146. rfir
  1147. nop
  1148. naitlb_miss_20:
  1149. get_pgd spc,ptp
  1150. space_check spc,t0,naitlb_fault
  1151. L2_ptep ptp,pte,t0,va,naitlb_check_alias_20
  1152. ptl_lock spc,ptp,pte,t0,t1,naitlb_check_alias_20
  1153. update_accessed ptp,pte,t0,t1
  1154. make_insert_tlb spc,pte,prot,t1
  1155. f_extend pte,t1
  1156. iitlbt pte,prot
  1157. ptl_unlock1 spc,t0
  1158. rfir
  1159. nop
  1160. naitlb_check_alias_20:
  1161. do_alias spc,t0,t1,va,pte,prot,naitlb_fault,20
  1162. iitlbt pte,prot
  1163. rfir
  1164. nop
  1165. #endif
  1166. #ifdef CONFIG_64BIT
  1167. dbit_trap_20w:
  1168. space_adjust spc,va,t0
  1169. get_pgd spc,ptp
  1170. space_check spc,t0,dbit_fault
  1171. L3_ptep ptp,pte,t0,va,dbit_fault
  1172. ptl_lock spc,ptp,pte,t0,t1,dbit_fault
  1173. update_dirty ptp,pte,t1
  1174. make_insert_tlb spc,pte,prot,t1
  1175. idtlbt pte,prot
  1176. ptl_unlock0 spc,t0
  1177. rfir
  1178. nop
  1179. #else
  1180. dbit_trap_11:
  1181. get_pgd spc,ptp
  1182. space_check spc,t0,dbit_fault
  1183. L2_ptep ptp,pte,t0,va,dbit_fault
  1184. ptl_lock spc,ptp,pte,t0,t1,dbit_fault
  1185. update_dirty ptp,pte,t1
  1186. make_insert_tlb_11 spc,pte,prot
  1187. mfsp %sr1,t1 /* Save sr1 so we can use it in tlb inserts */
  1188. mtsp spc,%sr1
  1189. idtlba pte,(%sr1,va)
  1190. idtlbp prot,(%sr1,va)
  1191. mtsp t1, %sr1 /* Restore sr1 */
  1192. ptl_unlock0 spc,t0
  1193. rfir
  1194. nop
  1195. dbit_trap_20:
  1196. get_pgd spc,ptp
  1197. space_check spc,t0,dbit_fault
  1198. L2_ptep ptp,pte,t0,va,dbit_fault
  1199. ptl_lock spc,ptp,pte,t0,t1,dbit_fault
  1200. update_dirty ptp,pte,t1
  1201. make_insert_tlb spc,pte,prot,t1
  1202. f_extend pte,t1
  1203. idtlbt pte,prot
  1204. ptl_unlock0 spc,t0
  1205. rfir
  1206. nop
  1207. #endif
  1208. .import handle_interruption,code
  1209. kernel_bad_space:
  1210. b intr_save
  1211. ldi 31,%r8 /* Use an unused code */
  1212. dbit_fault:
  1213. b intr_save
  1214. ldi 20,%r8
  1215. itlb_fault:
  1216. b intr_save
  1217. ldi PARISC_ITLB_TRAP,%r8
  1218. nadtlb_fault:
  1219. b intr_save
  1220. ldi 17,%r8
  1221. naitlb_fault:
  1222. b intr_save
  1223. ldi 16,%r8
  1224. dtlb_fault:
  1225. b intr_save
  1226. ldi 15,%r8
  1227. /* Register saving semantics for system calls:
  1228. %r1 clobbered by system call macro in userspace
  1229. %r2 saved in PT_REGS by gateway page
  1230. %r3 - %r18 preserved by C code (saved by signal code)
  1231. %r19 - %r20 saved in PT_REGS by gateway page
  1232. %r21 - %r22 non-standard syscall args
  1233. stored in kernel stack by gateway page
  1234. %r23 - %r26 arg3-arg0, saved in PT_REGS by gateway page
  1235. %r27 - %r30 saved in PT_REGS by gateway page
  1236. %r31 syscall return pointer
  1237. */
  1238. /* Floating point registers (FIXME: what do we do with these?)
  1239. %fr0 - %fr3 status/exception, not preserved
  1240. %fr4 - %fr7 arguments
  1241. %fr8 - %fr11 not preserved by C code
  1242. %fr12 - %fr21 preserved by C code
  1243. %fr22 - %fr31 not preserved by C code
  1244. */
  1245. .macro reg_save regs
  1246. STREG %r3, PT_GR3(\regs)
  1247. STREG %r4, PT_GR4(\regs)
  1248. STREG %r5, PT_GR5(\regs)
  1249. STREG %r6, PT_GR6(\regs)
  1250. STREG %r7, PT_GR7(\regs)
  1251. STREG %r8, PT_GR8(\regs)
  1252. STREG %r9, PT_GR9(\regs)
  1253. STREG %r10,PT_GR10(\regs)
  1254. STREG %r11,PT_GR11(\regs)
  1255. STREG %r12,PT_GR12(\regs)
  1256. STREG %r13,PT_GR13(\regs)
  1257. STREG %r14,PT_GR14(\regs)
  1258. STREG %r15,PT_GR15(\regs)
  1259. STREG %r16,PT_GR16(\regs)
  1260. STREG %r17,PT_GR17(\regs)
  1261. STREG %r18,PT_GR18(\regs)
  1262. .endm
  1263. .macro reg_restore regs
  1264. LDREG PT_GR3(\regs), %r3
  1265. LDREG PT_GR4(\regs), %r4
  1266. LDREG PT_GR5(\regs), %r5
  1267. LDREG PT_GR6(\regs), %r6
  1268. LDREG PT_GR7(\regs), %r7
  1269. LDREG PT_GR8(\regs), %r8
  1270. LDREG PT_GR9(\regs), %r9
  1271. LDREG PT_GR10(\regs),%r10
  1272. LDREG PT_GR11(\regs),%r11
  1273. LDREG PT_GR12(\regs),%r12
  1274. LDREG PT_GR13(\regs),%r13
  1275. LDREG PT_GR14(\regs),%r14
  1276. LDREG PT_GR15(\regs),%r15
  1277. LDREG PT_GR16(\regs),%r16
  1278. LDREG PT_GR17(\regs),%r17
  1279. LDREG PT_GR18(\regs),%r18
  1280. .endm
  1281. .macro fork_like name
  1282. ENTRY_CFI(sys_\name\()_wrapper)
  1283. mfctl %cr30,%r1
  1284. ldo TASK_REGS(%r1),%r1
  1285. reg_save %r1
  1286. mfctl %cr27, %r28
  1287. ldil L%sys_\name, %r31
  1288. be R%sys_\name(%sr4,%r31)
  1289. STREG %r28, PT_CR27(%r1)
  1290. ENDPROC_CFI(sys_\name\()_wrapper)
  1291. .endm
  1292. fork_like clone
  1293. fork_like clone3
  1294. fork_like fork
  1295. fork_like vfork
  1296. /* Set the return value for the child */
  1297. ENTRY(child_return)
  1298. BL schedule_tail, %r2
  1299. nop
  1300. finish_child_return:
  1301. mfctl %cr30,%r1
  1302. ldo TASK_REGS(%r1),%r1 /* get pt regs */
  1303. LDREG PT_CR27(%r1), %r3
  1304. mtctl %r3, %cr27
  1305. reg_restore %r1
  1306. b syscall_exit
  1307. copy %r0,%r28
  1308. END(child_return)
  1309. ENTRY_CFI(sys_rt_sigreturn_wrapper)
  1310. mfctl %cr30,%r26
  1311. ldo TASK_REGS(%r26),%r26 /* get pt regs */
  1312. /* Don't save regs, we are going to restore them from sigcontext. */
  1313. STREG %r2, -RP_OFFSET(%r30)
  1314. #ifdef CONFIG_64BIT
  1315. ldo FRAME_SIZE(%r30), %r30
  1316. BL sys_rt_sigreturn,%r2
  1317. ldo -16(%r30),%r29 /* Reference param save area */
  1318. #else
  1319. BL sys_rt_sigreturn,%r2
  1320. ldo FRAME_SIZE(%r30), %r30
  1321. #endif
  1322. ldo -FRAME_SIZE(%r30), %r30
  1323. LDREG -RP_OFFSET(%r30), %r2
  1324. /* FIXME: I think we need to restore a few more things here. */
  1325. mfctl %cr30,%r1
  1326. ldo TASK_REGS(%r1),%r1 /* get pt regs */
  1327. reg_restore %r1
  1328. /* If the signal was received while the process was blocked on a
  1329. * syscall, then r2 will take us to syscall_exit; otherwise r2 will
  1330. * take us to syscall_exit_rfi and on to intr_return.
  1331. */
  1332. bv %r0(%r2)
  1333. LDREG PT_GR28(%r1),%r28 /* reload original r28 for syscall_exit */
  1334. ENDPROC_CFI(sys_rt_sigreturn_wrapper)
  1335. ENTRY(syscall_exit)
  1336. /* NOTE: Not all syscalls exit this way. rt_sigreturn will exit
  1337. * via syscall_exit_rfi if the signal was received while the process
  1338. * was running.
  1339. */
  1340. /* save return value now */
  1341. mfctl %cr30, %r1
  1342. STREG %r28,TASK_PT_GR28(%r1)
  1343. /* Seems to me that dp could be wrong here, if the syscall involved
  1344. * calling a module, and nothing got round to restoring dp on return.
  1345. */
  1346. loadgp
  1347. syscall_check_resched:
  1348. /* check for reschedule */
  1349. mfctl %cr30,%r19
  1350. LDREG TASK_TI_FLAGS(%r19),%r19 /* long */
  1351. bb,<,n %r19, 31-TIF_NEED_RESCHED, syscall_do_resched /* forward */
  1352. .import do_signal,code
  1353. syscall_check_sig:
  1354. mfctl %cr30,%r19
  1355. LDREG TASK_TI_FLAGS(%r19),%r19
  1356. ldi (_TIF_USER_WORK_MASK & ~_TIF_NEED_RESCHED), %r26
  1357. and,COND(<>) %r19, %r26, %r0
  1358. b,n syscall_restore /* skip past if we've nothing to do */
  1359. syscall_do_signal:
  1360. /* Save callee-save registers (for sigcontext).
  1361. * FIXME: After this point the process structure should be
  1362. * consistent with all the relevant state of the process
  1363. * before the syscall. We need to verify this.
  1364. */
  1365. mfctl %cr30,%r1
  1366. ldo TASK_REGS(%r1), %r26 /* struct pt_regs *regs */
  1367. reg_save %r26
  1368. #ifdef CONFIG_64BIT
  1369. ldo -16(%r30),%r29 /* Reference param save area */
  1370. #endif
  1371. BL do_notify_resume,%r2
  1372. ldi 1, %r25 /* long in_syscall = 1 */
  1373. mfctl %cr30,%r1
  1374. ldo TASK_REGS(%r1), %r20 /* reload pt_regs */
  1375. reg_restore %r20
  1376. b,n syscall_check_sig
  1377. syscall_restore:
  1378. mfctl %cr30,%r1
  1379. /* Are we being ptraced? */
  1380. LDREG TASK_TI_FLAGS(%r1),%r19
  1381. ldi _TIF_SINGLESTEP|_TIF_BLOCKSTEP,%r2
  1382. and,COND(=) %r19,%r2,%r0
  1383. b,n syscall_restore_rfi
  1384. ldo TASK_PT_FR31(%r1),%r19 /* reload fpregs */
  1385. rest_fp %r19
  1386. LDREG TASK_PT_SAR(%r1),%r19 /* restore SAR */
  1387. mtsar %r19
  1388. LDREG TASK_PT_GR2(%r1),%r2 /* restore user rp */
  1389. LDREG TASK_PT_GR19(%r1),%r19
  1390. LDREG TASK_PT_GR20(%r1),%r20
  1391. LDREG TASK_PT_GR21(%r1),%r21
  1392. LDREG TASK_PT_GR22(%r1),%r22
  1393. LDREG TASK_PT_GR23(%r1),%r23
  1394. LDREG TASK_PT_GR24(%r1),%r24
  1395. LDREG TASK_PT_GR25(%r1),%r25
  1396. LDREG TASK_PT_GR26(%r1),%r26
  1397. LDREG TASK_PT_GR27(%r1),%r27 /* restore user dp */
  1398. LDREG TASK_PT_GR28(%r1),%r28 /* syscall return value */
  1399. LDREG TASK_PT_GR29(%r1),%r29
  1400. LDREG TASK_PT_GR31(%r1),%r31 /* restore syscall rp */
  1401. /* NOTE: We use rsm/ssm pair to make this operation atomic */
  1402. LDREG TASK_PT_GR30(%r1),%r1 /* Get user sp */
  1403. rsm PSW_SM_I, %r0
  1404. copy %r1,%r30 /* Restore user sp */
  1405. mfsp %sr3,%r1 /* Get user space id */
  1406. mtsp %r1,%sr7 /* Restore sr7 */
  1407. ssm PSW_SM_I, %r0
  1408. /* Set sr2 to zero for userspace syscalls to work. */
  1409. mtsp %r0,%sr2
  1410. mtsp %r1,%sr4 /* Restore sr4 */
  1411. mtsp %r1,%sr5 /* Restore sr5 */
  1412. mtsp %r1,%sr6 /* Restore sr6 */
  1413. depi PRIV_USER,31,2,%r31 /* ensure return to user mode. */
  1414. #ifdef CONFIG_64BIT
  1415. /* decide whether to reset the wide mode bit
  1416. *
  1417. * For a syscall, the W bit is stored in the lowest bit
  1418. * of sp. Extract it and reset W if it is zero */
  1419. extrd,u,*<> %r30,63,1,%r1
  1420. rsm PSW_SM_W, %r0
  1421. /* now reset the lowest bit of sp if it was set */
  1422. xor %r30,%r1,%r30
  1423. #endif
  1424. be,n 0(%sr3,%r31) /* return to user space */
  1425. /* We have to return via an RFI, so that PSW T and R bits can be set
  1426. * appropriately.
  1427. * This sets up pt_regs so we can return via intr_restore, which is not
  1428. * the most efficient way of doing things, but it works.
  1429. */
  1430. syscall_restore_rfi:
  1431. ldo -1(%r0),%r2 /* Set recovery cntr to -1 */
  1432. mtctl %r2,%cr0 /* for immediate trap */
  1433. LDREG TASK_PT_PSW(%r1),%r2 /* Get old PSW */
  1434. ldi 0x0b,%r20 /* Create new PSW */
  1435. depi -1,13,1,%r20 /* C, Q, D, and I bits */
  1436. /* The values of SINGLESTEP_BIT and BLOCKSTEP_BIT are
  1437. * set in thread_info.h and converted to PA bitmap
  1438. * numbers in asm-offsets.c */
  1439. /* if ((%r19.SINGLESTEP_BIT)) { %r20.27=1} */
  1440. extru,= %r19,TIF_SINGLESTEP_PA_BIT,1,%r0
  1441. depi -1,27,1,%r20 /* R bit */
  1442. /* if ((%r19.BLOCKSTEP_BIT)) { %r20.7=1} */
  1443. extru,= %r19,TIF_BLOCKSTEP_PA_BIT,1,%r0
  1444. depi -1,7,1,%r20 /* T bit */
  1445. STREG %r20,TASK_PT_PSW(%r1)
  1446. /* Always store space registers, since sr3 can be changed (e.g. fork) */
  1447. mfsp %sr3,%r25
  1448. STREG %r25,TASK_PT_SR3(%r1)
  1449. STREG %r25,TASK_PT_SR4(%r1)
  1450. STREG %r25,TASK_PT_SR5(%r1)
  1451. STREG %r25,TASK_PT_SR6(%r1)
  1452. STREG %r25,TASK_PT_SR7(%r1)
  1453. STREG %r25,TASK_PT_IASQ0(%r1)
  1454. STREG %r25,TASK_PT_IASQ1(%r1)
  1455. /* XXX W bit??? */
  1456. /* Now if old D bit is clear, it means we didn't save all registers
  1457. * on syscall entry, so do that now. This only happens on TRACEME
  1458. * calls, or if someone attached to us while we were on a syscall.
  1459. * We could make this more efficient by not saving r3-r18, but
  1460. * then we wouldn't be able to use the common intr_restore path.
  1461. * It is only for traced processes anyway, so performance is not
  1462. * an issue.
  1463. */
  1464. bb,< %r2,30,pt_regs_ok /* Branch if D set */
  1465. ldo TASK_REGS(%r1),%r25
  1466. reg_save %r25 /* Save r3 to r18 */
  1467. /* Save the current sr */
  1468. mfsp %sr0,%r2
  1469. STREG %r2,TASK_PT_SR0(%r1)
  1470. /* Save the scratch sr */
  1471. mfsp %sr1,%r2
  1472. STREG %r2,TASK_PT_SR1(%r1)
  1473. /* sr2 should be set to zero for userspace syscalls */
  1474. STREG %r0,TASK_PT_SR2(%r1)
  1475. LDREG TASK_PT_GR31(%r1),%r2
  1476. depi PRIV_USER,31,2,%r2 /* ensure return to user mode. */
  1477. STREG %r2,TASK_PT_IAOQ0(%r1)
  1478. ldo 4(%r2),%r2
  1479. STREG %r2,TASK_PT_IAOQ1(%r1)
  1480. b intr_restore
  1481. copy %r25,%r16
  1482. pt_regs_ok:
  1483. LDREG TASK_PT_IAOQ0(%r1),%r2
  1484. depi PRIV_USER,31,2,%r2 /* ensure return to user mode. */
  1485. STREG %r2,TASK_PT_IAOQ0(%r1)
  1486. LDREG TASK_PT_IAOQ1(%r1),%r2
  1487. depi PRIV_USER,31,2,%r2
  1488. STREG %r2,TASK_PT_IAOQ1(%r1)
  1489. b intr_restore
  1490. copy %r25,%r16
  1491. syscall_do_resched:
  1492. load32 syscall_check_resched,%r2 /* if resched, we start over again */
  1493. load32 schedule,%r19
  1494. bv %r0(%r19) /* jumps to schedule() */
  1495. #ifdef CONFIG_64BIT
  1496. ldo -16(%r30),%r29 /* Reference param save area */
  1497. #else
  1498. nop
  1499. #endif
  1500. END(syscall_exit)
  1501. #ifdef CONFIG_FUNCTION_TRACER
  1502. .import ftrace_function_trampoline,code
  1503. .align L1_CACHE_BYTES
  1504. ENTRY_CFI(mcount, caller)
  1505. _mcount:
  1506. .export _mcount,data
  1507. /*
  1508. * The 64bit mcount() function pointer needs 4 dwords, of which the
  1509. * first two are free. We optimize it here and put 2 instructions for
  1510. * calling mcount(), and 2 instructions for ftrace_stub(). That way we
  1511. * have all on one L1 cacheline.
  1512. */
  1513. ldi 0, %arg3
  1514. b ftrace_function_trampoline
  1515. copy %r3, %arg2 /* caller original %sp */
  1516. ftrace_stub:
  1517. .globl ftrace_stub
  1518. .type ftrace_stub, @function
  1519. #ifdef CONFIG_64BIT
  1520. bve (%rp)
  1521. #else
  1522. bv %r0(%rp)
  1523. #endif
  1524. nop
  1525. #ifdef CONFIG_64BIT
  1526. .dword mcount
  1527. .dword 0 /* code in head.S puts value of global gp here */
  1528. #endif
  1529. ENDPROC_CFI(mcount)
  1530. #ifdef CONFIG_DYNAMIC_FTRACE
  1531. #ifdef CONFIG_64BIT
  1532. #define FTRACE_FRAME_SIZE (2*FRAME_SIZE)
  1533. #else
  1534. #define FTRACE_FRAME_SIZE FRAME_SIZE
  1535. #endif
  1536. ENTRY_CFI(ftrace_caller, caller,frame=FTRACE_FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
  1537. ftrace_caller:
  1538. .global ftrace_caller
  1539. STREG %r3, -FTRACE_FRAME_SIZE+1*REG_SZ(%sp)
  1540. ldo -FTRACE_FRAME_SIZE(%sp), %r3
  1541. STREG %rp, -RP_OFFSET(%r3)
  1542. /* Offset 0 is already allocated for %r1 */
  1543. STREG %r23, 2*REG_SZ(%r3)
  1544. STREG %r24, 3*REG_SZ(%r3)
  1545. STREG %r25, 4*REG_SZ(%r3)
  1546. STREG %r26, 5*REG_SZ(%r3)
  1547. STREG %r28, 6*REG_SZ(%r3)
  1548. STREG %r29, 7*REG_SZ(%r3)
  1549. #ifdef CONFIG_64BIT
  1550. STREG %r19, 8*REG_SZ(%r3)
  1551. STREG %r20, 9*REG_SZ(%r3)
  1552. STREG %r21, 10*REG_SZ(%r3)
  1553. STREG %r22, 11*REG_SZ(%r3)
  1554. STREG %r27, 12*REG_SZ(%r3)
  1555. STREG %r31, 13*REG_SZ(%r3)
  1556. loadgp
  1557. ldo -16(%sp),%r29
  1558. #endif
  1559. LDREG 0(%r3), %r25
  1560. copy %rp, %r26
  1561. ldo -8(%r25), %r25
  1562. ldi 0, %r23 /* no pt_regs */
  1563. b,l ftrace_function_trampoline, %rp
  1564. copy %r3, %r24
  1565. LDREG -RP_OFFSET(%r3), %rp
  1566. LDREG 2*REG_SZ(%r3), %r23
  1567. LDREG 3*REG_SZ(%r3), %r24
  1568. LDREG 4*REG_SZ(%r3), %r25
  1569. LDREG 5*REG_SZ(%r3), %r26
  1570. LDREG 6*REG_SZ(%r3), %r28
  1571. LDREG 7*REG_SZ(%r3), %r29
  1572. #ifdef CONFIG_64BIT
  1573. LDREG 8*REG_SZ(%r3), %r19
  1574. LDREG 9*REG_SZ(%r3), %r20
  1575. LDREG 10*REG_SZ(%r3), %r21
  1576. LDREG 11*REG_SZ(%r3), %r22
  1577. LDREG 12*REG_SZ(%r3), %r27
  1578. LDREG 13*REG_SZ(%r3), %r31
  1579. #endif
  1580. LDREG 1*REG_SZ(%r3), %r3
  1581. LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
  1582. /* Adjust return point to jump back to beginning of traced function */
  1583. ldo -4(%r1), %r1
  1584. bv,n (%r1)
  1585. ENDPROC_CFI(ftrace_caller)
  1586. #ifdef CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS
  1587. ENTRY_CFI(ftrace_regs_caller,caller,frame=FTRACE_FRAME_SIZE+PT_SZ_ALGN,
  1588. CALLS,SAVE_RP,SAVE_SP)
  1589. ftrace_regs_caller:
  1590. .global ftrace_regs_caller
  1591. ldo -FTRACE_FRAME_SIZE(%sp), %r1
  1592. STREG %rp, -RP_OFFSET(%r1)
  1593. copy %sp, %r1
  1594. ldo PT_SZ_ALGN(%sp), %sp
  1595. STREG %rp, PT_GR2(%r1)
  1596. STREG %r3, PT_GR3(%r1)
  1597. STREG %r4, PT_GR4(%r1)
  1598. STREG %r5, PT_GR5(%r1)
  1599. STREG %r6, PT_GR6(%r1)
  1600. STREG %r7, PT_GR7(%r1)
  1601. STREG %r8, PT_GR8(%r1)
  1602. STREG %r9, PT_GR9(%r1)
  1603. STREG %r10, PT_GR10(%r1)
  1604. STREG %r11, PT_GR11(%r1)
  1605. STREG %r12, PT_GR12(%r1)
  1606. STREG %r13, PT_GR13(%r1)
  1607. STREG %r14, PT_GR14(%r1)
  1608. STREG %r15, PT_GR15(%r1)
  1609. STREG %r16, PT_GR16(%r1)
  1610. STREG %r17, PT_GR17(%r1)
  1611. STREG %r18, PT_GR18(%r1)
  1612. STREG %r19, PT_GR19(%r1)
  1613. STREG %r20, PT_GR20(%r1)
  1614. STREG %r21, PT_GR21(%r1)
  1615. STREG %r22, PT_GR22(%r1)
  1616. STREG %r23, PT_GR23(%r1)
  1617. STREG %r24, PT_GR24(%r1)
  1618. STREG %r25, PT_GR25(%r1)
  1619. STREG %r26, PT_GR26(%r1)
  1620. STREG %r27, PT_GR27(%r1)
  1621. STREG %r28, PT_GR28(%r1)
  1622. STREG %r29, PT_GR29(%r1)
  1623. STREG %r30, PT_GR30(%r1)
  1624. STREG %r31, PT_GR31(%r1)
  1625. mfctl %cr11, %r26
  1626. STREG %r26, PT_SAR(%r1)
  1627. copy %rp, %r26
  1628. LDREG -FTRACE_FRAME_SIZE-PT_SZ_ALGN(%sp), %r25
  1629. ldo -8(%r25), %r25
  1630. ldo -FTRACE_FRAME_SIZE(%r1), %arg2
  1631. b,l ftrace_function_trampoline, %rp
  1632. copy %r1, %arg3 /* struct pt_regs */
  1633. ldo -PT_SZ_ALGN(%sp), %r1
  1634. LDREG PT_SAR(%r1), %rp
  1635. mtctl %rp, %cr11
  1636. LDREG PT_GR2(%r1), %rp
  1637. LDREG PT_GR3(%r1), %r3
  1638. LDREG PT_GR4(%r1), %r4
  1639. LDREG PT_GR5(%r1), %r5
  1640. LDREG PT_GR6(%r1), %r6
  1641. LDREG PT_GR7(%r1), %r7
  1642. LDREG PT_GR8(%r1), %r8
  1643. LDREG PT_GR9(%r1), %r9
  1644. LDREG PT_GR10(%r1),%r10
  1645. LDREG PT_GR11(%r1),%r11
  1646. LDREG PT_GR12(%r1),%r12
  1647. LDREG PT_GR13(%r1),%r13
  1648. LDREG PT_GR14(%r1),%r14
  1649. LDREG PT_GR15(%r1),%r15
  1650. LDREG PT_GR16(%r1),%r16
  1651. LDREG PT_GR17(%r1),%r17
  1652. LDREG PT_GR18(%r1),%r18
  1653. LDREG PT_GR19(%r1),%r19
  1654. LDREG PT_GR20(%r1),%r20
  1655. LDREG PT_GR21(%r1),%r21
  1656. LDREG PT_GR22(%r1),%r22
  1657. LDREG PT_GR23(%r1),%r23
  1658. LDREG PT_GR24(%r1),%r24
  1659. LDREG PT_GR25(%r1),%r25
  1660. LDREG PT_GR26(%r1),%r26
  1661. LDREG PT_GR27(%r1),%r27
  1662. LDREG PT_GR28(%r1),%r28
  1663. LDREG PT_GR29(%r1),%r29
  1664. LDREG PT_GR30(%r1),%r30
  1665. LDREG PT_GR31(%r1),%r31
  1666. ldo -PT_SZ_ALGN(%sp), %sp
  1667. LDREGM -FTRACE_FRAME_SIZE(%sp), %r1
  1668. /* Adjust return point to jump back to beginning of traced function */
  1669. ldo -4(%r1), %r1
  1670. bv,n (%r1)
  1671. ENDPROC_CFI(ftrace_regs_caller)
  1672. #endif
  1673. #endif
  1674. #ifdef CONFIG_FUNCTION_GRAPH_TRACER
  1675. .align 8
  1676. ENTRY_CFI(return_to_handler, caller,frame=FRAME_SIZE)
  1677. .export parisc_return_to_handler,data
  1678. parisc_return_to_handler:
  1679. copy %r3,%r1
  1680. STREG %r0,-RP_OFFSET(%sp) /* store 0 as %rp */
  1681. copy %sp,%r3
  1682. STREGM %r1,FRAME_SIZE(%sp)
  1683. STREG %ret0,8(%r3)
  1684. STREG %ret1,16(%r3)
  1685. #ifdef CONFIG_64BIT
  1686. loadgp
  1687. #endif
  1688. /* call ftrace_return_to_handler(0) */
  1689. .import ftrace_return_to_handler,code
  1690. load32 ftrace_return_to_handler,%ret0
  1691. load32 .Lftrace_ret,%r2
  1692. #ifdef CONFIG_64BIT
  1693. ldo -16(%sp),%ret1 /* Reference param save area */
  1694. bve (%ret0)
  1695. #else
  1696. bv %r0(%ret0)
  1697. #endif
  1698. ldi 0,%r26
  1699. .Lftrace_ret:
  1700. copy %ret0,%rp
  1701. /* restore original return values */
  1702. LDREG 8(%r3),%ret0
  1703. LDREG 16(%r3),%ret1
  1704. /* return from function */
  1705. #ifdef CONFIG_64BIT
  1706. bve (%rp)
  1707. #else
  1708. bv %r0(%rp)
  1709. #endif
  1710. LDREGM -FRAME_SIZE(%sp),%r3
  1711. ENDPROC_CFI(return_to_handler)
  1712. #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
  1713. #endif /* CONFIG_FUNCTION_TRACER */
  1714. #ifdef CONFIG_IRQSTACKS
  1715. /* void call_on_stack(unsigned long param1, void *func,
  1716. unsigned long new_stack) */
  1717. ENTRY_CFI(call_on_stack, FRAME=2*FRAME_SIZE,CALLS,SAVE_RP,SAVE_SP)
  1718. ENTRY(_call_on_stack)
  1719. copy %sp, %r1
  1720. /* Regarding the HPPA calling conventions for function pointers,
  1721. we assume the PIC register is not changed across call. For
  1722. CONFIG_64BIT, the argument pointer is left to point at the
  1723. argument region allocated for the call to call_on_stack. */
  1724. /* Switch to new stack. We allocate two frames. */
  1725. ldo 2*FRAME_SIZE(%arg2), %sp
  1726. # ifdef CONFIG_64BIT
  1727. /* Save previous stack pointer and return pointer in frame marker */
  1728. STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
  1729. /* Calls always use function descriptor */
  1730. LDREG 16(%arg1), %arg1
  1731. bve,l (%arg1), %rp
  1732. STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
  1733. LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
  1734. bve (%rp)
  1735. LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
  1736. # else
  1737. /* Save previous stack pointer and return pointer in frame marker */
  1738. STREG %r1, -FRAME_SIZE-REG_SZ(%sp)
  1739. STREG %rp, -FRAME_SIZE-RP_OFFSET(%sp)
  1740. /* Calls use function descriptor if PLABEL bit is set */
  1741. bb,>=,n %arg1, 30, 1f
  1742. depwi 0,31,2, %arg1
  1743. LDREG 0(%arg1), %arg1
  1744. 1:
  1745. be,l 0(%sr4,%arg1), %sr0, %r31
  1746. copy %r31, %rp
  1747. LDREG -FRAME_SIZE-RP_OFFSET(%sp), %rp
  1748. bv (%rp)
  1749. LDREG -FRAME_SIZE-REG_SZ(%sp), %sp
  1750. # endif /* CONFIG_64BIT */
  1751. ENDPROC_CFI(call_on_stack)
  1752. #endif /* CONFIG_IRQSTACKS */
  1753. ENTRY_CFI(get_register)
  1754. /*
  1755. * get_register is used by the non access tlb miss handlers to
  1756. * copy the value of the general register specified in r8 into
  1757. * r1. This routine can't be used for shadowed registers, since
  1758. * the rfir will restore the original value. So, for the shadowed
  1759. * registers we put a -1 into r1 to indicate that the register
  1760. * should not be used (the register being copied could also have
  1761. * a -1 in it, but that is OK, it just means that we will have
  1762. * to use the slow path instead).
  1763. */
  1764. blr %r8,%r0
  1765. nop
  1766. bv %r0(%r25) /* r0 */
  1767. copy %r0,%r1
  1768. bv %r0(%r25) /* r1 - shadowed */
  1769. ldi -1,%r1
  1770. bv %r0(%r25) /* r2 */
  1771. copy %r2,%r1
  1772. bv %r0(%r25) /* r3 */
  1773. copy %r3,%r1
  1774. bv %r0(%r25) /* r4 */
  1775. copy %r4,%r1
  1776. bv %r0(%r25) /* r5 */
  1777. copy %r5,%r1
  1778. bv %r0(%r25) /* r6 */
  1779. copy %r6,%r1
  1780. bv %r0(%r25) /* r7 */
  1781. copy %r7,%r1
  1782. bv %r0(%r25) /* r8 - shadowed */
  1783. ldi -1,%r1
  1784. bv %r0(%r25) /* r9 - shadowed */
  1785. ldi -1,%r1
  1786. bv %r0(%r25) /* r10 */
  1787. copy %r10,%r1
  1788. bv %r0(%r25) /* r11 */
  1789. copy %r11,%r1
  1790. bv %r0(%r25) /* r12 */
  1791. copy %r12,%r1
  1792. bv %r0(%r25) /* r13 */
  1793. copy %r13,%r1
  1794. bv %r0(%r25) /* r14 */
  1795. copy %r14,%r1
  1796. bv %r0(%r25) /* r15 */
  1797. copy %r15,%r1
  1798. bv %r0(%r25) /* r16 - shadowed */
  1799. ldi -1,%r1
  1800. bv %r0(%r25) /* r17 - shadowed */
  1801. ldi -1,%r1
  1802. bv %r0(%r25) /* r18 */
  1803. copy %r18,%r1
  1804. bv %r0(%r25) /* r19 */
  1805. copy %r19,%r1
  1806. bv %r0(%r25) /* r20 */
  1807. copy %r20,%r1
  1808. bv %r0(%r25) /* r21 */
  1809. copy %r21,%r1
  1810. bv %r0(%r25) /* r22 */
  1811. copy %r22,%r1
  1812. bv %r0(%r25) /* r23 */
  1813. copy %r23,%r1
  1814. bv %r0(%r25) /* r24 - shadowed */
  1815. ldi -1,%r1
  1816. bv %r0(%r25) /* r25 - shadowed */
  1817. ldi -1,%r1
  1818. bv %r0(%r25) /* r26 */
  1819. copy %r26,%r1
  1820. bv %r0(%r25) /* r27 */
  1821. copy %r27,%r1
  1822. bv %r0(%r25) /* r28 */
  1823. copy %r28,%r1
  1824. bv %r0(%r25) /* r29 */
  1825. copy %r29,%r1
  1826. bv %r0(%r25) /* r30 */
  1827. copy %r30,%r1
  1828. bv %r0(%r25) /* r31 */
  1829. copy %r31,%r1
  1830. ENDPROC_CFI(get_register)
  1831. ENTRY_CFI(set_register)
  1832. /*
  1833. * set_register is used by the non access tlb miss handlers to
  1834. * copy the value of r1 into the general register specified in
  1835. * r8.
  1836. */
  1837. blr %r8,%r0
  1838. nop
  1839. bv %r0(%r25) /* r0 (silly, but it is a place holder) */
  1840. copy %r1,%r0
  1841. bv %r0(%r25) /* r1 */
  1842. copy %r1,%r1
  1843. bv %r0(%r25) /* r2 */
  1844. copy %r1,%r2
  1845. bv %r0(%r25) /* r3 */
  1846. copy %r1,%r3
  1847. bv %r0(%r25) /* r4 */
  1848. copy %r1,%r4
  1849. bv %r0(%r25) /* r5 */
  1850. copy %r1,%r5
  1851. bv %r0(%r25) /* r6 */
  1852. copy %r1,%r6
  1853. bv %r0(%r25) /* r7 */
  1854. copy %r1,%r7
  1855. bv %r0(%r25) /* r8 */
  1856. copy %r1,%r8
  1857. bv %r0(%r25) /* r9 */
  1858. copy %r1,%r9
  1859. bv %r0(%r25) /* r10 */
  1860. copy %r1,%r10
  1861. bv %r0(%r25) /* r11 */
  1862. copy %r1,%r11
  1863. bv %r0(%r25) /* r12 */
  1864. copy %r1,%r12
  1865. bv %r0(%r25) /* r13 */
  1866. copy %r1,%r13
  1867. bv %r0(%r25) /* r14 */
  1868. copy %r1,%r14
  1869. bv %r0(%r25) /* r15 */
  1870. copy %r1,%r15
  1871. bv %r0(%r25) /* r16 */
  1872. copy %r1,%r16
  1873. bv %r0(%r25) /* r17 */
  1874. copy %r1,%r17
  1875. bv %r0(%r25) /* r18 */
  1876. copy %r1,%r18
  1877. bv %r0(%r25) /* r19 */
  1878. copy %r1,%r19
  1879. bv %r0(%r25) /* r20 */
  1880. copy %r1,%r20
  1881. bv %r0(%r25) /* r21 */
  1882. copy %r1,%r21
  1883. bv %r0(%r25) /* r22 */
  1884. copy %r1,%r22
  1885. bv %r0(%r25) /* r23 */
  1886. copy %r1,%r23
  1887. bv %r0(%r25) /* r24 */
  1888. copy %r1,%r24
  1889. bv %r0(%r25) /* r25 */
  1890. copy %r1,%r25
  1891. bv %r0(%r25) /* r26 */
  1892. copy %r1,%r26
  1893. bv %r0(%r25) /* r27 */
  1894. copy %r1,%r27
  1895. bv %r0(%r25) /* r28 */
  1896. copy %r1,%r28
  1897. bv %r0(%r25) /* r29 */
  1898. copy %r1,%r29
  1899. bv %r0(%r25) /* r30 */
  1900. copy %r1,%r30
  1901. bv %r0(%r25) /* r31 */
  1902. copy %r1,%r31
  1903. ENDPROC_CFI(set_register)