tlb.c 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. */
  5. #include <linux/init.h>
  6. #include <linux/sched.h>
  7. #include <linux/smp.h>
  8. #include <linux/mm.h>
  9. #include <linux/hugetlb.h>
  10. #include <linux/export.h>
  11. #include <asm/cpu.h>
  12. #include <asm/bootinfo.h>
  13. #include <asm/mmu_context.h>
  14. #include <asm/pgtable.h>
  15. #include <asm/tlb.h>
  16. void local_flush_tlb_all(void)
  17. {
  18. invtlb_all(INVTLB_CURRENT_ALL, 0, 0);
  19. }
  20. EXPORT_SYMBOL(local_flush_tlb_all);
  21. void local_flush_tlb_user(void)
  22. {
  23. invtlb_all(INVTLB_CURRENT_GFALSE, 0, 0);
  24. }
  25. EXPORT_SYMBOL(local_flush_tlb_user);
  26. void local_flush_tlb_kernel(void)
  27. {
  28. invtlb_all(INVTLB_CURRENT_GTRUE, 0, 0);
  29. }
  30. EXPORT_SYMBOL(local_flush_tlb_kernel);
  31. /*
  32. * All entries common to a mm share an asid. To effectively flush
  33. * these entries, we just bump the asid.
  34. */
  35. void local_flush_tlb_mm(struct mm_struct *mm)
  36. {
  37. int cpu;
  38. preempt_disable();
  39. cpu = smp_processor_id();
  40. if (asid_valid(mm, cpu))
  41. drop_mmu_context(mm, cpu);
  42. else
  43. cpumask_clear_cpu(cpu, mm_cpumask(mm));
  44. preempt_enable();
  45. }
  46. void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
  47. unsigned long end)
  48. {
  49. struct mm_struct *mm = vma->vm_mm;
  50. int cpu = smp_processor_id();
  51. if (asid_valid(mm, cpu)) {
  52. unsigned long size, flags;
  53. local_irq_save(flags);
  54. start = round_down(start, PAGE_SIZE << 1);
  55. end = round_up(end, PAGE_SIZE << 1);
  56. size = (end - start) >> (PAGE_SHIFT + 1);
  57. if (size <= (current_cpu_data.tlbsizestlbsets ?
  58. current_cpu_data.tlbsize / 8 :
  59. current_cpu_data.tlbsize / 2)) {
  60. int asid = cpu_asid(cpu, mm);
  61. while (start < end) {
  62. invtlb(INVTLB_ADDR_GFALSE_AND_ASID, asid, start);
  63. start += (PAGE_SIZE << 1);
  64. }
  65. } else {
  66. drop_mmu_context(mm, cpu);
  67. }
  68. local_irq_restore(flags);
  69. } else {
  70. cpumask_clear_cpu(cpu, mm_cpumask(mm));
  71. }
  72. }
  73. void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
  74. {
  75. unsigned long size, flags;
  76. local_irq_save(flags);
  77. size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
  78. size = (size + 1) >> 1;
  79. if (size <= (current_cpu_data.tlbsizestlbsets ?
  80. current_cpu_data.tlbsize / 8 :
  81. current_cpu_data.tlbsize / 2)) {
  82. start &= (PAGE_MASK << 1);
  83. end += ((PAGE_SIZE << 1) - 1);
  84. end &= (PAGE_MASK << 1);
  85. while (start < end) {
  86. invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, start);
  87. start += (PAGE_SIZE << 1);
  88. }
  89. } else {
  90. local_flush_tlb_kernel();
  91. }
  92. local_irq_restore(flags);
  93. }
  94. void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
  95. {
  96. int cpu = smp_processor_id();
  97. if (asid_valid(vma->vm_mm, cpu)) {
  98. int newpid;
  99. newpid = cpu_asid(cpu, vma->vm_mm);
  100. page &= (PAGE_MASK << 1);
  101. invtlb(INVTLB_ADDR_GFALSE_AND_ASID, newpid, page);
  102. } else {
  103. cpumask_clear_cpu(cpu, mm_cpumask(vma->vm_mm));
  104. }
  105. }
  106. /*
  107. * This one is only used for pages with the global bit set so we don't care
  108. * much about the ASID.
  109. */
  110. void local_flush_tlb_one(unsigned long page)
  111. {
  112. page &= (PAGE_MASK << 1);
  113. invtlb_addr(INVTLB_ADDR_GTRUE_OR_ASID, 0, page);
  114. }
  115. static void __update_hugetlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  116. {
  117. #ifdef CONFIG_HUGETLB_PAGE
  118. int idx;
  119. unsigned long lo;
  120. unsigned long flags;
  121. local_irq_save(flags);
  122. address &= (PAGE_MASK << 1);
  123. write_csr_entryhi(address);
  124. tlb_probe();
  125. idx = read_csr_tlbidx();
  126. write_csr_pagesize(PS_HUGE_SIZE);
  127. lo = pmd_to_entrylo(pte_val(*ptep));
  128. write_csr_entrylo0(lo);
  129. write_csr_entrylo1(lo + (HPAGE_SIZE >> 1));
  130. if (idx < 0)
  131. tlb_write_random();
  132. else
  133. tlb_write_indexed();
  134. write_csr_pagesize(PS_DEFAULT_SIZE);
  135. local_irq_restore(flags);
  136. #endif
  137. }
  138. void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
  139. {
  140. int idx;
  141. unsigned long flags;
  142. /*
  143. * Handle debugger faulting in for debugee.
  144. */
  145. if (current->active_mm != vma->vm_mm)
  146. return;
  147. if (pte_val(*ptep) & _PAGE_HUGE) {
  148. __update_hugetlb(vma, address, ptep);
  149. return;
  150. }
  151. local_irq_save(flags);
  152. if ((unsigned long)ptep & sizeof(pte_t))
  153. ptep--;
  154. address &= (PAGE_MASK << 1);
  155. write_csr_entryhi(address);
  156. tlb_probe();
  157. idx = read_csr_tlbidx();
  158. write_csr_pagesize(PS_DEFAULT_SIZE);
  159. write_csr_entrylo0(pte_val(*ptep++));
  160. write_csr_entrylo1(pte_val(*ptep));
  161. if (idx < 0)
  162. tlb_write_random();
  163. else
  164. tlb_write_indexed();
  165. local_irq_restore(flags);
  166. }
  167. static void setup_ptwalker(void)
  168. {
  169. unsigned long pwctl0, pwctl1;
  170. unsigned long pgd_i = 0, pgd_w = 0;
  171. unsigned long pud_i = 0, pud_w = 0;
  172. unsigned long pmd_i = 0, pmd_w = 0;
  173. unsigned long pte_i = 0, pte_w = 0;
  174. pgd_i = PGDIR_SHIFT;
  175. pgd_w = PAGE_SHIFT - 3;
  176. #if CONFIG_PGTABLE_LEVELS > 3
  177. pud_i = PUD_SHIFT;
  178. pud_w = PAGE_SHIFT - 3;
  179. #endif
  180. #if CONFIG_PGTABLE_LEVELS > 2
  181. pmd_i = PMD_SHIFT;
  182. pmd_w = PAGE_SHIFT - 3;
  183. #endif
  184. pte_i = PAGE_SHIFT;
  185. pte_w = PAGE_SHIFT - 3;
  186. pwctl0 = pte_i | pte_w << 5 | pmd_i << 10 | pmd_w << 15 | pud_i << 20 | pud_w << 25;
  187. pwctl1 = pgd_i | pgd_w << 6;
  188. csr_write64(pwctl0, LOONGARCH_CSR_PWCTL0);
  189. csr_write64(pwctl1, LOONGARCH_CSR_PWCTL1);
  190. csr_write64((long)swapper_pg_dir, LOONGARCH_CSR_PGDH);
  191. csr_write64((long)invalid_pg_dir, LOONGARCH_CSR_PGDL);
  192. csr_write64((long)smp_processor_id(), LOONGARCH_CSR_TMID);
  193. }
  194. static void output_pgtable_bits_defines(void)
  195. {
  196. #define pr_define(fmt, ...) \
  197. pr_debug("#define " fmt, ##__VA_ARGS__)
  198. pr_debug("#include <asm/asm.h>\n");
  199. pr_debug("#include <asm/regdef.h>\n");
  200. pr_debug("\n");
  201. pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT);
  202. pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT);
  203. pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT);
  204. pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT);
  205. pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT);
  206. pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT);
  207. pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT);
  208. pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT);
  209. pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT);
  210. pr_debug("\n");
  211. }
  212. #ifdef CONFIG_NUMA
  213. static unsigned long pcpu_handlers[NR_CPUS];
  214. #endif
  215. extern long exception_handlers[VECSIZE * 128 / sizeof(long)];
  216. void setup_tlb_handler(int cpu)
  217. {
  218. setup_ptwalker();
  219. local_flush_tlb_all();
  220. /* The tlb handlers are generated only once */
  221. if (cpu == 0) {
  222. memcpy((void *)tlbrentry, handle_tlb_refill, 0x80);
  223. local_flush_icache_range(tlbrentry, tlbrentry + 0x80);
  224. set_handler(EXCCODE_TLBI * VECSIZE, handle_tlb_load, VECSIZE);
  225. set_handler(EXCCODE_TLBL * VECSIZE, handle_tlb_load, VECSIZE);
  226. set_handler(EXCCODE_TLBS * VECSIZE, handle_tlb_store, VECSIZE);
  227. set_handler(EXCCODE_TLBM * VECSIZE, handle_tlb_modify, VECSIZE);
  228. set_handler(EXCCODE_TLBNR * VECSIZE, handle_tlb_protect, VECSIZE);
  229. set_handler(EXCCODE_TLBNX * VECSIZE, handle_tlb_protect, VECSIZE);
  230. set_handler(EXCCODE_TLBPE * VECSIZE, handle_tlb_protect, VECSIZE);
  231. }
  232. #ifdef CONFIG_NUMA
  233. else {
  234. void *addr;
  235. struct page *page;
  236. const int vec_sz = sizeof(exception_handlers);
  237. if (pcpu_handlers[cpu])
  238. return;
  239. page = alloc_pages_node(cpu_to_node(cpu), GFP_ATOMIC, get_order(vec_sz));
  240. if (!page)
  241. return;
  242. addr = page_address(page);
  243. pcpu_handlers[cpu] = (unsigned long)addr;
  244. memcpy((void *)addr, (void *)eentry, vec_sz);
  245. local_flush_icache_range((unsigned long)addr, (unsigned long)addr + vec_sz);
  246. csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_EENTRY);
  247. csr_write64(pcpu_handlers[cpu], LOONGARCH_CSR_MERRENTRY);
  248. csr_write64(pcpu_handlers[cpu] + 80*VECSIZE, LOONGARCH_CSR_TLBRENTRY);
  249. }
  250. #endif
  251. }
  252. void tlb_init(int cpu)
  253. {
  254. write_csr_pagesize(PS_DEFAULT_SIZE);
  255. write_csr_stlbpgsize(PS_DEFAULT_SIZE);
  256. write_csr_tlbrefill_pagesize(PS_DEFAULT_SIZE);
  257. setup_tlb_handler(cpu);
  258. output_pgtable_bits_defines();
  259. }