math.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/module.h>
  3. #include <linux/types.h>
  4. #include <linux/kernel.h>
  5. #include <linux/sched.h>
  6. #include <asm/ptrace.h>
  7. #include <linux/uaccess.h>
  8. #include "sfp-util.h"
  9. #include <math-emu/soft-fp.h>
  10. #include <math-emu/single.h>
  11. #include <math-emu/double.h>
  12. #define OPC_PAL 0x00
  13. #define OPC_INTA 0x10
  14. #define OPC_INTL 0x11
  15. #define OPC_INTS 0x12
  16. #define OPC_INTM 0x13
  17. #define OPC_FLTC 0x14
  18. #define OPC_FLTV 0x15
  19. #define OPC_FLTI 0x16
  20. #define OPC_FLTL 0x17
  21. #define OPC_MISC 0x18
  22. #define OPC_JSR 0x1a
  23. #define FOP_SRC_S 0
  24. #define FOP_SRC_T 2
  25. #define FOP_SRC_Q 3
  26. #define FOP_FNC_ADDx 0
  27. #define FOP_FNC_CVTQL 0
  28. #define FOP_FNC_SUBx 1
  29. #define FOP_FNC_MULx 2
  30. #define FOP_FNC_DIVx 3
  31. #define FOP_FNC_CMPxUN 4
  32. #define FOP_FNC_CMPxEQ 5
  33. #define FOP_FNC_CMPxLT 6
  34. #define FOP_FNC_CMPxLE 7
  35. #define FOP_FNC_SQRTx 11
  36. #define FOP_FNC_CVTxS 12
  37. #define FOP_FNC_CVTxT 14
  38. #define FOP_FNC_CVTxQ 15
  39. #define MISC_TRAPB 0x0000
  40. #define MISC_EXCB 0x0400
  41. extern unsigned long alpha_read_fp_reg (unsigned long reg);
  42. extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
  43. extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
  44. extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
  45. #ifdef MODULE
  46. MODULE_DESCRIPTION("FP Software completion module");
  47. MODULE_LICENSE("GPL v2");
  48. extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
  49. extern long (*alpha_fp_emul) (unsigned long pc);
  50. static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
  51. static long (*save_emul) (unsigned long pc);
  52. long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
  53. long do_alpha_fp_emul(unsigned long);
  54. static int alpha_fp_emul_init_module(void)
  55. {
  56. save_emul_imprecise = alpha_fp_emul_imprecise;
  57. save_emul = alpha_fp_emul;
  58. alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
  59. alpha_fp_emul = do_alpha_fp_emul;
  60. return 0;
  61. }
  62. module_init(alpha_fp_emul_init_module);
  63. static void alpha_fp_emul_cleanup_module(void)
  64. {
  65. alpha_fp_emul_imprecise = save_emul_imprecise;
  66. alpha_fp_emul = save_emul;
  67. }
  68. module_exit(alpha_fp_emul_cleanup_module);
  69. #undef alpha_fp_emul_imprecise
  70. #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
  71. #undef alpha_fp_emul
  72. #define alpha_fp_emul do_alpha_fp_emul
  73. #endif /* MODULE */
  74. /*
  75. * Emulate the floating point instruction at address PC. Returns -1 if the
  76. * instruction to be emulated is illegal (such as with the opDEC trap), else
  77. * the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
  78. *
  79. * Notice that the kernel does not and cannot use FP regs. This is good
  80. * because it means that instead of saving/restoring all fp regs, we simply
  81. * stick the result of the operation into the appropriate register.
  82. */
  83. long
  84. alpha_fp_emul (unsigned long pc)
  85. {
  86. FP_DECL_EX;
  87. FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
  88. FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
  89. unsigned long fa, fb, fc, func, mode, src;
  90. unsigned long res, va, vb, vc, swcr, fpcr;
  91. __u32 insn;
  92. long si_code;
  93. get_user(insn, (__u32 __user *)pc);
  94. fc = (insn >> 0) & 0x1f; /* destination register */
  95. fb = (insn >> 16) & 0x1f;
  96. fa = (insn >> 21) & 0x1f;
  97. func = (insn >> 5) & 0xf;
  98. src = (insn >> 9) & 0x3;
  99. mode = (insn >> 11) & 0x3;
  100. fpcr = rdfpcr();
  101. swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr);
  102. if (mode == 3) {
  103. /* Dynamic -- get rounding mode from fpcr. */
  104. mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
  105. }
  106. switch (src) {
  107. case FOP_SRC_S:
  108. va = alpha_read_fp_reg_s(fa);
  109. vb = alpha_read_fp_reg_s(fb);
  110. FP_UNPACK_SP(SA, &va);
  111. FP_UNPACK_SP(SB, &vb);
  112. switch (func) {
  113. case FOP_FNC_SUBx:
  114. FP_SUB_S(SR, SA, SB);
  115. goto pack_s;
  116. case FOP_FNC_ADDx:
  117. FP_ADD_S(SR, SA, SB);
  118. goto pack_s;
  119. case FOP_FNC_MULx:
  120. FP_MUL_S(SR, SA, SB);
  121. goto pack_s;
  122. case FOP_FNC_DIVx:
  123. FP_DIV_S(SR, SA, SB);
  124. goto pack_s;
  125. case FOP_FNC_SQRTx:
  126. FP_SQRT_S(SR, SB);
  127. goto pack_s;
  128. }
  129. goto bad_insn;
  130. case FOP_SRC_T:
  131. va = alpha_read_fp_reg(fa);
  132. vb = alpha_read_fp_reg(fb);
  133. if ((func & ~3) == FOP_FNC_CMPxUN) {
  134. FP_UNPACK_RAW_DP(DA, &va);
  135. FP_UNPACK_RAW_DP(DB, &vb);
  136. if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
  137. FP_SET_EXCEPTION(FP_EX_DENORM);
  138. if (FP_DENORM_ZERO)
  139. _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
  140. }
  141. if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
  142. FP_SET_EXCEPTION(FP_EX_DENORM);
  143. if (FP_DENORM_ZERO)
  144. _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
  145. }
  146. FP_CMP_D(res, DA, DB, 3);
  147. vc = 0x4000000000000000UL;
  148. /* CMPTEQ, CMPTUN don't trap on QNaN,
  149. while CMPTLT and CMPTLE do */
  150. if (res == 3
  151. && ((func & 3) >= 2
  152. || FP_ISSIGNAN_D(DA)
  153. || FP_ISSIGNAN_D(DB))) {
  154. FP_SET_EXCEPTION(FP_EX_INVALID);
  155. }
  156. switch (func) {
  157. case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
  158. case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
  159. case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
  160. case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
  161. }
  162. goto done_d;
  163. }
  164. FP_UNPACK_DP(DA, &va);
  165. FP_UNPACK_DP(DB, &vb);
  166. switch (func) {
  167. case FOP_FNC_SUBx:
  168. FP_SUB_D(DR, DA, DB);
  169. goto pack_d;
  170. case FOP_FNC_ADDx:
  171. FP_ADD_D(DR, DA, DB);
  172. goto pack_d;
  173. case FOP_FNC_MULx:
  174. FP_MUL_D(DR, DA, DB);
  175. goto pack_d;
  176. case FOP_FNC_DIVx:
  177. FP_DIV_D(DR, DA, DB);
  178. goto pack_d;
  179. case FOP_FNC_SQRTx:
  180. FP_SQRT_D(DR, DB);
  181. goto pack_d;
  182. case FOP_FNC_CVTxS:
  183. /* It is irritating that DEC encoded CVTST with
  184. SRC == T_floating. It is also interesting that
  185. the bit used to tell the two apart is /U... */
  186. if (insn & 0x2000) {
  187. FP_CONV(S,D,1,1,SR,DB);
  188. goto pack_s;
  189. } else {
  190. vb = alpha_read_fp_reg_s(fb);
  191. FP_UNPACK_SP(SB, &vb);
  192. DR_c = DB_c;
  193. DR_s = DB_s;
  194. DR_e = DB_e + (1024 - 128);
  195. DR_f = SB_f << (52 - 23);
  196. goto pack_d;
  197. }
  198. case FOP_FNC_CVTxQ:
  199. if (DB_c == FP_CLS_NAN
  200. && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
  201. /* AAHB Table B-2 says QNaN should not trigger INV */
  202. vc = 0;
  203. } else
  204. FP_TO_INT_ROUND_D(vc, DB, 64, 2);
  205. goto done_d;
  206. }
  207. goto bad_insn;
  208. case FOP_SRC_Q:
  209. vb = alpha_read_fp_reg(fb);
  210. switch (func) {
  211. case FOP_FNC_CVTQL:
  212. /* Notice: We can get here only due to an integer
  213. overflow. Such overflows are reported as invalid
  214. ops. We return the result the hw would have
  215. computed. */
  216. vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
  217. (vb & 0x3fffffff) << 29); /* rest of the int */
  218. FP_SET_EXCEPTION (FP_EX_INVALID);
  219. goto done_d;
  220. case FOP_FNC_CVTxS:
  221. FP_FROM_INT_S(SR, ((long)vb), 64, long);
  222. goto pack_s;
  223. case FOP_FNC_CVTxT:
  224. FP_FROM_INT_D(DR, ((long)vb), 64, long);
  225. goto pack_d;
  226. }
  227. goto bad_insn;
  228. }
  229. goto bad_insn;
  230. pack_s:
  231. FP_PACK_SP(&vc, SR);
  232. if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
  233. vc = 0;
  234. alpha_write_fp_reg_s(fc, vc);
  235. goto done;
  236. pack_d:
  237. FP_PACK_DP(&vc, DR);
  238. if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
  239. vc = 0;
  240. done_d:
  241. alpha_write_fp_reg(fc, vc);
  242. goto done;
  243. /*
  244. * Take the appropriate action for each possible
  245. * floating-point result:
  246. *
  247. * - Set the appropriate bits in the FPCR
  248. * - If the specified exception is enabled in the FPCR,
  249. * return. The caller (entArith) will dispatch
  250. * the appropriate signal to the translated program.
  251. *
  252. * In addition, properly track the exception state in software
  253. * as described in the Alpha Architecture Handbook section 4.7.7.3.
  254. */
  255. done:
  256. if (_fex) {
  257. /* Record exceptions in software control word. */
  258. swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
  259. current_thread_info()->ieee_state
  260. |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
  261. /* Update hardware control register. */
  262. fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
  263. fpcr |= ieee_swcr_to_fpcr(swcr);
  264. wrfpcr(fpcr);
  265. /* Do we generate a signal? */
  266. _fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK;
  267. si_code = 0;
  268. if (_fex) {
  269. if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND;
  270. if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES;
  271. if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND;
  272. if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF;
  273. if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV;
  274. if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
  275. }
  276. return si_code;
  277. }
  278. /* We used to write the destination register here, but DEC FORTRAN
  279. requires that the result *always* be written... so we do the write
  280. immediately after the operations above. */
  281. return 0;
  282. bad_insn:
  283. printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
  284. insn, pc);
  285. return -1;
  286. }
  287. long
  288. alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
  289. {
  290. unsigned long trigger_pc = regs->pc - 4;
  291. unsigned long insn, opcode, rc, si_code = 0;
  292. /*
  293. * Turn off the bits corresponding to registers that are the
  294. * target of instructions that set bits in the exception
  295. * summary register. We have some slack doing this because a
  296. * register that is the target of a trapping instruction can
  297. * be written at most once in the trap shadow.
  298. *
  299. * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
  300. * bound the trap shadow, so we need not look any further than
  301. * up to the first occurrence of such an instruction.
  302. */
  303. while (write_mask) {
  304. get_user(insn, (__u32 __user *)(trigger_pc));
  305. opcode = insn >> 26;
  306. rc = insn & 0x1f;
  307. switch (opcode) {
  308. case OPC_PAL:
  309. case OPC_JSR:
  310. case 0x30 ... 0x3f: /* branches */
  311. goto egress;
  312. case OPC_MISC:
  313. switch (insn & 0xffff) {
  314. case MISC_TRAPB:
  315. case MISC_EXCB:
  316. goto egress;
  317. default:
  318. break;
  319. }
  320. break;
  321. case OPC_INTA:
  322. case OPC_INTL:
  323. case OPC_INTS:
  324. case OPC_INTM:
  325. write_mask &= ~(1UL << rc);
  326. break;
  327. case OPC_FLTC:
  328. case OPC_FLTV:
  329. case OPC_FLTI:
  330. case OPC_FLTL:
  331. write_mask &= ~(1UL << (rc + 32));
  332. break;
  333. }
  334. if (!write_mask) {
  335. /* Re-execute insns in the trap-shadow. */
  336. regs->pc = trigger_pc + 4;
  337. si_code = alpha_fp_emul(trigger_pc);
  338. goto egress;
  339. }
  340. trigger_pc -= 4;
  341. }
  342. egress:
  343. return si_code;
  344. }