time.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/alpha/kernel/time.c
  4. *
  5. * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
  6. *
  7. * This file contains the clocksource time handling.
  8. * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
  9. * "A Kernel Model for Precision Timekeeping" by Dave Mills
  10. * 1997-01-09 Adrian Sun
  11. * use interval timer if CONFIG_RTC=y
  12. * 1997-10-29 John Bowman ([email protected])
  13. * fixed tick loss calculation in timer_interrupt
  14. * (round system clock to nearest tick instead of truncating)
  15. * fixed algorithm in time_init for getting time from CMOS clock
  16. * 1999-04-16 Thorsten Kranzkowski ([email protected])
  17. * fixed algorithm in do_gettimeofday() for calculating the precise time
  18. * from processor cycle counter (now taking lost_ticks into account)
  19. * 2003-06-03 R. Scott Bailey <[email protected]>
  20. * Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
  21. */
  22. #include <linux/errno.h>
  23. #include <linux/module.h>
  24. #include <linux/sched.h>
  25. #include <linux/kernel.h>
  26. #include <linux/param.h>
  27. #include <linux/string.h>
  28. #include <linux/mm.h>
  29. #include <linux/delay.h>
  30. #include <linux/ioport.h>
  31. #include <linux/irq.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/init.h>
  34. #include <linux/bcd.h>
  35. #include <linux/profile.h>
  36. #include <linux/irq_work.h>
  37. #include <linux/uaccess.h>
  38. #include <asm/io.h>
  39. #include <asm/hwrpb.h>
  40. #include <linux/mc146818rtc.h>
  41. #include <linux/time.h>
  42. #include <linux/timex.h>
  43. #include <linux/clocksource.h>
  44. #include <linux/clockchips.h>
  45. #include "proto.h"
  46. #include "irq_impl.h"
  47. DEFINE_SPINLOCK(rtc_lock);
  48. EXPORT_SYMBOL(rtc_lock);
  49. unsigned long est_cycle_freq;
  50. #ifdef CONFIG_IRQ_WORK
  51. DEFINE_PER_CPU(u8, irq_work_pending);
  52. #define set_irq_work_pending_flag() __this_cpu_write(irq_work_pending, 1)
  53. #define test_irq_work_pending() __this_cpu_read(irq_work_pending)
  54. #define clear_irq_work_pending() __this_cpu_write(irq_work_pending, 0)
  55. void arch_irq_work_raise(void)
  56. {
  57. set_irq_work_pending_flag();
  58. }
  59. #else /* CONFIG_IRQ_WORK */
  60. #define test_irq_work_pending() 0
  61. #define clear_irq_work_pending()
  62. #endif /* CONFIG_IRQ_WORK */
  63. static inline __u32 rpcc(void)
  64. {
  65. return __builtin_alpha_rpcc();
  66. }
  67. /*
  68. * The RTC as a clock_event_device primitive.
  69. */
  70. static DEFINE_PER_CPU(struct clock_event_device, cpu_ce);
  71. irqreturn_t
  72. rtc_timer_interrupt(int irq, void *dev)
  73. {
  74. int cpu = smp_processor_id();
  75. struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
  76. /* Don't run the hook for UNUSED or SHUTDOWN. */
  77. if (likely(clockevent_state_periodic(ce)))
  78. ce->event_handler(ce);
  79. if (test_irq_work_pending()) {
  80. clear_irq_work_pending();
  81. irq_work_run();
  82. }
  83. return IRQ_HANDLED;
  84. }
  85. static int
  86. rtc_ce_set_next_event(unsigned long evt, struct clock_event_device *ce)
  87. {
  88. /* This hook is for oneshot mode, which we don't support. */
  89. return -EINVAL;
  90. }
  91. static void __init
  92. init_rtc_clockevent(void)
  93. {
  94. int cpu = smp_processor_id();
  95. struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
  96. *ce = (struct clock_event_device){
  97. .name = "rtc",
  98. .features = CLOCK_EVT_FEAT_PERIODIC,
  99. .rating = 100,
  100. .cpumask = cpumask_of(cpu),
  101. .set_next_event = rtc_ce_set_next_event,
  102. };
  103. clockevents_config_and_register(ce, CONFIG_HZ, 0, 0);
  104. }
  105. /*
  106. * The QEMU clock as a clocksource primitive.
  107. */
  108. static u64
  109. qemu_cs_read(struct clocksource *cs)
  110. {
  111. return qemu_get_vmtime();
  112. }
  113. static struct clocksource qemu_cs = {
  114. .name = "qemu",
  115. .rating = 400,
  116. .read = qemu_cs_read,
  117. .mask = CLOCKSOURCE_MASK(64),
  118. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  119. .max_idle_ns = LONG_MAX
  120. };
  121. /*
  122. * The QEMU alarm as a clock_event_device primitive.
  123. */
  124. static int qemu_ce_shutdown(struct clock_event_device *ce)
  125. {
  126. /* The mode member of CE is updated for us in generic code.
  127. Just make sure that the event is disabled. */
  128. qemu_set_alarm_abs(0);
  129. return 0;
  130. }
  131. static int
  132. qemu_ce_set_next_event(unsigned long evt, struct clock_event_device *ce)
  133. {
  134. qemu_set_alarm_rel(evt);
  135. return 0;
  136. }
  137. static irqreturn_t
  138. qemu_timer_interrupt(int irq, void *dev)
  139. {
  140. int cpu = smp_processor_id();
  141. struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
  142. ce->event_handler(ce);
  143. return IRQ_HANDLED;
  144. }
  145. static void __init
  146. init_qemu_clockevent(void)
  147. {
  148. int cpu = smp_processor_id();
  149. struct clock_event_device *ce = &per_cpu(cpu_ce, cpu);
  150. *ce = (struct clock_event_device){
  151. .name = "qemu",
  152. .features = CLOCK_EVT_FEAT_ONESHOT,
  153. .rating = 400,
  154. .cpumask = cpumask_of(cpu),
  155. .set_state_shutdown = qemu_ce_shutdown,
  156. .set_state_oneshot = qemu_ce_shutdown,
  157. .tick_resume = qemu_ce_shutdown,
  158. .set_next_event = qemu_ce_set_next_event,
  159. };
  160. clockevents_config_and_register(ce, NSEC_PER_SEC, 1000, LONG_MAX);
  161. }
  162. void __init
  163. common_init_rtc(void)
  164. {
  165. unsigned char x, sel = 0;
  166. /* Reset periodic interrupt frequency. */
  167. #if CONFIG_HZ == 1024 || CONFIG_HZ == 1200
  168. x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
  169. /* Test includes known working values on various platforms
  170. where 0x26 is wrong; we refuse to change those. */
  171. if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
  172. sel = RTC_REF_CLCK_32KHZ + 6;
  173. }
  174. #elif CONFIG_HZ == 256 || CONFIG_HZ == 128 || CONFIG_HZ == 64 || CONFIG_HZ == 32
  175. sel = RTC_REF_CLCK_32KHZ + __builtin_ffs(32768 / CONFIG_HZ);
  176. #else
  177. # error "Unknown HZ from arch/alpha/Kconfig"
  178. #endif
  179. if (sel) {
  180. printk(KERN_INFO "Setting RTC_FREQ to %d Hz (%x)\n",
  181. CONFIG_HZ, sel);
  182. CMOS_WRITE(sel, RTC_FREQ_SELECT);
  183. }
  184. /* Turn on periodic interrupts. */
  185. x = CMOS_READ(RTC_CONTROL);
  186. if (!(x & RTC_PIE)) {
  187. printk("Turning on RTC interrupts.\n");
  188. x |= RTC_PIE;
  189. x &= ~(RTC_AIE | RTC_UIE);
  190. CMOS_WRITE(x, RTC_CONTROL);
  191. }
  192. (void) CMOS_READ(RTC_INTR_FLAGS);
  193. outb(0x36, 0x43); /* pit counter 0: system timer */
  194. outb(0x00, 0x40);
  195. outb(0x00, 0x40);
  196. outb(0xb6, 0x43); /* pit counter 2: speaker */
  197. outb(0x31, 0x42);
  198. outb(0x13, 0x42);
  199. init_rtc_irq(NULL);
  200. }
  201. #ifndef CONFIG_ALPHA_WTINT
  202. /*
  203. * The RPCC as a clocksource primitive.
  204. *
  205. * While we have free-running timecounters running on all CPUs, and we make
  206. * a half-hearted attempt in init_rtc_rpcc_info to sync the timecounter
  207. * with the wall clock, that initialization isn't kept up-to-date across
  208. * different time counters in SMP mode. Therefore we can only use this
  209. * method when there's only one CPU enabled.
  210. *
  211. * When using the WTINT PALcall, the RPCC may shift to a lower frequency,
  212. * or stop altogether, while waiting for the interrupt. Therefore we cannot
  213. * use this method when WTINT is in use.
  214. */
  215. static u64 read_rpcc(struct clocksource *cs)
  216. {
  217. return rpcc();
  218. }
  219. static struct clocksource clocksource_rpcc = {
  220. .name = "rpcc",
  221. .rating = 300,
  222. .read = read_rpcc,
  223. .mask = CLOCKSOURCE_MASK(32),
  224. .flags = CLOCK_SOURCE_IS_CONTINUOUS
  225. };
  226. #endif /* ALPHA_WTINT */
  227. /* Validate a computed cycle counter result against the known bounds for
  228. the given processor core. There's too much brokenness in the way of
  229. timing hardware for any one method to work everywhere. :-(
  230. Return 0 if the result cannot be trusted, otherwise return the argument. */
  231. static unsigned long __init
  232. validate_cc_value(unsigned long cc)
  233. {
  234. static struct bounds {
  235. unsigned int min, max;
  236. } cpu_hz[] __initdata = {
  237. [EV3_CPU] = { 50000000, 200000000 }, /* guess */
  238. [EV4_CPU] = { 100000000, 300000000 },
  239. [LCA4_CPU] = { 100000000, 300000000 }, /* guess */
  240. [EV45_CPU] = { 200000000, 300000000 },
  241. [EV5_CPU] = { 250000000, 433000000 },
  242. [EV56_CPU] = { 333000000, 667000000 },
  243. [PCA56_CPU] = { 400000000, 600000000 }, /* guess */
  244. [PCA57_CPU] = { 500000000, 600000000 }, /* guess */
  245. [EV6_CPU] = { 466000000, 600000000 },
  246. [EV67_CPU] = { 600000000, 750000000 },
  247. [EV68AL_CPU] = { 750000000, 940000000 },
  248. [EV68CB_CPU] = { 1000000000, 1333333333 },
  249. /* None of the following are shipping as of 2001-11-01. */
  250. [EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
  251. [EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
  252. [EV7_CPU] = { 800000000, 1400000000 }, /* guess */
  253. [EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
  254. };
  255. /* Allow for some drift in the crystal. 10MHz is more than enough. */
  256. const unsigned int deviation = 10000000;
  257. struct percpu_struct *cpu;
  258. unsigned int index;
  259. cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
  260. index = cpu->type & 0xffffffff;
  261. /* If index out of bounds, no way to validate. */
  262. if (index >= ARRAY_SIZE(cpu_hz))
  263. return cc;
  264. /* If index contains no data, no way to validate. */
  265. if (cpu_hz[index].max == 0)
  266. return cc;
  267. if (cc < cpu_hz[index].min - deviation
  268. || cc > cpu_hz[index].max + deviation)
  269. return 0;
  270. return cc;
  271. }
  272. /*
  273. * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
  274. * arch/i386/time.c.
  275. */
  276. #define CALIBRATE_LATCH 0xffff
  277. #define TIMEOUT_COUNT 0x100000
  278. static unsigned long __init
  279. calibrate_cc_with_pit(void)
  280. {
  281. int cc, count = 0;
  282. /* Set the Gate high, disable speaker */
  283. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  284. /*
  285. * Now let's take care of CTC channel 2
  286. *
  287. * Set the Gate high, program CTC channel 2 for mode 0,
  288. * (interrupt on terminal count mode), binary count,
  289. * load 5 * LATCH count, (LSB and MSB) to begin countdown.
  290. */
  291. outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
  292. outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
  293. outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
  294. cc = rpcc();
  295. do {
  296. count++;
  297. } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
  298. cc = rpcc() - cc;
  299. /* Error: ECTCNEVERSET or ECPUTOOFAST. */
  300. if (count <= 1 || count == TIMEOUT_COUNT)
  301. return 0;
  302. return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
  303. }
  304. /* The Linux interpretation of the CMOS clock register contents:
  305. When the Update-In-Progress (UIP) flag goes from 1 to 0, the
  306. RTC registers show the second which has precisely just started.
  307. Let's hope other operating systems interpret the RTC the same way. */
  308. static unsigned long __init
  309. rpcc_after_update_in_progress(void)
  310. {
  311. do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
  312. do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
  313. return rpcc();
  314. }
  315. void __init
  316. time_init(void)
  317. {
  318. unsigned int cc1, cc2;
  319. unsigned long cycle_freq, tolerance;
  320. long diff;
  321. if (alpha_using_qemu) {
  322. clocksource_register_hz(&qemu_cs, NSEC_PER_SEC);
  323. init_qemu_clockevent();
  324. init_rtc_irq(qemu_timer_interrupt);
  325. return;
  326. }
  327. /* Calibrate CPU clock -- attempt #1. */
  328. if (!est_cycle_freq)
  329. est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
  330. cc1 = rpcc();
  331. /* Calibrate CPU clock -- attempt #2. */
  332. if (!est_cycle_freq) {
  333. cc1 = rpcc_after_update_in_progress();
  334. cc2 = rpcc_after_update_in_progress();
  335. est_cycle_freq = validate_cc_value(cc2 - cc1);
  336. cc1 = cc2;
  337. }
  338. cycle_freq = hwrpb->cycle_freq;
  339. if (est_cycle_freq) {
  340. /* If the given value is within 250 PPM of what we calculated,
  341. accept it. Otherwise, use what we found. */
  342. tolerance = cycle_freq / 4000;
  343. diff = cycle_freq - est_cycle_freq;
  344. if (diff < 0)
  345. diff = -diff;
  346. if ((unsigned long)diff > tolerance) {
  347. cycle_freq = est_cycle_freq;
  348. printk("HWRPB cycle frequency bogus. "
  349. "Estimated %lu Hz\n", cycle_freq);
  350. } else {
  351. est_cycle_freq = 0;
  352. }
  353. } else if (! validate_cc_value (cycle_freq)) {
  354. printk("HWRPB cycle frequency bogus, "
  355. "and unable to estimate a proper value!\n");
  356. }
  357. /* See above for restrictions on using clocksource_rpcc. */
  358. #ifndef CONFIG_ALPHA_WTINT
  359. if (hwrpb->nr_processors == 1)
  360. clocksource_register_hz(&clocksource_rpcc, cycle_freq);
  361. #endif
  362. /* Startup the timer source. */
  363. alpha_mv.init_rtc();
  364. init_rtc_clockevent();
  365. }
  366. /* Initialize the clock_event_device for secondary cpus. */
  367. #ifdef CONFIG_SMP
  368. void __init
  369. init_clockevent(void)
  370. {
  371. if (alpha_using_qemu)
  372. init_qemu_clockevent();
  373. else
  374. init_rtc_clockevent();
  375. }
  376. #endif