cpcap.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ALSA SoC CPCAP codec driver
  4. *
  5. * Copyright (C) 2017 - 2018 Sebastian Reichel <[email protected]>
  6. *
  7. * Very loosely based on original driver from Motorola:
  8. * Copyright (C) 2007 - 2009 Motorola, Inc.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mfd/motorola-cpcap.h>
  14. #include <sound/core.h>
  15. #include <sound/soc.h>
  16. #include <sound/tlv.h>
  17. /* Register 512 CPCAP_REG_VAUDIOC --- Audio Regulator and Bias Voltage */
  18. #define CPCAP_BIT_AUDIO_LOW_PWR 6
  19. #define CPCAP_BIT_AUD_LOWPWR_SPEED 5
  20. #define CPCAP_BIT_VAUDIOPRISTBY 4
  21. #define CPCAP_BIT_VAUDIO_MODE1 2
  22. #define CPCAP_BIT_VAUDIO_MODE0 1
  23. #define CPCAP_BIT_V_AUDIO_EN 0
  24. /* Register 513 CPCAP_REG_CC --- CODEC */
  25. #define CPCAP_BIT_CDC_CLK2 15
  26. #define CPCAP_BIT_CDC_CLK1 14
  27. #define CPCAP_BIT_CDC_CLK0 13
  28. #define CPCAP_BIT_CDC_SR3 12
  29. #define CPCAP_BIT_CDC_SR2 11
  30. #define CPCAP_BIT_CDC_SR1 10
  31. #define CPCAP_BIT_CDC_SR0 9
  32. #define CPCAP_BIT_CDC_CLOCK_TREE_RESET 8
  33. #define CPCAP_BIT_MIC2_CDC_EN 7
  34. #define CPCAP_BIT_CDC_EN_RX 6
  35. #define CPCAP_BIT_DF_RESET 5
  36. #define CPCAP_BIT_MIC1_CDC_EN 4
  37. #define CPCAP_BIT_AUDOHPF_1 3
  38. #define CPCAP_BIT_AUDOHPF_0 2
  39. #define CPCAP_BIT_AUDIHPF_1 1
  40. #define CPCAP_BIT_AUDIHPF_0 0
  41. /* Register 514 CPCAP_REG_CDI --- CODEC Digital Audio Interface */
  42. #define CPCAP_BIT_CDC_PLL_SEL 15
  43. #define CPCAP_BIT_CLK_IN_SEL 13
  44. #define CPCAP_BIT_DIG_AUD_IN 12
  45. #define CPCAP_BIT_CDC_CLK_EN 11
  46. #define CPCAP_BIT_CDC_DIG_AUD_FS1 10
  47. #define CPCAP_BIT_CDC_DIG_AUD_FS0 9
  48. #define CPCAP_BIT_MIC2_TIMESLOT2 8
  49. #define CPCAP_BIT_MIC2_TIMESLOT1 7
  50. #define CPCAP_BIT_MIC2_TIMESLOT0 6
  51. #define CPCAP_BIT_MIC1_RX_TIMESLOT2 5
  52. #define CPCAP_BIT_MIC1_RX_TIMESLOT1 4
  53. #define CPCAP_BIT_MIC1_RX_TIMESLOT0 3
  54. #define CPCAP_BIT_FS_INV 2
  55. #define CPCAP_BIT_CLK_INV 1
  56. #define CPCAP_BIT_SMB_CDC 0
  57. /* Register 515 CPCAP_REG_SDAC --- Stereo DAC */
  58. #define CPCAP_BIT_FSYNC_CLK_IN_COMMON 11
  59. #define CPCAP_BIT_SLAVE_PLL_CLK_INPUT 10
  60. #define CPCAP_BIT_ST_CLOCK_TREE_RESET 9
  61. #define CPCAP_BIT_DF_RESET_ST_DAC 8
  62. #define CPCAP_BIT_ST_SR3 7
  63. #define CPCAP_BIT_ST_SR2 6
  64. #define CPCAP_BIT_ST_SR1 5
  65. #define CPCAP_BIT_ST_SR0 4
  66. #define CPCAP_BIT_ST_DAC_CLK2 3
  67. #define CPCAP_BIT_ST_DAC_CLK1 2
  68. #define CPCAP_BIT_ST_DAC_CLK0 1
  69. #define CPCAP_BIT_ST_DAC_EN 0
  70. /* Register 516 CPCAP_REG_SDACDI --- Stereo DAC Digital Audio Interface */
  71. #define CPCAP_BIT_ST_L_TIMESLOT2 13
  72. #define CPCAP_BIT_ST_L_TIMESLOT1 12
  73. #define CPCAP_BIT_ST_L_TIMESLOT0 11
  74. #define CPCAP_BIT_ST_R_TIMESLOT2 10
  75. #define CPCAP_BIT_ST_R_TIMESLOT1 9
  76. #define CPCAP_BIT_ST_R_TIMESLOT0 8
  77. #define CPCAP_BIT_ST_DAC_CLK_IN_SEL 7
  78. #define CPCAP_BIT_ST_FS_INV 6
  79. #define CPCAP_BIT_ST_CLK_INV 5
  80. #define CPCAP_BIT_ST_DIG_AUD_FS1 4
  81. #define CPCAP_BIT_ST_DIG_AUD_FS0 3
  82. #define CPCAP_BIT_DIG_AUD_IN_ST_DAC 2
  83. #define CPCAP_BIT_ST_CLK_EN 1
  84. #define CPCAP_BIT_SMB_ST_DAC 0
  85. /* Register 517 CPCAP_REG_TXI --- TX Interface */
  86. #define CPCAP_BIT_PTT_TH 15
  87. #define CPCAP_BIT_PTT_CMP_EN 14
  88. #define CPCAP_BIT_HS_ID_TX 13
  89. #define CPCAP_BIT_MB_ON2 12
  90. #define CPCAP_BIT_MB_ON1L 11
  91. #define CPCAP_BIT_MB_ON1R 10
  92. #define CPCAP_BIT_RX_L_ENCODE 9
  93. #define CPCAP_BIT_RX_R_ENCODE 8
  94. #define CPCAP_BIT_MIC2_MUX 7
  95. #define CPCAP_BIT_MIC2_PGA_EN 6
  96. #define CPCAP_BIT_CDET_DIS 5
  97. #define CPCAP_BIT_EMU_MIC_MUX 4
  98. #define CPCAP_BIT_HS_MIC_MUX 3
  99. #define CPCAP_BIT_MIC1_MUX 2
  100. #define CPCAP_BIT_MIC1_PGA_EN 1
  101. #define CPCAP_BIT_DLM 0
  102. /* Register 518 CPCAP_REG_TXMP --- Mic Gain */
  103. #define CPCAP_BIT_MB_BIAS_R1 11
  104. #define CPCAP_BIT_MB_BIAS_R0 10
  105. #define CPCAP_BIT_MIC2_GAIN_4 9
  106. #define CPCAP_BIT_MIC2_GAIN_3 8
  107. #define CPCAP_BIT_MIC2_GAIN_2 7
  108. #define CPCAP_BIT_MIC2_GAIN_1 6
  109. #define CPCAP_BIT_MIC2_GAIN_0 5
  110. #define CPCAP_BIT_MIC1_GAIN_4 4
  111. #define CPCAP_BIT_MIC1_GAIN_3 3
  112. #define CPCAP_BIT_MIC1_GAIN_2 2
  113. #define CPCAP_BIT_MIC1_GAIN_1 1
  114. #define CPCAP_BIT_MIC1_GAIN_0 0
  115. /* Register 519 CPCAP_REG_RXOA --- RX Output Amplifier */
  116. #define CPCAP_BIT_UNUSED_519_15 15
  117. #define CPCAP_BIT_UNUSED_519_14 14
  118. #define CPCAP_BIT_UNUSED_519_13 13
  119. #define CPCAP_BIT_STDAC_LOW_PWR_DISABLE 12
  120. #define CPCAP_BIT_HS_LOW_PWR 11
  121. #define CPCAP_BIT_HS_ID_RX 10
  122. #define CPCAP_BIT_ST_HS_CP_EN 9
  123. #define CPCAP_BIT_EMU_SPKR_R_EN 8
  124. #define CPCAP_BIT_EMU_SPKR_L_EN 7
  125. #define CPCAP_BIT_HS_L_EN 6
  126. #define CPCAP_BIT_HS_R_EN 5
  127. #define CPCAP_BIT_A4_LINEOUT_L_EN 4
  128. #define CPCAP_BIT_A4_LINEOUT_R_EN 3
  129. #define CPCAP_BIT_A2_LDSP_L_EN 2
  130. #define CPCAP_BIT_A2_LDSP_R_EN 1
  131. #define CPCAP_BIT_A1_EAR_EN 0
  132. /* Register 520 CPCAP_REG_RXVC --- RX Volume Control */
  133. #define CPCAP_BIT_VOL_EXT3 15
  134. #define CPCAP_BIT_VOL_EXT2 14
  135. #define CPCAP_BIT_VOL_EXT1 13
  136. #define CPCAP_BIT_VOL_EXT0 12
  137. #define CPCAP_BIT_VOL_DAC3 11
  138. #define CPCAP_BIT_VOL_DAC2 10
  139. #define CPCAP_BIT_VOL_DAC1 9
  140. #define CPCAP_BIT_VOL_DAC0 8
  141. #define CPCAP_BIT_VOL_DAC_LSB_1dB1 7
  142. #define CPCAP_BIT_VOL_DAC_LSB_1dB0 6
  143. #define CPCAP_BIT_VOL_CDC3 5
  144. #define CPCAP_BIT_VOL_CDC2 4
  145. #define CPCAP_BIT_VOL_CDC1 3
  146. #define CPCAP_BIT_VOL_CDC0 2
  147. #define CPCAP_BIT_VOL_CDC_LSB_1dB1 1
  148. #define CPCAP_BIT_VOL_CDC_LSB_1dB0 0
  149. /* Register 521 CPCAP_REG_RXCOA --- Codec to Output Amp Switches */
  150. #define CPCAP_BIT_PGA_CDC_EN 10
  151. #define CPCAP_BIT_CDC_SW 9
  152. #define CPCAP_BIT_PGA_OUTR_USBDP_CDC_SW 8
  153. #define CPCAP_BIT_PGA_OUTL_USBDN_CDC_SW 7
  154. #define CPCAP_BIT_ALEFT_HS_CDC_SW 6
  155. #define CPCAP_BIT_ARIGHT_HS_CDC_SW 5
  156. #define CPCAP_BIT_A4_LINEOUT_L_CDC_SW 4
  157. #define CPCAP_BIT_A4_LINEOUT_R_CDC_SW 3
  158. #define CPCAP_BIT_A2_LDSP_L_CDC_SW 2
  159. #define CPCAP_BIT_A2_LDSP_R_CDC_SW 1
  160. #define CPCAP_BIT_A1_EAR_CDC_SW 0
  161. /* Register 522 CPCAP_REG_RXSDOA --- RX Stereo DAC to Output Amp Switches */
  162. #define CPCAP_BIT_PGA_DAC_EN 12
  163. #define CPCAP_BIT_ST_DAC_SW 11
  164. #define CPCAP_BIT_MONO_DAC1 10
  165. #define CPCAP_BIT_MONO_DAC0 9
  166. #define CPCAP_BIT_PGA_OUTR_USBDP_DAC_SW 8
  167. #define CPCAP_BIT_PGA_OUTL_USBDN_DAC_SW 7
  168. #define CPCAP_BIT_ALEFT_HS_DAC_SW 6
  169. #define CPCAP_BIT_ARIGHT_HS_DAC_SW 5
  170. #define CPCAP_BIT_A4_LINEOUT_L_DAC_SW 4
  171. #define CPCAP_BIT_A4_LINEOUT_R_DAC_SW 3
  172. #define CPCAP_BIT_A2_LDSP_L_DAC_SW 2
  173. #define CPCAP_BIT_A2_LDSP_R_DAC_SW 1
  174. #define CPCAP_BIT_A1_EAR_DAC_SW 0
  175. /* Register 523 CPCAP_REG_RXEPOA --- RX External PGA to Output Amp Switches */
  176. #define CPCAP_BIT_PGA_EXT_L_EN 14
  177. #define CPCAP_BIT_PGA_EXT_R_EN 13
  178. #define CPCAP_BIT_PGA_IN_L_SW 12
  179. #define CPCAP_BIT_PGA_IN_R_SW 11
  180. #define CPCAP_BIT_MONO_EXT1 10
  181. #define CPCAP_BIT_MONO_EXT0 9
  182. #define CPCAP_BIT_PGA_OUTR_USBDP_EXT_SW 8
  183. #define CPCAP_BIT_PGA_OUTL_USBDN_EXT_SW 7
  184. #define CPCAP_BIT_ALEFT_HS_EXT_SW 6
  185. #define CPCAP_BIT_ARIGHT_HS_EXT_SW 5
  186. #define CPCAP_BIT_A4_LINEOUT_L_EXT_SW 4
  187. #define CPCAP_BIT_A4_LINEOUT_R_EXT_SW 3
  188. #define CPCAP_BIT_A2_LDSP_L_EXT_SW 2
  189. #define CPCAP_BIT_A2_LDSP_R_EXT_SW 1
  190. #define CPCAP_BIT_A1_EAR_EXT_SW 0
  191. /* Register 525 CPCAP_REG_A2LA --- SPK Amplifier and Clock Config for Headset */
  192. #define CPCAP_BIT_NCP_CLK_SYNC 7
  193. #define CPCAP_BIT_A2_CLK_SYNC 6
  194. #define CPCAP_BIT_A2_FREE_RUN 5
  195. #define CPCAP_BIT_A2_CLK2 4
  196. #define CPCAP_BIT_A2_CLK1 3
  197. #define CPCAP_BIT_A2_CLK0 2
  198. #define CPCAP_BIT_A2_CLK_IN 1
  199. #define CPCAP_BIT_A2_CONFIG 0
  200. #define SLEEP_ACTIVATE_POWER 2
  201. #define CLOCK_TREE_RESET_TIME 1
  202. /* constants for ST delay workaround */
  203. #define STM_STDAC_ACTIVATE_RAMP_TIME 1
  204. #define STM_STDAC_EN_TEST_PRE 0x090C
  205. #define STM_STDAC_EN_TEST_POST 0x0000
  206. #define STM_STDAC_EN_ST_TEST1_PRE 0x2400
  207. #define STM_STDAC_EN_ST_TEST1_POST 0x0400
  208. struct cpcap_reg_info {
  209. u16 reg;
  210. u16 mask;
  211. u16 val;
  212. };
  213. static const struct cpcap_reg_info cpcap_default_regs[] = {
  214. { CPCAP_REG_VAUDIOC, 0x003F, 0x0000 },
  215. { CPCAP_REG_CC, 0xFFFF, 0x0000 },
  216. { CPCAP_REG_CC, 0xFFFF, 0x0000 },
  217. { CPCAP_REG_CDI, 0xBFFF, 0x0000 },
  218. { CPCAP_REG_SDAC, 0x0FFF, 0x0000 },
  219. { CPCAP_REG_SDACDI, 0x3FFF, 0x0000 },
  220. { CPCAP_REG_TXI, 0x0FDF, 0x0000 },
  221. { CPCAP_REG_TXMP, 0x0FFF, 0x0400 },
  222. { CPCAP_REG_RXOA, 0x01FF, 0x0000 },
  223. { CPCAP_REG_RXVC, 0xFF3C, 0x0000 },
  224. { CPCAP_REG_RXCOA, 0x07FF, 0x0000 },
  225. { CPCAP_REG_RXSDOA, 0x1FFF, 0x0000 },
  226. { CPCAP_REG_RXEPOA, 0x7FFF, 0x0000 },
  227. { CPCAP_REG_A2LA, BIT(CPCAP_BIT_A2_FREE_RUN),
  228. BIT(CPCAP_BIT_A2_FREE_RUN) },
  229. };
  230. enum cpcap_dai {
  231. CPCAP_DAI_HIFI,
  232. CPCAP_DAI_VOICE,
  233. };
  234. struct cpcap_audio {
  235. struct snd_soc_component *component;
  236. struct regmap *regmap;
  237. u16 vendor;
  238. int codec_clk_id;
  239. int codec_freq;
  240. int codec_format;
  241. };
  242. static int cpcap_st_workaround(struct snd_soc_dapm_widget *w,
  243. struct snd_kcontrol *kcontrol, int event)
  244. {
  245. struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  246. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  247. int err = 0;
  248. /* Only CPCAP from ST requires workaround */
  249. if (cpcap->vendor != CPCAP_VENDOR_ST)
  250. return 0;
  251. switch (event) {
  252. case SND_SOC_DAPM_PRE_PMU:
  253. err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
  254. STM_STDAC_EN_TEST_PRE);
  255. if (err)
  256. return err;
  257. err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
  258. STM_STDAC_EN_ST_TEST1_PRE);
  259. break;
  260. case SND_SOC_DAPM_POST_PMU:
  261. msleep(STM_STDAC_ACTIVATE_RAMP_TIME);
  262. err = regmap_write(cpcap->regmap, CPCAP_REG_ST_TEST1,
  263. STM_STDAC_EN_ST_TEST1_POST);
  264. if (err)
  265. return err;
  266. err = regmap_write(cpcap->regmap, CPCAP_REG_TEST,
  267. STM_STDAC_EN_TEST_POST);
  268. break;
  269. default:
  270. break;
  271. }
  272. return err;
  273. }
  274. /* Capture Gain Control: 0dB to 31dB in 1dB steps */
  275. static const DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
  276. /* Playback Gain Control: -33dB to 12dB in 3dB steps */
  277. static const DECLARE_TLV_DB_SCALE(vol_tlv, -3300, 300, 0);
  278. static const struct snd_kcontrol_new cpcap_snd_controls[] = {
  279. /* Playback Gain */
  280. SOC_SINGLE_TLV("HiFi Playback Volume",
  281. CPCAP_REG_RXVC, CPCAP_BIT_VOL_DAC0, 0xF, 0, vol_tlv),
  282. SOC_SINGLE_TLV("Voice Playback Volume",
  283. CPCAP_REG_RXVC, CPCAP_BIT_VOL_CDC0, 0xF, 0, vol_tlv),
  284. SOC_SINGLE_TLV("Ext Playback Volume",
  285. CPCAP_REG_RXVC, CPCAP_BIT_VOL_EXT0, 0xF, 0, vol_tlv),
  286. /* Capture Gain */
  287. SOC_SINGLE_TLV("Mic1 Capture Volume",
  288. CPCAP_REG_TXMP, CPCAP_BIT_MIC1_GAIN_0, 0x1F, 0, mic_gain_tlv),
  289. SOC_SINGLE_TLV("Mic2 Capture Volume",
  290. CPCAP_REG_TXMP, CPCAP_BIT_MIC2_GAIN_0, 0x1F, 0, mic_gain_tlv),
  291. /* Phase Invert */
  292. SOC_SINGLE("Hifi Left Phase Invert Switch",
  293. CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC0, 1, 0),
  294. SOC_SINGLE("Ext Left Phase Invert Switch",
  295. CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
  296. };
  297. static const char * const cpcap_out_mux_texts[] = {
  298. "Off", "Voice", "HiFi", "Ext"
  299. };
  300. static const char * const cpcap_in_right_mux_texts[] = {
  301. "Off", "Mic 1", "Headset Mic", "EMU Mic", "Ext Right"
  302. };
  303. static const char * const cpcap_in_left_mux_texts[] = {
  304. "Off", "Mic 2", "Ext Left"
  305. };
  306. /*
  307. * input muxes use unusual register layout, so that we need to use custom
  308. * getter/setter methods
  309. */
  310. static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_left_mux_enum,
  311. cpcap_in_left_mux_texts);
  312. static SOC_ENUM_SINGLE_EXT_DECL(cpcap_input_right_mux_enum,
  313. cpcap_in_right_mux_texts);
  314. /*
  315. * mux uses same bit in CPCAP_REG_RXCOA, CPCAP_REG_RXSDOA & CPCAP_REG_RXEPOA;
  316. * even though the register layout makes it look like a mixer, this is a mux.
  317. * Enabling multiple inputs will result in no audio being forwarded.
  318. */
  319. static SOC_ENUM_SINGLE_DECL(cpcap_earpiece_mux_enum, 0, 0, cpcap_out_mux_texts);
  320. static SOC_ENUM_SINGLE_DECL(cpcap_spkr_r_mux_enum, 0, 1, cpcap_out_mux_texts);
  321. static SOC_ENUM_SINGLE_DECL(cpcap_spkr_l_mux_enum, 0, 2, cpcap_out_mux_texts);
  322. static SOC_ENUM_SINGLE_DECL(cpcap_line_r_mux_enum, 0, 3, cpcap_out_mux_texts);
  323. static SOC_ENUM_SINGLE_DECL(cpcap_line_l_mux_enum, 0, 4, cpcap_out_mux_texts);
  324. static SOC_ENUM_SINGLE_DECL(cpcap_hs_r_mux_enum, 0, 5, cpcap_out_mux_texts);
  325. static SOC_ENUM_SINGLE_DECL(cpcap_hs_l_mux_enum, 0, 6, cpcap_out_mux_texts);
  326. static SOC_ENUM_SINGLE_DECL(cpcap_emu_l_mux_enum, 0, 7, cpcap_out_mux_texts);
  327. static SOC_ENUM_SINGLE_DECL(cpcap_emu_r_mux_enum, 0, 8, cpcap_out_mux_texts);
  328. static int cpcap_output_mux_get_enum(struct snd_kcontrol *kcontrol,
  329. struct snd_ctl_elem_value *ucontrol)
  330. {
  331. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  332. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  333. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  334. unsigned int shift = e->shift_l;
  335. int reg_voice, reg_hifi, reg_ext, status;
  336. int err;
  337. err = regmap_read(cpcap->regmap, CPCAP_REG_RXCOA, &reg_voice);
  338. if (err)
  339. return err;
  340. err = regmap_read(cpcap->regmap, CPCAP_REG_RXSDOA, &reg_hifi);
  341. if (err)
  342. return err;
  343. err = regmap_read(cpcap->regmap, CPCAP_REG_RXEPOA, &reg_ext);
  344. if (err)
  345. return err;
  346. reg_voice = (reg_voice >> shift) & 1;
  347. reg_hifi = (reg_hifi >> shift) & 1;
  348. reg_ext = (reg_ext >> shift) & 1;
  349. status = reg_ext << 2 | reg_hifi << 1 | reg_voice;
  350. switch (status) {
  351. case 0x04:
  352. ucontrol->value.enumerated.item[0] = 3;
  353. break;
  354. case 0x02:
  355. ucontrol->value.enumerated.item[0] = 2;
  356. break;
  357. case 0x01:
  358. ucontrol->value.enumerated.item[0] = 1;
  359. break;
  360. default:
  361. ucontrol->value.enumerated.item[0] = 0;
  362. break;
  363. }
  364. return 0;
  365. }
  366. static int cpcap_output_mux_put_enum(struct snd_kcontrol *kcontrol,
  367. struct snd_ctl_elem_value *ucontrol)
  368. {
  369. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  370. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  371. struct snd_soc_dapm_context *dapm =
  372. snd_soc_dapm_kcontrol_dapm(kcontrol);
  373. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  374. unsigned int muxval = ucontrol->value.enumerated.item[0];
  375. unsigned int mask = BIT(e->shift_l);
  376. u16 reg_voice = 0x00, reg_hifi = 0x00, reg_ext = 0x00;
  377. int err;
  378. switch (muxval) {
  379. case 1:
  380. reg_voice = mask;
  381. break;
  382. case 2:
  383. reg_hifi = mask;
  384. break;
  385. case 3:
  386. reg_ext = mask;
  387. break;
  388. default:
  389. break;
  390. }
  391. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
  392. mask, reg_voice);
  393. if (err)
  394. return err;
  395. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXSDOA,
  396. mask, reg_hifi);
  397. if (err)
  398. return err;
  399. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXEPOA,
  400. mask, reg_ext);
  401. if (err)
  402. return err;
  403. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  404. return 0;
  405. }
  406. static int cpcap_input_right_mux_get_enum(struct snd_kcontrol *kcontrol,
  407. struct snd_ctl_elem_value *ucontrol)
  408. {
  409. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  410. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  411. int regval, mask;
  412. int err;
  413. err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
  414. if (err)
  415. return err;
  416. mask = 0;
  417. mask |= BIT(CPCAP_BIT_MIC1_MUX);
  418. mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
  419. mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
  420. mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
  421. switch (regval & mask) {
  422. case BIT(CPCAP_BIT_RX_R_ENCODE):
  423. ucontrol->value.enumerated.item[0] = 4;
  424. break;
  425. case BIT(CPCAP_BIT_EMU_MIC_MUX):
  426. ucontrol->value.enumerated.item[0] = 3;
  427. break;
  428. case BIT(CPCAP_BIT_HS_MIC_MUX):
  429. ucontrol->value.enumerated.item[0] = 2;
  430. break;
  431. case BIT(CPCAP_BIT_MIC1_MUX):
  432. ucontrol->value.enumerated.item[0] = 1;
  433. break;
  434. default:
  435. ucontrol->value.enumerated.item[0] = 0;
  436. break;
  437. }
  438. return 0;
  439. }
  440. static int cpcap_input_right_mux_put_enum(struct snd_kcontrol *kcontrol,
  441. struct snd_ctl_elem_value *ucontrol)
  442. {
  443. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  444. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  445. struct snd_soc_dapm_context *dapm =
  446. snd_soc_dapm_kcontrol_dapm(kcontrol);
  447. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  448. unsigned int muxval = ucontrol->value.enumerated.item[0];
  449. int regval = 0, mask;
  450. int err;
  451. mask = 0;
  452. mask |= BIT(CPCAP_BIT_MIC1_MUX);
  453. mask |= BIT(CPCAP_BIT_HS_MIC_MUX);
  454. mask |= BIT(CPCAP_BIT_EMU_MIC_MUX);
  455. mask |= BIT(CPCAP_BIT_RX_R_ENCODE);
  456. switch (muxval) {
  457. case 1:
  458. regval = BIT(CPCAP_BIT_MIC1_MUX);
  459. break;
  460. case 2:
  461. regval = BIT(CPCAP_BIT_HS_MIC_MUX);
  462. break;
  463. case 3:
  464. regval = BIT(CPCAP_BIT_EMU_MIC_MUX);
  465. break;
  466. case 4:
  467. regval = BIT(CPCAP_BIT_RX_R_ENCODE);
  468. break;
  469. default:
  470. break;
  471. }
  472. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  473. mask, regval);
  474. if (err)
  475. return err;
  476. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  477. return 0;
  478. }
  479. static int cpcap_input_left_mux_get_enum(struct snd_kcontrol *kcontrol,
  480. struct snd_ctl_elem_value *ucontrol)
  481. {
  482. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  483. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  484. int regval, mask;
  485. int err;
  486. err = regmap_read(cpcap->regmap, CPCAP_REG_TXI, &regval);
  487. if (err)
  488. return err;
  489. mask = 0;
  490. mask |= BIT(CPCAP_BIT_MIC2_MUX);
  491. mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
  492. switch (regval & mask) {
  493. case BIT(CPCAP_BIT_RX_L_ENCODE):
  494. ucontrol->value.enumerated.item[0] = 2;
  495. break;
  496. case BIT(CPCAP_BIT_MIC2_MUX):
  497. ucontrol->value.enumerated.item[0] = 1;
  498. break;
  499. default:
  500. ucontrol->value.enumerated.item[0] = 0;
  501. break;
  502. }
  503. return 0;
  504. }
  505. static int cpcap_input_left_mux_put_enum(struct snd_kcontrol *kcontrol,
  506. struct snd_ctl_elem_value *ucontrol)
  507. {
  508. struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
  509. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  510. struct snd_soc_dapm_context *dapm =
  511. snd_soc_dapm_kcontrol_dapm(kcontrol);
  512. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  513. unsigned int muxval = ucontrol->value.enumerated.item[0];
  514. int regval = 0, mask;
  515. int err;
  516. mask = 0;
  517. mask |= BIT(CPCAP_BIT_MIC2_MUX);
  518. mask |= BIT(CPCAP_BIT_RX_L_ENCODE);
  519. switch (muxval) {
  520. case 1:
  521. regval = BIT(CPCAP_BIT_MIC2_MUX);
  522. break;
  523. case 2:
  524. regval = BIT(CPCAP_BIT_RX_L_ENCODE);
  525. break;
  526. default:
  527. break;
  528. }
  529. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  530. mask, regval);
  531. if (err)
  532. return err;
  533. snd_soc_dapm_mux_update_power(dapm, kcontrol, muxval, e, NULL);
  534. return 0;
  535. }
  536. static const struct snd_kcontrol_new cpcap_input_left_mux =
  537. SOC_DAPM_ENUM_EXT("Input Left", cpcap_input_left_mux_enum,
  538. cpcap_input_left_mux_get_enum,
  539. cpcap_input_left_mux_put_enum);
  540. static const struct snd_kcontrol_new cpcap_input_right_mux =
  541. SOC_DAPM_ENUM_EXT("Input Right", cpcap_input_right_mux_enum,
  542. cpcap_input_right_mux_get_enum,
  543. cpcap_input_right_mux_put_enum);
  544. static const struct snd_kcontrol_new cpcap_emu_left_mux =
  545. SOC_DAPM_ENUM_EXT("EMU Left", cpcap_emu_l_mux_enum,
  546. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  547. static const struct snd_kcontrol_new cpcap_emu_right_mux =
  548. SOC_DAPM_ENUM_EXT("EMU Right", cpcap_emu_r_mux_enum,
  549. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  550. static const struct snd_kcontrol_new cpcap_hs_left_mux =
  551. SOC_DAPM_ENUM_EXT("Headset Left", cpcap_hs_l_mux_enum,
  552. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  553. static const struct snd_kcontrol_new cpcap_hs_right_mux =
  554. SOC_DAPM_ENUM_EXT("Headset Right", cpcap_hs_r_mux_enum,
  555. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  556. static const struct snd_kcontrol_new cpcap_line_left_mux =
  557. SOC_DAPM_ENUM_EXT("Line Left", cpcap_line_l_mux_enum,
  558. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  559. static const struct snd_kcontrol_new cpcap_line_right_mux =
  560. SOC_DAPM_ENUM_EXT("Line Right", cpcap_line_r_mux_enum,
  561. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  562. static const struct snd_kcontrol_new cpcap_speaker_left_mux =
  563. SOC_DAPM_ENUM_EXT("Speaker Left", cpcap_spkr_l_mux_enum,
  564. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  565. static const struct snd_kcontrol_new cpcap_speaker_right_mux =
  566. SOC_DAPM_ENUM_EXT("Speaker Right", cpcap_spkr_r_mux_enum,
  567. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  568. static const struct snd_kcontrol_new cpcap_earpiece_mux =
  569. SOC_DAPM_ENUM_EXT("Earpiece", cpcap_earpiece_mux_enum,
  570. cpcap_output_mux_get_enum, cpcap_output_mux_put_enum);
  571. static const struct snd_kcontrol_new cpcap_hifi_mono_mixer_controls[] = {
  572. SOC_DAPM_SINGLE("HiFi Mono Playback Switch",
  573. CPCAP_REG_RXSDOA, CPCAP_BIT_MONO_DAC1, 1, 0),
  574. };
  575. static const struct snd_kcontrol_new cpcap_ext_mono_mixer_controls[] = {
  576. SOC_DAPM_SINGLE("Ext Mono Playback Switch",
  577. CPCAP_REG_RXEPOA, CPCAP_BIT_MONO_EXT0, 1, 0),
  578. };
  579. static const struct snd_kcontrol_new cpcap_extr_mute_control =
  580. SOC_DAPM_SINGLE("Switch",
  581. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_R_SW, 1, 0);
  582. static const struct snd_kcontrol_new cpcap_extl_mute_control =
  583. SOC_DAPM_SINGLE("Switch",
  584. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_IN_L_SW, 1, 0);
  585. static const struct snd_kcontrol_new cpcap_voice_loopback =
  586. SOC_DAPM_SINGLE("Switch",
  587. CPCAP_REG_TXI, CPCAP_BIT_DLM, 1, 0);
  588. static const struct snd_soc_dapm_widget cpcap_dapm_widgets[] = {
  589. /* DAIs */
  590. SND_SOC_DAPM_AIF_IN("HiFi RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  591. SND_SOC_DAPM_AIF_IN("Voice RX", NULL, 0, SND_SOC_NOPM, 0, 0),
  592. SND_SOC_DAPM_AIF_OUT("Voice TX", NULL, 0, SND_SOC_NOPM, 0, 0),
  593. /* Power Supply */
  594. SND_SOC_DAPM_REGULATOR_SUPPLY("VAUDIO", SLEEP_ACTIVATE_POWER, 0),
  595. /* Highpass Filters */
  596. SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter RX",
  597. CPCAP_REG_CC, CPCAP_BIT_AUDIHPF_0, 0x3, 0x3, 0x0),
  598. SND_SOC_DAPM_REG(snd_soc_dapm_pga, "Highpass Filter TX",
  599. CPCAP_REG_CC, CPCAP_BIT_AUDOHPF_0, 0x3, 0x3, 0x0),
  600. /* Clocks */
  601. SND_SOC_DAPM_SUPPLY("HiFi DAI Clock",
  602. CPCAP_REG_SDACDI, CPCAP_BIT_ST_CLK_EN, 0, NULL, 0),
  603. SND_SOC_DAPM_SUPPLY("Voice DAI Clock",
  604. CPCAP_REG_CDI, CPCAP_BIT_CDC_CLK_EN, 0, NULL, 0),
  605. /* Microphone Bias */
  606. SND_SOC_DAPM_SUPPLY("MIC1R Bias",
  607. CPCAP_REG_TXI, CPCAP_BIT_MB_ON1R, 0, NULL, 0),
  608. SND_SOC_DAPM_SUPPLY("MIC1L Bias",
  609. CPCAP_REG_TXI, CPCAP_BIT_MB_ON1L, 0, NULL, 0),
  610. SND_SOC_DAPM_SUPPLY("MIC2 Bias",
  611. CPCAP_REG_TXI, CPCAP_BIT_MB_ON2, 0, NULL, 0),
  612. /* Inputs */
  613. SND_SOC_DAPM_INPUT("MICR"),
  614. SND_SOC_DAPM_INPUT("HSMIC"),
  615. SND_SOC_DAPM_INPUT("EMUMIC"),
  616. SND_SOC_DAPM_INPUT("MICL"),
  617. SND_SOC_DAPM_INPUT("EXTR"),
  618. SND_SOC_DAPM_INPUT("EXTL"),
  619. /* Capture Route */
  620. SND_SOC_DAPM_MUX("Right Capture Route",
  621. SND_SOC_NOPM, 0, 0, &cpcap_input_right_mux),
  622. SND_SOC_DAPM_MUX("Left Capture Route",
  623. SND_SOC_NOPM, 0, 0, &cpcap_input_left_mux),
  624. /* Capture PGAs */
  625. SND_SOC_DAPM_PGA("Microphone 1 PGA",
  626. CPCAP_REG_TXI, CPCAP_BIT_MIC1_PGA_EN, 0, NULL, 0),
  627. SND_SOC_DAPM_PGA("Microphone 2 PGA",
  628. CPCAP_REG_TXI, CPCAP_BIT_MIC2_PGA_EN, 0, NULL, 0),
  629. /* ADC */
  630. SND_SOC_DAPM_ADC("ADC Right", NULL,
  631. CPCAP_REG_CC, CPCAP_BIT_MIC1_CDC_EN, 0),
  632. SND_SOC_DAPM_ADC("ADC Left", NULL,
  633. CPCAP_REG_CC, CPCAP_BIT_MIC2_CDC_EN, 0),
  634. /* DAC */
  635. SND_SOC_DAPM_DAC_E("DAC HiFi", NULL,
  636. CPCAP_REG_SDAC, CPCAP_BIT_ST_DAC_EN, 0,
  637. cpcap_st_workaround,
  638. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  639. SND_SOC_DAPM_DAC_E("DAC Voice", NULL,
  640. CPCAP_REG_CC, CPCAP_BIT_CDC_EN_RX, 0,
  641. cpcap_st_workaround,
  642. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  643. /* Playback PGA */
  644. SND_SOC_DAPM_PGA("HiFi PGA",
  645. CPCAP_REG_RXSDOA, CPCAP_BIT_PGA_DAC_EN, 0, NULL, 0),
  646. SND_SOC_DAPM_PGA("Voice PGA",
  647. CPCAP_REG_RXCOA, CPCAP_BIT_PGA_CDC_EN, 0, NULL, 0),
  648. SND_SOC_DAPM_PGA_E("Ext Right PGA",
  649. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_R_EN, 0,
  650. NULL, 0,
  651. cpcap_st_workaround,
  652. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  653. SND_SOC_DAPM_PGA_E("Ext Left PGA",
  654. CPCAP_REG_RXEPOA, CPCAP_BIT_PGA_EXT_L_EN, 0,
  655. NULL, 0,
  656. cpcap_st_workaround,
  657. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
  658. /* Playback Switch */
  659. SND_SOC_DAPM_SWITCH("Ext Right Enable", SND_SOC_NOPM, 0, 0,
  660. &cpcap_extr_mute_control),
  661. SND_SOC_DAPM_SWITCH("Ext Left Enable", SND_SOC_NOPM, 0, 0,
  662. &cpcap_extl_mute_control),
  663. /* Loopback Switch */
  664. SND_SOC_DAPM_SWITCH("Voice Loopback", SND_SOC_NOPM, 0, 0,
  665. &cpcap_voice_loopback),
  666. /* Mono Mixer */
  667. SOC_MIXER_ARRAY("HiFi Mono Left Mixer", SND_SOC_NOPM, 0, 0,
  668. cpcap_hifi_mono_mixer_controls),
  669. SOC_MIXER_ARRAY("HiFi Mono Right Mixer", SND_SOC_NOPM, 0, 0,
  670. cpcap_hifi_mono_mixer_controls),
  671. SOC_MIXER_ARRAY("Ext Mono Left Mixer", SND_SOC_NOPM, 0, 0,
  672. cpcap_ext_mono_mixer_controls),
  673. SOC_MIXER_ARRAY("Ext Mono Right Mixer", SND_SOC_NOPM, 0, 0,
  674. cpcap_ext_mono_mixer_controls),
  675. /* Output Routes */
  676. SND_SOC_DAPM_MUX("Earpiece Playback Route", SND_SOC_NOPM, 0, 0,
  677. &cpcap_earpiece_mux),
  678. SND_SOC_DAPM_MUX("Speaker Right Playback Route", SND_SOC_NOPM, 0, 0,
  679. &cpcap_speaker_right_mux),
  680. SND_SOC_DAPM_MUX("Speaker Left Playback Route", SND_SOC_NOPM, 0, 0,
  681. &cpcap_speaker_left_mux),
  682. SND_SOC_DAPM_MUX("Lineout Right Playback Route", SND_SOC_NOPM, 0, 0,
  683. &cpcap_line_right_mux),
  684. SND_SOC_DAPM_MUX("Lineout Left Playback Route", SND_SOC_NOPM, 0, 0,
  685. &cpcap_line_left_mux),
  686. SND_SOC_DAPM_MUX("Headset Right Playback Route", SND_SOC_NOPM, 0, 0,
  687. &cpcap_hs_right_mux),
  688. SND_SOC_DAPM_MUX("Headset Left Playback Route", SND_SOC_NOPM, 0, 0,
  689. &cpcap_hs_left_mux),
  690. SND_SOC_DAPM_MUX("EMU Right Playback Route", SND_SOC_NOPM, 0, 0,
  691. &cpcap_emu_right_mux),
  692. SND_SOC_DAPM_MUX("EMU Left Playback Route", SND_SOC_NOPM, 0, 0,
  693. &cpcap_emu_left_mux),
  694. /* Output Amplifier */
  695. SND_SOC_DAPM_PGA("Earpiece PGA",
  696. CPCAP_REG_RXOA, CPCAP_BIT_A1_EAR_EN, 0, NULL, 0),
  697. SND_SOC_DAPM_PGA("Speaker Right PGA",
  698. CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_R_EN, 0, NULL, 0),
  699. SND_SOC_DAPM_PGA("Speaker Left PGA",
  700. CPCAP_REG_RXOA, CPCAP_BIT_A2_LDSP_L_EN, 0, NULL, 0),
  701. SND_SOC_DAPM_PGA("Lineout Right PGA",
  702. CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_R_EN, 0, NULL, 0),
  703. SND_SOC_DAPM_PGA("Lineout Left PGA",
  704. CPCAP_REG_RXOA, CPCAP_BIT_A4_LINEOUT_L_EN, 0, NULL, 0),
  705. SND_SOC_DAPM_PGA("Headset Right PGA",
  706. CPCAP_REG_RXOA, CPCAP_BIT_HS_R_EN, 0, NULL, 0),
  707. SND_SOC_DAPM_PGA("Headset Left PGA",
  708. CPCAP_REG_RXOA, CPCAP_BIT_HS_L_EN, 0, NULL, 0),
  709. SND_SOC_DAPM_PGA("EMU Right PGA",
  710. CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_R_EN, 0, NULL, 0),
  711. SND_SOC_DAPM_PGA("EMU Left PGA",
  712. CPCAP_REG_RXOA, CPCAP_BIT_EMU_SPKR_L_EN, 0, NULL, 0),
  713. /* Headet Charge Pump */
  714. SND_SOC_DAPM_SUPPLY("Headset Charge Pump",
  715. CPCAP_REG_RXOA, CPCAP_BIT_ST_HS_CP_EN, 0, NULL, 0),
  716. /* Outputs */
  717. SND_SOC_DAPM_OUTPUT("EP"),
  718. SND_SOC_DAPM_OUTPUT("SPKR"),
  719. SND_SOC_DAPM_OUTPUT("SPKL"),
  720. SND_SOC_DAPM_OUTPUT("LINER"),
  721. SND_SOC_DAPM_OUTPUT("LINEL"),
  722. SND_SOC_DAPM_OUTPUT("HSR"),
  723. SND_SOC_DAPM_OUTPUT("HSL"),
  724. SND_SOC_DAPM_OUTPUT("EMUR"),
  725. SND_SOC_DAPM_OUTPUT("EMUL"),
  726. };
  727. static const struct snd_soc_dapm_route intercon[] = {
  728. /* Power Supply */
  729. {"HiFi PGA", NULL, "VAUDIO"},
  730. {"Voice PGA", NULL, "VAUDIO"},
  731. {"Ext Right PGA", NULL, "VAUDIO"},
  732. {"Ext Left PGA", NULL, "VAUDIO"},
  733. {"Microphone 1 PGA", NULL, "VAUDIO"},
  734. {"Microphone 2 PGA", NULL, "VAUDIO"},
  735. /* Stream -> AIF */
  736. {"HiFi RX", NULL, "HiFi Playback"},
  737. {"Voice RX", NULL, "Voice Playback"},
  738. {"Voice Capture", NULL, "Voice TX"},
  739. /* AIF clocks */
  740. {"HiFi RX", NULL, "HiFi DAI Clock"},
  741. {"Voice RX", NULL, "Voice DAI Clock"},
  742. {"Voice TX", NULL, "Voice DAI Clock"},
  743. /* Digital Loopback */
  744. {"Voice Loopback", "Switch", "Voice TX"},
  745. {"Voice RX", NULL, "Voice Loopback"},
  746. /* Highpass Filters */
  747. {"Highpass Filter RX", NULL, "Voice RX"},
  748. {"Voice TX", NULL, "Highpass Filter TX"},
  749. /* AIF -> DAC mapping */
  750. {"DAC HiFi", NULL, "HiFi RX"},
  751. {"DAC Voice", NULL, "Highpass Filter RX"},
  752. /* DAC -> PGA */
  753. {"HiFi PGA", NULL, "DAC HiFi"},
  754. {"Voice PGA", NULL, "DAC Voice"},
  755. /* Ext Input -> PGA */
  756. {"Ext Right PGA", NULL, "EXTR"},
  757. {"Ext Left PGA", NULL, "EXTL"},
  758. /* Ext PGA -> Ext Playback Switch */
  759. {"Ext Right Enable", "Switch", "Ext Right PGA"},
  760. {"Ext Left Enable", "Switch", "Ext Left PGA"},
  761. /* HiFi PGA -> Mono Mixer */
  762. {"HiFi Mono Left Mixer", NULL, "HiFi PGA"},
  763. {"HiFi Mono Left Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
  764. {"HiFi Mono Right Mixer", NULL, "HiFi PGA"},
  765. {"HiFi Mono Right Mixer", "HiFi Mono Playback Switch", "HiFi PGA"},
  766. /* Ext Playback Switch -> Ext Mono Mixer */
  767. {"Ext Mono Right Mixer", NULL, "Ext Right Enable"},
  768. {"Ext Mono Right Mixer", "Ext Mono Playback Switch", "Ext Left Enable"},
  769. {"Ext Mono Left Mixer", NULL, "Ext Left Enable"},
  770. {"Ext Mono Left Mixer", "Ext Mono Playback Switch", "Ext Right Enable"},
  771. /* HiFi Mono Mixer -> Output Route */
  772. {"Earpiece Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  773. {"Speaker Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  774. {"Speaker Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  775. {"Lineout Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  776. {"Lineout Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  777. {"Headset Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  778. {"Headset Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  779. {"EMU Right Playback Route", "HiFi", "HiFi Mono Right Mixer"},
  780. {"EMU Left Playback Route", "HiFi", "HiFi Mono Left Mixer"},
  781. /* Voice PGA -> Output Route */
  782. {"Earpiece Playback Route", "Voice", "Voice PGA"},
  783. {"Speaker Right Playback Route", "Voice", "Voice PGA"},
  784. {"Speaker Left Playback Route", "Voice", "Voice PGA"},
  785. {"Lineout Right Playback Route", "Voice", "Voice PGA"},
  786. {"Lineout Left Playback Route", "Voice", "Voice PGA"},
  787. {"Headset Right Playback Route", "Voice", "Voice PGA"},
  788. {"Headset Left Playback Route", "Voice", "Voice PGA"},
  789. {"EMU Right Playback Route", "Voice", "Voice PGA"},
  790. {"EMU Left Playback Route", "Voice", "Voice PGA"},
  791. /* Ext Mono Mixer -> Output Route */
  792. {"Earpiece Playback Route", "Ext", "Ext Mono Right Mixer"},
  793. {"Speaker Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  794. {"Speaker Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  795. {"Lineout Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  796. {"Lineout Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  797. {"Headset Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  798. {"Headset Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  799. {"EMU Right Playback Route", "Ext", "Ext Mono Right Mixer"},
  800. {"EMU Left Playback Route", "Ext", "Ext Mono Left Mixer"},
  801. /* Output Route -> Output Amplifier */
  802. {"Earpiece PGA", NULL, "Earpiece Playback Route"},
  803. {"Speaker Right PGA", NULL, "Speaker Right Playback Route"},
  804. {"Speaker Left PGA", NULL, "Speaker Left Playback Route"},
  805. {"Lineout Right PGA", NULL, "Lineout Right Playback Route"},
  806. {"Lineout Left PGA", NULL, "Lineout Left Playback Route"},
  807. {"Headset Right PGA", NULL, "Headset Right Playback Route"},
  808. {"Headset Left PGA", NULL, "Headset Left Playback Route"},
  809. {"EMU Right PGA", NULL, "EMU Right Playback Route"},
  810. {"EMU Left PGA", NULL, "EMU Left Playback Route"},
  811. /* Output Amplifier -> Output */
  812. {"EP", NULL, "Earpiece PGA"},
  813. {"SPKR", NULL, "Speaker Right PGA"},
  814. {"SPKL", NULL, "Speaker Left PGA"},
  815. {"LINER", NULL, "Lineout Right PGA"},
  816. {"LINEL", NULL, "Lineout Left PGA"},
  817. {"HSR", NULL, "Headset Right PGA"},
  818. {"HSL", NULL, "Headset Left PGA"},
  819. {"EMUR", NULL, "EMU Right PGA"},
  820. {"EMUL", NULL, "EMU Left PGA"},
  821. /* Headset Charge Pump -> Headset */
  822. {"HSR", NULL, "Headset Charge Pump"},
  823. {"HSL", NULL, "Headset Charge Pump"},
  824. /* Mic -> Mic Route */
  825. {"Right Capture Route", "Mic 1", "MICR"},
  826. {"Right Capture Route", "Headset Mic", "HSMIC"},
  827. {"Right Capture Route", "EMU Mic", "EMUMIC"},
  828. {"Right Capture Route", "Ext Right", "EXTR"},
  829. {"Left Capture Route", "Mic 2", "MICL"},
  830. {"Left Capture Route", "Ext Left", "EXTL"},
  831. /* Input Route -> Microphone PGA */
  832. {"Microphone 1 PGA", NULL, "Right Capture Route"},
  833. {"Microphone 2 PGA", NULL, "Left Capture Route"},
  834. /* Microphone PGA -> ADC */
  835. {"ADC Right", NULL, "Microphone 1 PGA"},
  836. {"ADC Left", NULL, "Microphone 2 PGA"},
  837. /* ADC -> Stream */
  838. {"Highpass Filter TX", NULL, "ADC Right"},
  839. {"Highpass Filter TX", NULL, "ADC Left"},
  840. /* Mic Bias */
  841. {"MICL", NULL, "MIC1L Bias"},
  842. {"MICR", NULL, "MIC1R Bias"},
  843. };
  844. static int cpcap_set_sysclk(struct cpcap_audio *cpcap, enum cpcap_dai dai,
  845. int clk_id, int freq)
  846. {
  847. u16 clkfreqreg, clkfreqshift;
  848. u16 clkfreqmask, clkfreqval;
  849. u16 clkidreg, clkidshift;
  850. u16 mask, val;
  851. int err;
  852. switch (dai) {
  853. case CPCAP_DAI_HIFI:
  854. clkfreqreg = CPCAP_REG_SDAC;
  855. clkfreqshift = CPCAP_BIT_ST_DAC_CLK0;
  856. clkidreg = CPCAP_REG_SDACDI;
  857. clkidshift = CPCAP_BIT_ST_DAC_CLK_IN_SEL;
  858. break;
  859. case CPCAP_DAI_VOICE:
  860. clkfreqreg = CPCAP_REG_CC;
  861. clkfreqshift = CPCAP_BIT_CDC_CLK0;
  862. clkidreg = CPCAP_REG_CDI;
  863. clkidshift = CPCAP_BIT_CLK_IN_SEL;
  864. break;
  865. default:
  866. dev_err(cpcap->component->dev, "invalid DAI: %d", dai);
  867. return -EINVAL;
  868. }
  869. /* setup clk id */
  870. if (clk_id < 0 || clk_id > 1) {
  871. dev_err(cpcap->component->dev, "invalid clk id %d", clk_id);
  872. return -EINVAL;
  873. }
  874. err = regmap_update_bits(cpcap->regmap, clkidreg, BIT(clkidshift),
  875. clk_id ? BIT(clkidshift) : 0);
  876. if (err)
  877. return err;
  878. /* enable PLL for Voice DAI */
  879. if (dai == CPCAP_DAI_VOICE) {
  880. mask = BIT(CPCAP_BIT_CDC_PLL_SEL);
  881. val = BIT(CPCAP_BIT_CDC_PLL_SEL);
  882. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  883. mask, val);
  884. if (err)
  885. return err;
  886. }
  887. /* setup frequency */
  888. clkfreqmask = 0x7 << clkfreqshift;
  889. switch (freq) {
  890. case 15360000:
  891. clkfreqval = 0x01 << clkfreqshift;
  892. break;
  893. case 16800000:
  894. clkfreqval = 0x02 << clkfreqshift;
  895. break;
  896. case 19200000:
  897. clkfreqval = 0x03 << clkfreqshift;
  898. break;
  899. case 26000000:
  900. clkfreqval = 0x04 << clkfreqshift;
  901. break;
  902. case 33600000:
  903. clkfreqval = 0x05 << clkfreqshift;
  904. break;
  905. case 38400000:
  906. clkfreqval = 0x06 << clkfreqshift;
  907. break;
  908. default:
  909. dev_err(cpcap->component->dev, "unsupported freq %u", freq);
  910. return -EINVAL;
  911. }
  912. err = regmap_update_bits(cpcap->regmap, clkfreqreg,
  913. clkfreqmask, clkfreqval);
  914. if (err)
  915. return err;
  916. if (dai == CPCAP_DAI_VOICE) {
  917. cpcap->codec_clk_id = clk_id;
  918. cpcap->codec_freq = freq;
  919. }
  920. return 0;
  921. }
  922. static int cpcap_set_samprate(struct cpcap_audio *cpcap, enum cpcap_dai dai,
  923. int samplerate)
  924. {
  925. struct snd_soc_component *component = cpcap->component;
  926. u16 sampreg, sampmask, sampshift, sampval, sampreset;
  927. int err, sampreadval;
  928. switch (dai) {
  929. case CPCAP_DAI_HIFI:
  930. sampreg = CPCAP_REG_SDAC;
  931. sampshift = CPCAP_BIT_ST_SR0;
  932. sampreset = BIT(CPCAP_BIT_DF_RESET_ST_DAC) |
  933. BIT(CPCAP_BIT_ST_CLOCK_TREE_RESET);
  934. break;
  935. case CPCAP_DAI_VOICE:
  936. sampreg = CPCAP_REG_CC;
  937. sampshift = CPCAP_BIT_CDC_SR0;
  938. sampreset = BIT(CPCAP_BIT_DF_RESET) |
  939. BIT(CPCAP_BIT_CDC_CLOCK_TREE_RESET);
  940. break;
  941. default:
  942. dev_err(component->dev, "invalid DAI: %d", dai);
  943. return -EINVAL;
  944. }
  945. sampmask = 0xF << sampshift | sampreset;
  946. switch (samplerate) {
  947. case 48000:
  948. sampval = 0x8 << sampshift;
  949. break;
  950. case 44100:
  951. sampval = 0x7 << sampshift;
  952. break;
  953. case 32000:
  954. sampval = 0x6 << sampshift;
  955. break;
  956. case 24000:
  957. sampval = 0x5 << sampshift;
  958. break;
  959. case 22050:
  960. sampval = 0x4 << sampshift;
  961. break;
  962. case 16000:
  963. sampval = 0x3 << sampshift;
  964. break;
  965. case 12000:
  966. sampval = 0x2 << sampshift;
  967. break;
  968. case 11025:
  969. sampval = 0x1 << sampshift;
  970. break;
  971. case 8000:
  972. sampval = 0x0 << sampshift;
  973. break;
  974. default:
  975. dev_err(component->dev, "unsupported samplerate %d", samplerate);
  976. return -EINVAL;
  977. }
  978. err = regmap_update_bits(cpcap->regmap, sampreg,
  979. sampmask, sampval | sampreset);
  980. if (err)
  981. return err;
  982. /* Wait for clock tree reset to complete */
  983. mdelay(CLOCK_TREE_RESET_TIME);
  984. err = regmap_read(cpcap->regmap, sampreg, &sampreadval);
  985. if (err)
  986. return err;
  987. if (sampreadval & sampreset) {
  988. dev_err(component->dev, "reset self-clear failed: %04x",
  989. sampreadval);
  990. return -EIO;
  991. }
  992. return 0;
  993. }
  994. static int cpcap_hifi_hw_params(struct snd_pcm_substream *substream,
  995. struct snd_pcm_hw_params *params,
  996. struct snd_soc_dai *dai)
  997. {
  998. struct snd_soc_component *component = dai->component;
  999. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1000. int rate = params_rate(params);
  1001. dev_dbg(component->dev, "HiFi setup HW params: rate=%d", rate);
  1002. return cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, rate);
  1003. }
  1004. static int cpcap_hifi_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  1005. unsigned int freq, int dir)
  1006. {
  1007. struct snd_soc_component *component = codec_dai->component;
  1008. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1009. struct device *dev = component->dev;
  1010. dev_dbg(dev, "HiFi setup sysclk: clk_id=%u, freq=%u", clk_id, freq);
  1011. return cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, clk_id, freq);
  1012. }
  1013. static int cpcap_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1014. unsigned int fmt)
  1015. {
  1016. struct snd_soc_component *component = codec_dai->component;
  1017. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1018. struct device *dev = component->dev;
  1019. static const u16 reg = CPCAP_REG_SDACDI;
  1020. static const u16 mask =
  1021. BIT(CPCAP_BIT_SMB_ST_DAC) |
  1022. BIT(CPCAP_BIT_ST_CLK_INV) |
  1023. BIT(CPCAP_BIT_ST_FS_INV) |
  1024. BIT(CPCAP_BIT_ST_DIG_AUD_FS0) |
  1025. BIT(CPCAP_BIT_ST_DIG_AUD_FS1) |
  1026. BIT(CPCAP_BIT_ST_L_TIMESLOT0) |
  1027. BIT(CPCAP_BIT_ST_L_TIMESLOT1) |
  1028. BIT(CPCAP_BIT_ST_L_TIMESLOT2) |
  1029. BIT(CPCAP_BIT_ST_R_TIMESLOT0) |
  1030. BIT(CPCAP_BIT_ST_R_TIMESLOT1) |
  1031. BIT(CPCAP_BIT_ST_R_TIMESLOT2);
  1032. u16 val = 0x0000;
  1033. dev_dbg(dev, "HiFi setup dai format (%08x)", fmt);
  1034. /*
  1035. * "HiFi Playback" should always be configured as
  1036. * SND_SOC_DAIFMT_CBP_CFP - codec clk & frm provider
  1037. * SND_SOC_DAIFMT_I2S - I2S mode
  1038. */
  1039. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  1040. case SND_SOC_DAIFMT_CBP_CFP:
  1041. val &= ~BIT(CPCAP_BIT_SMB_ST_DAC);
  1042. break;
  1043. default:
  1044. dev_err(dev, "HiFi dai fmt failed: CPCAP should be provider");
  1045. return -EINVAL;
  1046. }
  1047. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1048. case SND_SOC_DAIFMT_IB_IF:
  1049. val |= BIT(CPCAP_BIT_ST_FS_INV);
  1050. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1051. break;
  1052. case SND_SOC_DAIFMT_IB_NF:
  1053. val &= ~BIT(CPCAP_BIT_ST_FS_INV);
  1054. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1055. break;
  1056. case SND_SOC_DAIFMT_NB_IF:
  1057. val |= BIT(CPCAP_BIT_ST_FS_INV);
  1058. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1059. break;
  1060. case SND_SOC_DAIFMT_NB_NF:
  1061. val &= ~BIT(CPCAP_BIT_ST_FS_INV);
  1062. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1063. break;
  1064. default:
  1065. dev_err(dev, "HiFi dai fmt failed: unsupported clock invert mode");
  1066. return -EINVAL;
  1067. }
  1068. if (val & BIT(CPCAP_BIT_ST_CLK_INV))
  1069. val &= ~BIT(CPCAP_BIT_ST_CLK_INV);
  1070. else
  1071. val |= BIT(CPCAP_BIT_ST_CLK_INV);
  1072. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1073. case SND_SOC_DAIFMT_I2S:
  1074. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
  1075. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
  1076. break;
  1077. default:
  1078. /* 01 - 4 slots network mode */
  1079. val |= BIT(CPCAP_BIT_ST_DIG_AUD_FS0);
  1080. val &= ~BIT(CPCAP_BIT_ST_DIG_AUD_FS1);
  1081. /* L on slot 1 */
  1082. val |= BIT(CPCAP_BIT_ST_L_TIMESLOT0);
  1083. break;
  1084. }
  1085. dev_dbg(dev, "HiFi dai format: val=%04x", val);
  1086. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1087. }
  1088. static int cpcap_hifi_set_mute(struct snd_soc_dai *dai, int mute, int direction)
  1089. {
  1090. struct snd_soc_component *component = dai->component;
  1091. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1092. static const u16 reg = CPCAP_REG_RXSDOA;
  1093. static const u16 mask = BIT(CPCAP_BIT_ST_DAC_SW);
  1094. u16 val;
  1095. if (mute)
  1096. val = 0;
  1097. else
  1098. val = BIT(CPCAP_BIT_ST_DAC_SW);
  1099. dev_dbg(component->dev, "HiFi mute: %d", mute);
  1100. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1101. }
  1102. static const struct snd_soc_dai_ops cpcap_dai_hifi_ops = {
  1103. .hw_params = cpcap_hifi_hw_params,
  1104. .set_sysclk = cpcap_hifi_set_dai_sysclk,
  1105. .set_fmt = cpcap_hifi_set_dai_fmt,
  1106. .mute_stream = cpcap_hifi_set_mute,
  1107. .no_capture_mute = 1,
  1108. };
  1109. static int cpcap_voice_hw_params(struct snd_pcm_substream *substream,
  1110. struct snd_pcm_hw_params *params,
  1111. struct snd_soc_dai *dai)
  1112. {
  1113. struct snd_soc_component *component = dai->component;
  1114. struct device *dev = component->dev;
  1115. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1116. static const u16 reg_cdi = CPCAP_REG_CDI;
  1117. int rate = params_rate(params);
  1118. int channels = params_channels(params);
  1119. int direction = substream->stream;
  1120. u16 val, mask;
  1121. int err;
  1122. dev_dbg(dev, "Voice setup HW params: rate=%d, direction=%d, chan=%d",
  1123. rate, direction, channels);
  1124. err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, rate);
  1125. if (err)
  1126. return err;
  1127. if (direction == SNDRV_PCM_STREAM_CAPTURE) {
  1128. mask = 0x0000;
  1129. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
  1130. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT1);
  1131. mask |= BIT(CPCAP_BIT_MIC1_RX_TIMESLOT2);
  1132. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT0);
  1133. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT1);
  1134. mask |= BIT(CPCAP_BIT_MIC2_TIMESLOT2);
  1135. val = 0x0000;
  1136. if (channels >= 2)
  1137. val = BIT(CPCAP_BIT_MIC1_RX_TIMESLOT0);
  1138. err = regmap_update_bits(cpcap->regmap, reg_cdi, mask, val);
  1139. if (err)
  1140. return err;
  1141. }
  1142. return 0;
  1143. }
  1144. static int cpcap_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
  1145. unsigned int freq, int dir)
  1146. {
  1147. struct snd_soc_component *component = codec_dai->component;
  1148. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1149. dev_dbg(component->dev, "Voice setup sysclk: clk_id=%u, freq=%u",
  1150. clk_id, freq);
  1151. return cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, clk_id, freq);
  1152. }
  1153. static int cpcap_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1154. unsigned int fmt)
  1155. {
  1156. struct snd_soc_component *component = codec_dai->component;
  1157. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1158. static const u16 mask = BIT(CPCAP_BIT_SMB_CDC) |
  1159. BIT(CPCAP_BIT_CLK_INV) |
  1160. BIT(CPCAP_BIT_FS_INV) |
  1161. BIT(CPCAP_BIT_CDC_DIG_AUD_FS0) |
  1162. BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1163. u16 val = 0x0000;
  1164. int err;
  1165. dev_dbg(component->dev, "Voice setup dai format (%08x)", fmt);
  1166. /*
  1167. * "Voice Playback" and "Voice Capture" should always be
  1168. * configured as SND_SOC_DAIFMT_CBP_CFP - codec clk & frm
  1169. * provider
  1170. */
  1171. switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
  1172. case SND_SOC_DAIFMT_CBP_CFP:
  1173. val &= ~BIT(CPCAP_BIT_SMB_CDC);
  1174. break;
  1175. default:
  1176. dev_err(component->dev, "Voice dai fmt failed: CPCAP should be the provider");
  1177. val &= ~BIT(CPCAP_BIT_SMB_CDC);
  1178. break;
  1179. }
  1180. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1181. case SND_SOC_DAIFMT_IB_IF:
  1182. val |= BIT(CPCAP_BIT_CLK_INV);
  1183. val |= BIT(CPCAP_BIT_FS_INV);
  1184. break;
  1185. case SND_SOC_DAIFMT_IB_NF:
  1186. val |= BIT(CPCAP_BIT_CLK_INV);
  1187. val &= ~BIT(CPCAP_BIT_FS_INV);
  1188. break;
  1189. case SND_SOC_DAIFMT_NB_IF:
  1190. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1191. val |= BIT(CPCAP_BIT_FS_INV);
  1192. break;
  1193. case SND_SOC_DAIFMT_NB_NF:
  1194. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1195. val &= ~BIT(CPCAP_BIT_FS_INV);
  1196. break;
  1197. default:
  1198. dev_err(component->dev, "Voice dai fmt failed: unsupported clock invert mode");
  1199. break;
  1200. }
  1201. if (val & BIT(CPCAP_BIT_CLK_INV))
  1202. val &= ~BIT(CPCAP_BIT_CLK_INV);
  1203. else
  1204. val |= BIT(CPCAP_BIT_CLK_INV);
  1205. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1206. case SND_SOC_DAIFMT_I2S:
  1207. /* 11 - true I2S mode */
  1208. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
  1209. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1210. break;
  1211. default:
  1212. /* 4 timeslots network mode */
  1213. val |= BIT(CPCAP_BIT_CDC_DIG_AUD_FS0);
  1214. val &= ~BIT(CPCAP_BIT_CDC_DIG_AUD_FS1);
  1215. break;
  1216. }
  1217. dev_dbg(component->dev, "Voice dai format: val=%04x", val);
  1218. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI, mask, val);
  1219. if (err)
  1220. return err;
  1221. cpcap->codec_format = val;
  1222. return 0;
  1223. }
  1224. /*
  1225. * Configure codec for voice call if requested.
  1226. *
  1227. * We can configure most with snd_soc_dai_set_sysclk(), snd_soc_dai_set_fmt()
  1228. * and snd_soc_dai_set_tdm_slot(). This function configures the rest of the
  1229. * cpcap related hardware as CPU is not involved in the voice call.
  1230. */
  1231. static int cpcap_voice_call(struct cpcap_audio *cpcap, struct snd_soc_dai *dai,
  1232. bool voice_call)
  1233. {
  1234. int mask, err;
  1235. /* Modem to codec VAUDIO_MODE1 */
  1236. mask = BIT(CPCAP_BIT_VAUDIO_MODE1);
  1237. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_VAUDIOC,
  1238. mask, voice_call ? mask : 0);
  1239. if (err)
  1240. return err;
  1241. /* Clear MIC1_MUX for call */
  1242. mask = BIT(CPCAP_BIT_MIC1_MUX);
  1243. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  1244. mask, voice_call ? 0 : mask);
  1245. if (err)
  1246. return err;
  1247. /* Set MIC2_MUX for call */
  1248. mask = BIT(CPCAP_BIT_MB_ON1L) | BIT(CPCAP_BIT_MB_ON1R) |
  1249. BIT(CPCAP_BIT_MIC2_MUX) | BIT(CPCAP_BIT_MIC2_PGA_EN);
  1250. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_TXI,
  1251. mask, voice_call ? mask : 0);
  1252. if (err)
  1253. return err;
  1254. /* Enable LDSP for call */
  1255. mask = BIT(CPCAP_BIT_A2_LDSP_L_EN) | BIT(CPCAP_BIT_A2_LDSP_R_EN);
  1256. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXOA,
  1257. mask, voice_call ? mask : 0);
  1258. if (err)
  1259. return err;
  1260. /* Enable CPCAP_BIT_PGA_CDC_EN for call */
  1261. mask = BIT(CPCAP_BIT_PGA_CDC_EN);
  1262. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_RXCOA,
  1263. mask, voice_call ? mask : 0);
  1264. if (err)
  1265. return err;
  1266. /* Unmute voice for call */
  1267. if (dai) {
  1268. err = snd_soc_dai_digital_mute(dai, !voice_call,
  1269. SNDRV_PCM_STREAM_PLAYBACK);
  1270. if (err)
  1271. return err;
  1272. }
  1273. /* Set modem to codec mic CDC and HPF for call */
  1274. mask = BIT(CPCAP_BIT_MIC2_CDC_EN) | BIT(CPCAP_BIT_CDC_EN_RX) |
  1275. BIT(CPCAP_BIT_AUDOHPF_1) | BIT(CPCAP_BIT_AUDOHPF_0) |
  1276. BIT(CPCAP_BIT_AUDIHPF_1) | BIT(CPCAP_BIT_AUDIHPF_0);
  1277. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CC,
  1278. mask, voice_call ? mask : 0);
  1279. if (err)
  1280. return err;
  1281. /* Enable modem to codec CDC for call*/
  1282. mask = BIT(CPCAP_BIT_CDC_CLK_EN);
  1283. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  1284. mask, voice_call ? mask : 0);
  1285. return err;
  1286. }
  1287. static int cpcap_voice_set_tdm_slot(struct snd_soc_dai *dai,
  1288. unsigned int tx_mask, unsigned int rx_mask,
  1289. int slots, int slot_width)
  1290. {
  1291. struct snd_soc_component *component = dai->component;
  1292. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1293. int err, ts_mask, mask;
  1294. bool voice_call;
  1295. /*
  1296. * Primitive test for voice call, probably needs more checks
  1297. * later on for 16-bit calls detected, Bluetooth headset etc.
  1298. */
  1299. if (tx_mask == 0 && rx_mask == 1 && slot_width == 8)
  1300. voice_call = true;
  1301. else
  1302. voice_call = false;
  1303. ts_mask = 0x7 << CPCAP_BIT_MIC2_TIMESLOT0;
  1304. ts_mask |= 0x7 << CPCAP_BIT_MIC1_RX_TIMESLOT0;
  1305. mask = (tx_mask & 0x7) << CPCAP_BIT_MIC2_TIMESLOT0;
  1306. mask |= (rx_mask & 0x7) << CPCAP_BIT_MIC1_RX_TIMESLOT0;
  1307. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  1308. ts_mask, mask);
  1309. if (err)
  1310. return err;
  1311. err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, slot_width * 1000);
  1312. if (err)
  1313. return err;
  1314. err = cpcap_voice_call(cpcap, dai, voice_call);
  1315. if (err)
  1316. return err;
  1317. return 0;
  1318. }
  1319. static int cpcap_voice_set_mute(struct snd_soc_dai *dai, int mute, int direction)
  1320. {
  1321. struct snd_soc_component *component = dai->component;
  1322. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1323. static const u16 reg = CPCAP_REG_RXCOA;
  1324. static const u16 mask = BIT(CPCAP_BIT_CDC_SW);
  1325. u16 val;
  1326. if (mute)
  1327. val = 0;
  1328. else
  1329. val = BIT(CPCAP_BIT_CDC_SW);
  1330. dev_dbg(component->dev, "Voice mute: %d", mute);
  1331. return regmap_update_bits(cpcap->regmap, reg, mask, val);
  1332. };
  1333. static const struct snd_soc_dai_ops cpcap_dai_voice_ops = {
  1334. .hw_params = cpcap_voice_hw_params,
  1335. .set_sysclk = cpcap_voice_set_dai_sysclk,
  1336. .set_fmt = cpcap_voice_set_dai_fmt,
  1337. .set_tdm_slot = cpcap_voice_set_tdm_slot,
  1338. .mute_stream = cpcap_voice_set_mute,
  1339. .no_capture_mute = 1,
  1340. };
  1341. static struct snd_soc_dai_driver cpcap_dai[] = {
  1342. {
  1343. .id = 0,
  1344. .name = "cpcap-hifi",
  1345. .playback = {
  1346. .stream_name = "HiFi Playback",
  1347. .channels_min = 2,
  1348. .channels_max = 2,
  1349. .rates = SNDRV_PCM_RATE_8000_48000,
  1350. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,
  1351. },
  1352. .ops = &cpcap_dai_hifi_ops,
  1353. },
  1354. {
  1355. .id = 1,
  1356. .name = "cpcap-voice",
  1357. .playback = {
  1358. .stream_name = "Voice Playback",
  1359. .channels_min = 1,
  1360. .channels_max = 1,
  1361. .rates = SNDRV_PCM_RATE_8000_48000,
  1362. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1363. },
  1364. .capture = {
  1365. .stream_name = "Voice Capture",
  1366. .channels_min = 1,
  1367. .channels_max = 2,
  1368. .rates = SNDRV_PCM_RATE_8000_48000,
  1369. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1370. },
  1371. .ops = &cpcap_dai_voice_ops,
  1372. },
  1373. };
  1374. static int cpcap_dai_mux(struct cpcap_audio *cpcap, bool swap_dai_configuration)
  1375. {
  1376. u16 hifi_val, voice_val;
  1377. u16 hifi_mask = BIT(CPCAP_BIT_DIG_AUD_IN_ST_DAC);
  1378. u16 voice_mask = BIT(CPCAP_BIT_DIG_AUD_IN);
  1379. int err;
  1380. if (!swap_dai_configuration) {
  1381. /* Codec on DAI0, HiFi on DAI1 */
  1382. voice_val = 0;
  1383. hifi_val = hifi_mask;
  1384. } else {
  1385. /* Codec on DAI1, HiFi on DAI0 */
  1386. voice_val = voice_mask;
  1387. hifi_val = 0;
  1388. }
  1389. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_CDI,
  1390. voice_mask, voice_val);
  1391. if (err)
  1392. return err;
  1393. err = regmap_update_bits(cpcap->regmap, CPCAP_REG_SDACDI,
  1394. hifi_mask, hifi_val);
  1395. if (err)
  1396. return err;
  1397. return 0;
  1398. }
  1399. static int cpcap_audio_reset(struct snd_soc_component *component,
  1400. bool swap_dai_configuration)
  1401. {
  1402. struct cpcap_audio *cpcap = snd_soc_component_get_drvdata(component);
  1403. int i, err = 0;
  1404. dev_dbg(component->dev, "init audio codec");
  1405. for (i = 0; i < ARRAY_SIZE(cpcap_default_regs); i++) {
  1406. err = regmap_update_bits(cpcap->regmap,
  1407. cpcap_default_regs[i].reg,
  1408. cpcap_default_regs[i].mask,
  1409. cpcap_default_regs[i].val);
  1410. if (err)
  1411. return err;
  1412. }
  1413. /* setup default settings */
  1414. err = cpcap_dai_mux(cpcap, swap_dai_configuration);
  1415. if (err)
  1416. return err;
  1417. err = cpcap_set_sysclk(cpcap, CPCAP_DAI_HIFI, 0, 26000000);
  1418. if (err)
  1419. return err;
  1420. err = cpcap_set_sysclk(cpcap, CPCAP_DAI_VOICE, 0, 26000000);
  1421. if (err)
  1422. return err;
  1423. err = cpcap_set_samprate(cpcap, CPCAP_DAI_HIFI, 48000);
  1424. if (err)
  1425. return err;
  1426. err = cpcap_set_samprate(cpcap, CPCAP_DAI_VOICE, 48000);
  1427. if (err)
  1428. return err;
  1429. return 0;
  1430. }
  1431. static int cpcap_soc_probe(struct snd_soc_component *component)
  1432. {
  1433. struct cpcap_audio *cpcap;
  1434. int err;
  1435. cpcap = devm_kzalloc(component->dev, sizeof(*cpcap), GFP_KERNEL);
  1436. if (!cpcap)
  1437. return -ENOMEM;
  1438. snd_soc_component_set_drvdata(component, cpcap);
  1439. cpcap->component = component;
  1440. cpcap->regmap = dev_get_regmap(component->dev->parent, NULL);
  1441. if (!cpcap->regmap)
  1442. return -ENODEV;
  1443. snd_soc_component_init_regmap(component, cpcap->regmap);
  1444. err = cpcap_get_vendor(component->dev, cpcap->regmap, &cpcap->vendor);
  1445. if (err)
  1446. return err;
  1447. return cpcap_audio_reset(component, false);
  1448. }
  1449. static struct snd_soc_component_driver soc_codec_dev_cpcap = {
  1450. .probe = cpcap_soc_probe,
  1451. .controls = cpcap_snd_controls,
  1452. .num_controls = ARRAY_SIZE(cpcap_snd_controls),
  1453. .dapm_widgets = cpcap_dapm_widgets,
  1454. .num_dapm_widgets = ARRAY_SIZE(cpcap_dapm_widgets),
  1455. .dapm_routes = intercon,
  1456. .num_dapm_routes = ARRAY_SIZE(intercon),
  1457. .idle_bias_on = 1,
  1458. .use_pmdown_time = 1,
  1459. .endianness = 1,
  1460. };
  1461. static int cpcap_codec_probe(struct platform_device *pdev)
  1462. {
  1463. struct device_node *codec_node =
  1464. of_get_child_by_name(pdev->dev.parent->of_node, "audio-codec");
  1465. if (!codec_node)
  1466. return -ENODEV;
  1467. pdev->dev.of_node = codec_node;
  1468. return devm_snd_soc_register_component(&pdev->dev, &soc_codec_dev_cpcap,
  1469. cpcap_dai, ARRAY_SIZE(cpcap_dai));
  1470. }
  1471. static struct platform_driver cpcap_codec_driver = {
  1472. .probe = cpcap_codec_probe,
  1473. .driver = {
  1474. .name = "cpcap-codec",
  1475. },
  1476. };
  1477. module_platform_driver(cpcap_codec_driver);
  1478. MODULE_ALIAS("platform:cpcap-codec");
  1479. MODULE_DESCRIPTION("ASoC CPCAP codec driver");
  1480. MODULE_AUTHOR("Sebastian Reichel");
  1481. MODULE_LICENSE("GPL v2");