ac97c.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
  4. *
  5. * (c) 2011 Manuel Lauss <[email protected]>
  6. *
  7. * based on the old ALSA driver originally written by
  8. * Charles Eidsness <[email protected]>
  9. */
  10. #include <linux/init.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/device.h>
  14. #include <linux/delay.h>
  15. #include <linux/mutex.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/suspend.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/initval.h>
  21. #include <sound/soc.h>
  22. #include <asm/mach-au1x00/au1000.h>
  23. #include "psc.h"
  24. /* register offsets and bits */
  25. #define AC97_CONFIG 0x00
  26. #define AC97_STATUS 0x04
  27. #define AC97_DATA 0x08
  28. #define AC97_CMDRESP 0x0c
  29. #define AC97_ENABLE 0x10
  30. #define CFG_RC(x) (((x) & 0x3ff) << 13) /* valid rx slots mask */
  31. #define CFG_XS(x) (((x) & 0x3ff) << 3) /* valid tx slots mask */
  32. #define CFG_SG (1 << 2) /* sync gate */
  33. #define CFG_SN (1 << 1) /* sync control */
  34. #define CFG_RS (1 << 0) /* acrst# control */
  35. #define STAT_XU (1 << 11) /* tx underflow */
  36. #define STAT_XO (1 << 10) /* tx overflow */
  37. #define STAT_RU (1 << 9) /* rx underflow */
  38. #define STAT_RO (1 << 8) /* rx overflow */
  39. #define STAT_RD (1 << 7) /* codec ready */
  40. #define STAT_CP (1 << 6) /* command pending */
  41. #define STAT_TE (1 << 4) /* tx fifo empty */
  42. #define STAT_TF (1 << 3) /* tx fifo full */
  43. #define STAT_RE (1 << 1) /* rx fifo empty */
  44. #define STAT_RF (1 << 0) /* rx fifo full */
  45. #define CMD_SET_DATA(x) (((x) & 0xffff) << 16)
  46. #define CMD_GET_DATA(x) ((x) & 0xffff)
  47. #define CMD_READ (1 << 7)
  48. #define CMD_WRITE (0 << 7)
  49. #define CMD_IDX(x) ((x) & 0x7f)
  50. #define EN_D (1 << 1) /* DISable bit */
  51. #define EN_CE (1 << 0) /* clock enable bit */
  52. /* how often to retry failed codec register reads/writes */
  53. #define AC97_RW_RETRIES 5
  54. #define AC97_RATES \
  55. SNDRV_PCM_RATE_CONTINUOUS
  56. #define AC97_FMTS \
  57. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE)
  58. /* instance data. There can be only one, MacLeod!!!!, fortunately there IS only
  59. * once AC97C on early Alchemy chips. The newer ones aren't so lucky.
  60. */
  61. static struct au1xpsc_audio_data *ac97c_workdata;
  62. #define ac97_to_ctx(x) ac97c_workdata
  63. static inline unsigned long RD(struct au1xpsc_audio_data *ctx, int reg)
  64. {
  65. return __raw_readl(ctx->mmio + reg);
  66. }
  67. static inline void WR(struct au1xpsc_audio_data *ctx, int reg, unsigned long v)
  68. {
  69. __raw_writel(v, ctx->mmio + reg);
  70. wmb();
  71. }
  72. static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97,
  73. unsigned short r)
  74. {
  75. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  76. unsigned int tmo, retry;
  77. unsigned long data;
  78. data = ~0;
  79. retry = AC97_RW_RETRIES;
  80. do {
  81. mutex_lock(&ctx->lock);
  82. tmo = 6;
  83. while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
  84. udelay(21); /* wait an ac97 frame time */
  85. if (!tmo) {
  86. pr_debug("ac97rd timeout #1\n");
  87. goto next;
  88. }
  89. WR(ctx, AC97_CMDRESP, CMD_IDX(r) | CMD_READ);
  90. /* stupid errata: data is only valid for 21us, so
  91. * poll, Forrest, poll...
  92. */
  93. tmo = 0x10000;
  94. while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo)
  95. asm volatile ("nop");
  96. data = RD(ctx, AC97_CMDRESP);
  97. if (!tmo)
  98. pr_debug("ac97rd timeout #2\n");
  99. next:
  100. mutex_unlock(&ctx->lock);
  101. } while (--retry && !tmo);
  102. pr_debug("AC97RD %04x %04lx %d\n", r, data, retry);
  103. return retry ? data & 0xffff : 0xffff;
  104. }
  105. static void au1xac97c_ac97_write(struct snd_ac97 *ac97, unsigned short r,
  106. unsigned short v)
  107. {
  108. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  109. unsigned int tmo, retry;
  110. retry = AC97_RW_RETRIES;
  111. do {
  112. mutex_lock(&ctx->lock);
  113. for (tmo = 5; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
  114. udelay(21);
  115. if (!tmo) {
  116. pr_debug("ac97wr timeout #1\n");
  117. goto next;
  118. }
  119. WR(ctx, AC97_CMDRESP, CMD_WRITE | CMD_IDX(r) | CMD_SET_DATA(v));
  120. for (tmo = 10; (RD(ctx, AC97_STATUS) & STAT_CP) && tmo; tmo--)
  121. udelay(21);
  122. if (!tmo)
  123. pr_debug("ac97wr timeout #2\n");
  124. next:
  125. mutex_unlock(&ctx->lock);
  126. } while (--retry && !tmo);
  127. pr_debug("AC97WR %04x %04x %d\n", r, v, retry);
  128. }
  129. static void au1xac97c_ac97_warm_reset(struct snd_ac97 *ac97)
  130. {
  131. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  132. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG | CFG_SN);
  133. msleep(20);
  134. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_SG);
  135. WR(ctx, AC97_CONFIG, ctx->cfg);
  136. }
  137. static void au1xac97c_ac97_cold_reset(struct snd_ac97 *ac97)
  138. {
  139. struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97);
  140. int i;
  141. WR(ctx, AC97_CONFIG, ctx->cfg | CFG_RS);
  142. msleep(500);
  143. WR(ctx, AC97_CONFIG, ctx->cfg);
  144. /* wait for codec ready */
  145. i = 50;
  146. while (((RD(ctx, AC97_STATUS) & STAT_RD) == 0) && --i)
  147. msleep(20);
  148. if (!i)
  149. printk(KERN_ERR "ac97c: codec not ready after cold reset\n");
  150. }
  151. /* AC97 controller operations */
  152. static struct snd_ac97_bus_ops ac97c_bus_ops = {
  153. .read = au1xac97c_ac97_read,
  154. .write = au1xac97c_ac97_write,
  155. .reset = au1xac97c_ac97_cold_reset,
  156. .warm_reset = au1xac97c_ac97_warm_reset,
  157. };
  158. static int alchemy_ac97c_startup(struct snd_pcm_substream *substream,
  159. struct snd_soc_dai *dai)
  160. {
  161. struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai);
  162. snd_soc_dai_set_dma_data(dai, substream, &ctx->dmaids[0]);
  163. return 0;
  164. }
  165. static const struct snd_soc_dai_ops alchemy_ac97c_ops = {
  166. .startup = alchemy_ac97c_startup,
  167. };
  168. static int au1xac97c_dai_probe(struct snd_soc_dai *dai)
  169. {
  170. return ac97c_workdata ? 0 : -ENODEV;
  171. }
  172. static struct snd_soc_dai_driver au1xac97c_dai_driver = {
  173. .name = "alchemy-ac97c",
  174. .probe = au1xac97c_dai_probe,
  175. .playback = {
  176. .rates = AC97_RATES,
  177. .formats = AC97_FMTS,
  178. .channels_min = 2,
  179. .channels_max = 2,
  180. },
  181. .capture = {
  182. .rates = AC97_RATES,
  183. .formats = AC97_FMTS,
  184. .channels_min = 2,
  185. .channels_max = 2,
  186. },
  187. .ops = &alchemy_ac97c_ops,
  188. };
  189. static const struct snd_soc_component_driver au1xac97c_component = {
  190. .name = "au1xac97c",
  191. .legacy_dai_naming = 1,
  192. };
  193. static int au1xac97c_drvprobe(struct platform_device *pdev)
  194. {
  195. int ret;
  196. struct resource *iores, *dmares;
  197. struct au1xpsc_audio_data *ctx;
  198. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  199. if (!ctx)
  200. return -ENOMEM;
  201. mutex_init(&ctx->lock);
  202. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  203. if (!iores)
  204. return -ENODEV;
  205. if (!devm_request_mem_region(&pdev->dev, iores->start,
  206. resource_size(iores),
  207. pdev->name))
  208. return -EBUSY;
  209. ctx->mmio = devm_ioremap(&pdev->dev, iores->start,
  210. resource_size(iores));
  211. if (!ctx->mmio)
  212. return -EBUSY;
  213. dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  214. if (!dmares)
  215. return -EBUSY;
  216. ctx->dmaids[SNDRV_PCM_STREAM_PLAYBACK] = dmares->start;
  217. dmares = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  218. if (!dmares)
  219. return -EBUSY;
  220. ctx->dmaids[SNDRV_PCM_STREAM_CAPTURE] = dmares->start;
  221. /* switch it on */
  222. WR(ctx, AC97_ENABLE, EN_D | EN_CE);
  223. WR(ctx, AC97_ENABLE, EN_CE);
  224. ctx->cfg = CFG_RC(3) | CFG_XS(3);
  225. WR(ctx, AC97_CONFIG, ctx->cfg);
  226. platform_set_drvdata(pdev, ctx);
  227. ret = snd_soc_set_ac97_ops(&ac97c_bus_ops);
  228. if (ret)
  229. return ret;
  230. ret = snd_soc_register_component(&pdev->dev, &au1xac97c_component,
  231. &au1xac97c_dai_driver, 1);
  232. if (ret)
  233. return ret;
  234. ac97c_workdata = ctx;
  235. return 0;
  236. }
  237. static int au1xac97c_drvremove(struct platform_device *pdev)
  238. {
  239. struct au1xpsc_audio_data *ctx = platform_get_drvdata(pdev);
  240. snd_soc_unregister_component(&pdev->dev);
  241. WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
  242. ac97c_workdata = NULL; /* MDEV */
  243. return 0;
  244. }
  245. #ifdef CONFIG_PM
  246. static int au1xac97c_drvsuspend(struct device *dev)
  247. {
  248. struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
  249. WR(ctx, AC97_ENABLE, EN_D); /* clock off, disable */
  250. return 0;
  251. }
  252. static int au1xac97c_drvresume(struct device *dev)
  253. {
  254. struct au1xpsc_audio_data *ctx = dev_get_drvdata(dev);
  255. WR(ctx, AC97_ENABLE, EN_D | EN_CE);
  256. WR(ctx, AC97_ENABLE, EN_CE);
  257. WR(ctx, AC97_CONFIG, ctx->cfg);
  258. return 0;
  259. }
  260. static const struct dev_pm_ops au1xpscac97_pmops = {
  261. .suspend = au1xac97c_drvsuspend,
  262. .resume = au1xac97c_drvresume,
  263. };
  264. #define AU1XPSCAC97_PMOPS (&au1xpscac97_pmops)
  265. #else
  266. #define AU1XPSCAC97_PMOPS NULL
  267. #endif
  268. static struct platform_driver au1xac97c_driver = {
  269. .driver = {
  270. .name = "alchemy-ac97c",
  271. .pm = AU1XPSCAC97_PMOPS,
  272. },
  273. .probe = au1xac97c_drvprobe,
  274. .remove = au1xac97c_drvremove,
  275. };
  276. module_platform_driver(au1xac97c_driver);
  277. MODULE_LICENSE("GPL");
  278. MODULE_DESCRIPTION("Au1000/1500/1100 AC97C ASoC driver");
  279. MODULE_AUTHOR("Manuel Lauss");