qcom-dma-mapping.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  4. & Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. /*
  7. * DMA_ATTR_NO_DELAYED_UNMAP: Used by msm specific lazy mapping to indicate
  8. * that the mapping can be freed on unmap, rather than when the ion_buffer
  9. * is freed.
  10. */
  11. #define DMA_ATTR_NO_DELAYED_UNMAP (1UL << 13)
  12. /*
  13. * When passed to a DMA map call the DMA_ATTR_FORCE_COHERENT DMA
  14. * attribute can be used to force a buffer to be mapped as IO coherent.
  15. */
  16. #define DMA_ATTR_FORCE_COHERENT (1UL << 15)
  17. /*
  18. * When passed to a DMA map call the DMA_ATTR_FORCE_NON_COHERENT DMA
  19. * attribute can be used to force a buffer to not be mapped as IO
  20. * coherent.
  21. */
  22. #define DMA_ATTR_FORCE_NON_COHERENT (1UL << 16)
  23. /*
  24. * DMA_ATTR_DELAYED_UNMAP: Used by ION, it will ensure that mappings are not
  25. * removed on unmap but instead are removed when the ion_buffer is freed.
  26. */
  27. #define DMA_ATTR_DELAYED_UNMAP (1UL << 17)
  28. /*
  29. * DMA_ATTR_QTI_SMMU_PROXY_MAP : Map this buffer in the TVM SMMU if supported
  30. * on the target.
  31. */
  32. #define DMA_ATTR_QTI_SMMU_PROXY_MAP (1UL << 18)
  33. #ifndef DMA_ATTR_SYS_CACHE_ONLY
  34. /* Attributes are not supported, so render them ineffective. */
  35. #define DMA_ATTR_SYS_CACHE_ONLY (0UL)
  36. #define DMA_ATTR_SYS_CACHE_ONLY_NWA (0UL)
  37. #endif
  38. /*
  39. * DMA_ATTR_IOMMU_USE_UPSTREAM_HINT: Normally an smmu will override any bus
  40. * attributes (i.e cacheablilty) provided by the client device. Some hardware
  41. * may be designed to use the original attributes instead.
  42. */
  43. #define DMA_ATTR_IOMMU_USE_UPSTREAM_HINT (DMA_ATTR_SYS_CACHE_ONLY)
  44. /*
  45. * DMA_ATTR_IOMMU_USE_LLC_NWA: Overrides the bus attributes to use the System
  46. * Cache(LLC) with allocation policy as Inner Non-Cacheable, Outer Cacheable:
  47. * Write-Back, Read-Allocate, No Write-Allocate policy.
  48. */
  49. #define DMA_ATTR_IOMMU_USE_LLC_NWA (DMA_ATTR_SYS_CACHE_ONLY_NWA)