msm_gpi.h 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef __MSM_GPI_H_
  7. #define __MSM_GPI_H_
  8. #include <linux/types.h>
  9. struct __packed msm_gpi_tre {
  10. u32 dword[4];
  11. };
  12. enum GPI_EV_TYPE {
  13. XFER_COMPLETE_EV_TYPE = 0x22,
  14. IMMEDIATE_DATA_EV_TYPE = 0x30,
  15. QUP_NOTIF_EV_TYPE = 0x31,
  16. STALE_EV_TYPE = 0xFF,
  17. QUP_TCE_TYPE_Q2SPI_STATUS = 0x35,
  18. QUP_TCE_TYPE_Q2SPI_CR_HEADER = 0x36,
  19. };
  20. enum msm_gpi_tre_type {
  21. MSM_GPI_TRE_INVALID = 0x00,
  22. MSM_GPI_TRE_NOP = 0x01,
  23. MSM_GPI_TRE_DMA_W_BUF = 0x10,
  24. MSM_GPI_TRE_DMA_IMMEDIATE = 0x11,
  25. MSM_GPI_TRE_DMA_W_SG_LIST = 0x12,
  26. MSM_GPI_TRE_GO = 0x20,
  27. MSM_GPI_TRE_CONFIG0 = 0x22,
  28. MSM_GPI_TRE_CONFIG1 = 0x23,
  29. MSM_GPI_TRE_CONFIG2 = 0x24,
  30. MSM_GPI_TRE_CONFIG3 = 0x25,
  31. MSM_GPI_TRE_LOCK = 0x30,
  32. MSM_GPI_TRE_UNLOCK = 0x31,
  33. };
  34. #define MSM_GPI_TRE_TYPE(tre) ((tre->dword[3] >> 16) & 0xFF)
  35. /* Lock TRE */
  36. #define MSM_GPI_LOCK_TRE_DWORD0 (0)
  37. #define MSM_GPI_LOCK_TRE_DWORD1 (0)
  38. #define MSM_GPI_LOCK_TRE_DWORD2 (0)
  39. #define MSM_GPI_LOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  40. ((0x3 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
  41. (ieot << 9) | (ieob << 8) | ch)
  42. /* Unlock TRE */
  43. #define MSM_GPI_UNLOCK_TRE_DWORD0 (0)
  44. #define MSM_GPI_UNLOCK_TRE_DWORD1 (0)
  45. #define MSM_GPI_UNLOCK_TRE_DWORD2 (0)
  46. #define MSM_GPI_UNLOCK_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  47. ((0x3 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
  48. (ieot << 9) | (ieob << 8) | ch)
  49. /* DMA w. Buffer TRE */
  50. #ifdef CONFIG_ARM64
  51. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) ((u32)ptr)
  52. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
  53. #else
  54. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD0(ptr) (ptr)
  55. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD1(ptr) 0
  56. #endif
  57. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length) (length & 0xFFFFFF)
  58. #define MSM_GPI_DMA_W_BUFFER_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  59. ((0x1 << 20) | (0x0 << 16) | (link_rx << 11) | (bei << 10) | \
  60. (ieot << 9) | (ieob << 8) | ch)
  61. #define MSM_GPI_DMA_W_BUFFER_TRE_GET_LEN(tre) (tre->dword[2] & 0xFFFFFF)
  62. #define MSM_GPI_DMA_W_BUFFER_TRE_SET_LEN(tre, length) (tre->dword[2] = \
  63. MSM_GPI_DMA_W_BUFFER_TRE_DWORD2(length))
  64. /* DMA Immediate TRE */
  65. #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD0(d3, d2, d1, d0) ((d3 << 24) | \
  66. (d2 << 16) | (d1 << 8) | (d0))
  67. #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD1(d4, d5, d6, d7) ((d7 << 24) | \
  68. (d6 << 16) | (d5 << 8) | (d4))
  69. #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD2(length) (length & 0xF)
  70. #define MSM_GPI_DMA_IMMEDIATE_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  71. ((0x1 << 20) | (0x1 << 16) | (link_rx << 11) | (bei << 10) | \
  72. (ieot << 9) | (ieob << 8) | ch)
  73. #define MSM_GPI_DMA_IMMEDIATE_TRE_GET_LEN(tre) (tre->dword[2] & 0xF)
  74. /* DMA w. Scatter/Gather List TRE */
  75. #ifdef CONFIG_ARM64
  76. #define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) ((u32)ptr)
  77. #define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) ((u32)(ptr >> 32))
  78. #else
  79. #define MSM_GPI_SG_LIST_TRE_DWORD0(ptr) (ptr)
  80. #define MSM_GPI_SG_LIST_TRE_DWORD1(ptr) 0
  81. #endif
  82. #define MSM_GPI_SG_LIST_TRE_DWORD2(length) (length & 0xFFFF)
  83. #define MSM_GPI_SG_LIST_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x1 << 20) \
  84. | (0x2 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  85. (ieob << 8) | ch)
  86. /* SG Element */
  87. #ifdef CONFIG_ARM64
  88. #define MSM_GPI_SG_ELEMENT_DWORD0(ptr) ((u32)ptr)
  89. #define MSM_GPI_SG_ELEMENT_DWORD1(ptr) ((u32)(ptr >> 32))
  90. #else
  91. #define MSM_GPI_SG_ELEMENT_DWORD0(ptr) (ptr)
  92. #define MSM_GPI_SG_ELEMENT_DWORD1(ptr) 0
  93. #endif
  94. #define MSM_GSI_SG_ELEMENT_DWORD2(length) (length & 0xFFFFF)
  95. #define MSM_GSI_SG_ELEMENT_DWORD3 (0)
  96. /* Config2 TRE */
  97. #define GPI_CONFIG2_TRE_DWORD0(gr, txp) ((gr << 20) | (txp))
  98. #define GPI_CONFIG2_TRE_DWORD1(txp) (txp)
  99. #define GPI_CONFIG2_TRE_DWORD2 (0)
  100. #define GPI_CONFIG2_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
  101. (0x4 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  102. (ieob << 8) | ch)
  103. /* Config3 TRE */
  104. #define GPI_CONFIG3_TRE_DWORD0(rxp) (rxp)
  105. #define GPI_CONFIG3_TRE_DWORD1(rxp) (rxp)
  106. #define GPI_CONFIG3_TRE_DWORD2 (0)
  107. #define GPI_CONFIG3_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
  108. | (0x5 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  109. (ieob << 8) | ch)
  110. /* SPI Go TRE */
  111. #define MSM_GPI_SPI_GO_TRE_DWORD0(flags, cs, command) ((flags << 24) | \
  112. (cs << 8) | command)
  113. #define MSM_GPI_SPI_GO_TRE_DWORD1 (0)
  114. #define MSM_GPI_SPI_GO_TRE_DWORD2(rx_len) (rx_len)
  115. #define MSM_GPI_SPI_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
  116. (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  117. (ieob << 8) | ch)
  118. /* SPI Config0 TRE */
  119. #define MSM_GPI_SPI_CONFIG0_TRE_DWORD0(pack, flags, word_size) ((pack << 24) | \
  120. (flags << 8) | word_size)
  121. #define MSM_GPI_SPI_CONFIG0_TRE_DWORD1(it_del, cs_clk_del, iw_del) \
  122. ((it_del << 16) | (cs_clk_del << 8) | iw_del)
  123. #define MSM_GPI_SPI_CONFIG0_TRE_DWORD2(clk_src, clk_div) ((clk_src << 16) | \
  124. clk_div)
  125. #define MSM_GPI_SPI_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  126. ((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
  127. (ieot << 9) | (ieob << 8) | ch)
  128. /* UART Go TRE */
  129. #define MSM_GPI_UART_GO_TRE_DWORD0(en_hunt, command) ((en_hunt << 8) | command)
  130. #define MSM_GPI_UART_GO_TRE_DWORD1 (0)
  131. #define MSM_GPI_UART_GO_TRE_DWORD2 (0)
  132. #define MSM_GPI_UART_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) \
  133. | (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  134. (ieob << 8) | ch)
  135. /* UART Config0 TRE */
  136. #define MSM_GPI_UART_CONFIG0_TRE_DWORD0(pack, hunt, flags, parity, sbl, size) \
  137. ((pack << 24) | (hunt << 16) | (flags << 8) | (parity << 5) | \
  138. (sbl << 3) | size)
  139. #define MSM_GPI_UART_CONFIG0_TRE_DWORD1(rfr_level, rx_stale) \
  140. ((rfr_level << 24) | rx_stale)
  141. #define MSM_GPI_UART_CONFIG0_TRE_DWORD2(clk_source, clk_div) \
  142. ((clk_source << 16) | clk_div)
  143. #define MSM_GPI_UART_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  144. ((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
  145. (ieot << 9) | (ieob << 8) | ch)
  146. /* I2C GO TRE */
  147. #define MSM_GPI_I2C_GO_TRE_DWORD0(flags, slave, opcode) \
  148. ((flags << 24) | (slave << 8) | opcode)
  149. #define MSM_GPI_I2C_GO_TRE_DWORD1 (0)
  150. #define MSM_GPI_I2C_GO_TRE_DWORD2(rx_len) (rx_len)
  151. #define MSM_GPI_I2C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
  152. (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  153. (ieob << 8) | ch)
  154. /* I2C Config0 TRE */
  155. #define MSM_GPI_I2C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
  156. ((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
  157. #define MSM_GPI_I2C_CONFIG0_TRE_DWORD1(inter_delay, noise_rej) \
  158. ((inter_delay << 16) | noise_rej)
  159. #define MSM_GPI_I2C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
  160. ((clk_src << 16) | clk_div)
  161. #define MSM_GPI_I2C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  162. ((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
  163. (ieot << 9) | (ieob << 8) | ch)
  164. /* I3C GO TRE */
  165. #define MSM_GPI_I3C_GO_TRE_DWORD0(flags, ccc_hdr, slave, opcode) \
  166. ((flags << 24) | (ccc_hdr << 16) | (slave << 8) | opcode)
  167. #define MSM_GPI_I3C_GO_TRE_DWORD1(flags) (flags)
  168. #define MSM_GPI_I3C_GO_TRE_DWORD2(rx_len) (rx_len)
  169. #define MSM_GPI_I3C_GO_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) ((0x2 << 20) | \
  170. (0x0 << 16) | (link_rx << 11) | (bei << 10) | (ieot << 9) | \
  171. (ieob << 8) | ch)
  172. /* I3C Config0 TRE */
  173. #define MSM_GPI_I3C_CONFIG0_TRE_DWORD0(pack, t_cycle, t_high, t_low) \
  174. ((pack << 24) | (t_cycle << 16) | (t_high << 8) | t_low)
  175. #define MSM_GPI_I3C_CONFIG0_TRE_DWORD1(inter_delay, t_cycle, t_high) \
  176. ((inter_delay << 16) | (t_cycle << 8) | t_high)
  177. #define MSM_GPI_I3C_CONFIG0_TRE_DWORD2(clk_src, clk_div) \
  178. ((clk_src << 16) | clk_div)
  179. #define MSM_GPI_I3C_CONFIG0_TRE_DWORD3(link_rx, bei, ieot, ieob, ch) \
  180. ((0x2 << 20) | (0x2 << 16) | (link_rx << 11) | (bei << 10) | \
  181. (ieot << 9) | (ieob << 8) | ch)
  182. #ifdef CONFIG_ARM64
  183. #define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) ((u32)(ptr >> 32))
  184. #else
  185. #define MSM_GPI_RING_PHYS_ADDR_UPPER(ptr) 0
  186. #endif
  187. /* Static GPII here uses bit5 bit4 bit3 bit2 bit1(xxx1 111x) */
  188. #define STATIC_GPII_BMSK (0x1e)
  189. #define STATIC_GPII_SHFT (0x1)
  190. #define GPI_EV_PRIORITY_BMSK (0x1)
  191. #define GSI_SE_ERR(log_ctx, print, dev, x...) do { \
  192. ipc_log_string(log_ctx, x); \
  193. if (print) { \
  194. if (dev) \
  195. dev_err((dev), x); \
  196. else \
  197. pr_err(x); \
  198. } \
  199. } while (0)
  200. #define GSI_SE_DBG(log_ctx, print, dev, x...) do { \
  201. ipc_log_string(log_ctx, x); \
  202. if (print) { \
  203. if (dev) \
  204. dev_dbg((dev), x); \
  205. else \
  206. pr_debug(x); \
  207. } \
  208. } while (0)
  209. #define LOCK_TRE_SET BIT(0)
  210. #define CONFIG_TRE_SET BIT(1)
  211. #define GO_TRE_SET BIT(2)
  212. #define DMA_TRE_SET BIT(3)
  213. #define UNLOCK_TRE_SET BIT(4)
  214. #define GSI_MAX_TRE_TYPES (5)
  215. #define GSI_MAX_NUM_TRE_MSGS (448)
  216. #define GSI_MAX_IMMEDIATE_DMA_LEN (8)
  217. /* cmds to perform by using dmaengine_slave_config() */
  218. enum msm_gpi_ctrl_cmd {
  219. MSM_GPI_DEFAULT,
  220. MSM_GPI_INIT,
  221. MSM_GPI_CMD_UART_SW_STALE,
  222. MSM_GPI_CMD_UART_RFR_READY,
  223. MSM_GPI_CMD_UART_RFR_NOT_READY,
  224. MSM_GPI_DEEP_SLEEP_INIT,
  225. };
  226. enum msm_gpi_cb_event {
  227. /* These events are hardware generated events */
  228. MSM_GPI_QUP_NOTIFY,
  229. MSM_GPI_QUP_ERROR, /* global error */
  230. MSM_GPI_QUP_CH_ERROR, /* channel specific error */
  231. MSM_GPI_QUP_FW_ERROR, /* unhandled error */
  232. /* These events indicate a software bug */
  233. MSM_GPI_QUP_PENDING_EVENT,
  234. MSM_GPI_QUP_EOT_DESC_MISMATCH,
  235. MSM_GPI_QUP_SW_ERROR,
  236. MSM_GPI_QUP_CR_HEADER,
  237. MSM_GPI_QUP_MAX_EVENT,
  238. };
  239. struct msm_gpi_error_log {
  240. u32 routine;
  241. u32 type;
  242. u32 error_code;
  243. };
  244. struct __packed qup_q2spi_cr_header_event {
  245. u8 cr_hdr[4];
  246. u8 cr_ed_byte[4];
  247. u32 reserved0 : 24;
  248. u8 code : 8;
  249. u32 byte0_len : 4;
  250. u32 reserved1 : 3;
  251. u32 byte0_err : 1;
  252. u32 reserved2 : 8;
  253. u8 type : 8;
  254. u8 ch_id : 8;
  255. };
  256. struct msm_gpi_cb {
  257. enum msm_gpi_cb_event cb_event;
  258. u64 status;
  259. u64 timestamp;
  260. u64 count;
  261. struct msm_gpi_error_log error_log;
  262. struct __packed qup_q2spi_cr_header_event q2spi_cr_header_event;
  263. };
  264. struct dma_chan;
  265. struct gpi_client_info {
  266. /*
  267. * memory for msm_gpi_cb is released after callback, clients shall
  268. * save any required data for post processing after returning
  269. * from callback
  270. */
  271. void (*callback)(struct dma_chan *chan,
  272. struct msm_gpi_cb const *msm_gpi_cb,
  273. void *cb_param);
  274. void *cb_param;
  275. };
  276. /*
  277. * control structure to config gpi dma engine via dmaengine_slave_config()
  278. * dma_chan.private should point to msm_gpi_ctrl structure
  279. */
  280. struct msm_gpi_ctrl {
  281. enum msm_gpi_ctrl_cmd cmd;
  282. union {
  283. struct gpi_client_info init;
  284. };
  285. };
  286. enum msm_gpi_tce_code {
  287. MSM_GPI_TCE_SUCCESS = 1,
  288. MSM_GPI_TCE_EOT = 2,
  289. MSM_GPI_TCE_EOB = 4,
  290. MSM_GPI_TCE_UNEXP_ERR = 16,
  291. };
  292. /*
  293. * gpi specific callback parameters to pass between gpi client and gpi engine.
  294. * client shall set async_desc.callback_parm to msm_gpi_dma_async_tx_cb_param
  295. */
  296. struct msm_gpi_dma_async_tx_cb_param {
  297. u32 length;
  298. enum msm_gpi_tce_code completion_code; /* TCE event code */
  299. u32 status;
  300. struct __packed msm_gpi_tre imed_tre;
  301. void *userdata;
  302. enum GPI_EV_TYPE tce_type;
  303. u32 q2spi_status:8;
  304. };
  305. struct gsi_tre_info {
  306. struct msm_gpi_tre lock_t;
  307. struct msm_gpi_tre go_t;
  308. struct msm_gpi_tre config_t;
  309. struct msm_gpi_tre dma_t;
  310. struct msm_gpi_tre unlock_t;
  311. u8 flags;
  312. };
  313. struct gsi_tre_queue {
  314. u32 msg_cnt;
  315. u32 unmap_msg_cnt;
  316. u32 freed_msg_cnt;
  317. dma_addr_t dma_buf[GSI_MAX_NUM_TRE_MSGS];
  318. void *virt_buf[GSI_MAX_NUM_TRE_MSGS];
  319. u32 len[GSI_MAX_NUM_TRE_MSGS];
  320. atomic_t irq_cnt;
  321. };
  322. struct gsi_xfer_param {
  323. struct dma_async_tx_descriptor *desc;
  324. struct msm_gpi_dma_async_tx_cb_param cb;
  325. struct dma_chan *ch;
  326. struct scatterlist *sg; /* lock, cfg0, go, TX, unlock */
  327. dma_addr_t sg_dma;
  328. struct msm_gpi_ctrl ev;
  329. struct gsi_tre_info tre;
  330. struct gsi_tre_queue tre_queue;
  331. spinlock_t multi_tre_lock; /* multi tre spin lock */
  332. void (*cb_fun)(void *ptr); /* tx or rx cb */
  333. };
  334. struct gsi_common {
  335. u8 protocol;
  336. struct completion *xfer;
  337. struct device *dev;
  338. void *dev_node;
  339. struct gsi_xfer_param tx;
  340. struct gsi_xfer_param rx;
  341. void *ipc;
  342. bool req_chan;
  343. bool err; /* For every gsi error performing gsi reset */
  344. int *protocol_err; /* protocol specific error*/
  345. void (*ev_cb_fun)(struct dma_chan *ch, struct msm_gpi_cb const *cb_str, void *ptr);
  346. };
  347. /* Client drivers of the GPI can call this function to dump the GPI registers
  348. * whenever client met some scenario like timeout, error in GPI transfer mode.
  349. */
  350. void gpi_dump_for_geni(struct dma_chan *chan);
  351. /**
  352. * gsi_common_tre_process() - Process received TRE's from GSI HW
  353. * @gsi: Base address of the gsi common structure.
  354. * @num_xfers: number of messages count.
  355. * @num_msg_per_irq: num of messages per irq.
  356. * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
  357. *
  358. * This function is used to process received TRE's from GSI HW.
  359. * And also used for error case, it will clear and unmap all pending transfers.
  360. *
  361. * Return: None.
  362. */
  363. void gsi_common_tre_process(struct gsi_common *gsi, u32 num_xfers, u32 num_msg_per_irq,
  364. struct device *wrapper_dev);
  365. /**
  366. * gsi_common_tx_tre_optimization() - Process received TRE's from GSI HW
  367. * @gsi: Base address of the gsi common structure.
  368. * @num_xfers: number of messages count.
  369. * @num_msg_per_irq: num of messages per irq.
  370. * @xfer_timeout: xfer timeout value.
  371. * @wrapper_dev: Pointer to the corresponding QUPv3 wrapper core.
  372. *
  373. * This function is used to optimize dma tre's, it keeps always HW busy.
  374. *
  375. * Return: Returning timeout value
  376. */
  377. int gsi_common_tx_tre_optimization(struct gsi_common *gsi, u32 num_xfers, u32 num_msg_per_irq,
  378. u32 xfer_timeout, struct device *wrapper_dev);
  379. /**
  380. * geni_gsi_ch_start() - gsi channel command to start the GSI RX and TX channels
  381. * @chan: dma channel handle
  382. *
  383. * Return: Returns success or failure
  384. */
  385. int geni_gsi_ch_start(struct dma_chan *chan);
  386. /**
  387. * geni_gsi_disconnect_doorbell_stop_ch() - function to disconnect gsi doorbell and stop channel
  388. * @chan: dma channel handle
  389. *
  390. * Return: Returns success or failure
  391. */
  392. int geni_gsi_disconnect_doorbell_stop_ch(struct dma_chan *chan, bool stop_ch);
  393. /**
  394. * geni_gsi_common_request_channel() - gsi common dma request channel
  395. * @gsi: Base address of gsi common
  396. * @stop_ch: stop channel if set to true
  397. *
  398. * Return: Returns success or failure
  399. */
  400. int geni_gsi_common_request_channel(struct gsi_common *gsi);
  401. /**
  402. * gsi_common_prep_desc_and_submit() - gsi common prepare descriptor and gsi submit
  403. * @gsi: Base address of gsi common
  404. * @segs: Num of segments
  405. * @tx_chan: dma transfer channel type
  406. * @skip_callbacks: flag used to register callbacks
  407. *
  408. * Return: Returns success or failure
  409. */
  410. int gsi_common_prep_desc_and_submit(struct gsi_common *gsi, int segs, bool tx_chan, bool skip_cb);
  411. /**
  412. * gsi_common_fill_tre_buf() - gsi common fill tre buffers
  413. * @gsi: Base address of gsi common
  414. * @tx_chan: dma transfer channel type
  415. *
  416. * Return: Returns tre count
  417. */
  418. int gsi_common_fill_tre_buf(struct gsi_common *gsi, bool tx_chan);
  419. /**
  420. * gsi_common_clear_tre_indexes() - gsi common queue clear tre indexes
  421. * @gsi_q: Base address of gsi common queue
  422. *
  423. * Return: None
  424. */
  425. void gsi_common_clear_tre_indexes(struct gsi_tre_queue *gsi_q);
  426. #endif