atmel-smc.h 4.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Atmel SMC (Static Memory Controller) register offsets and bit definitions.
  4. *
  5. * Copyright (C) 2014 Atmel
  6. * Copyright (C) 2014 Free Electrons
  7. *
  8. * Author: Boris Brezillon <[email protected]>
  9. */
  10. #ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
  11. #define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
  12. #include <linux/kernel.h>
  13. #include <linux/of.h>
  14. #include <linux/regmap.h>
  15. #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
  16. #define ATMEL_HSMC_SETUP(layout, cs) \
  17. ((layout)->timing_regs_offset + ((cs) * 0x14))
  18. #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
  19. #define ATMEL_HSMC_PULSE(layout, cs) \
  20. ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
  21. #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
  22. #define ATMEL_HSMC_CYCLE(layout, cs) \
  23. ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
  24. #define ATMEL_SMC_NWE_SHIFT 0
  25. #define ATMEL_SMC_NCS_WR_SHIFT 8
  26. #define ATMEL_SMC_NRD_SHIFT 16
  27. #define ATMEL_SMC_NCS_RD_SHIFT 24
  28. #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
  29. #define ATMEL_HSMC_MODE(layout, cs) \
  30. ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
  31. #define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
  32. #define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
  33. #define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
  34. #define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
  35. #define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
  36. #define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
  37. #define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
  38. #define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
  39. #define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
  40. #define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
  41. #define ATMEL_SMC_MODE_BAT_MASK BIT(8)
  42. #define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
  43. #define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
  44. #define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
  45. #define ATMEL_SMC_MODE_DBW_8 (0 << 12)
  46. #define ATMEL_SMC_MODE_DBW_16 (1 << 12)
  47. #define ATMEL_SMC_MODE_DBW_32 (2 << 12)
  48. #define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
  49. #define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
  50. #define ATMEL_SMC_MODE_TDF_MAX 16
  51. #define ATMEL_SMC_MODE_TDF_MIN 1
  52. #define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
  53. #define ATMEL_SMC_MODE_PMEN BIT(24)
  54. #define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
  55. #define ATMEL_SMC_MODE_PS_4 (0 << 28)
  56. #define ATMEL_SMC_MODE_PS_8 (1 << 28)
  57. #define ATMEL_SMC_MODE_PS_16 (2 << 28)
  58. #define ATMEL_SMC_MODE_PS_32 (3 << 28)
  59. #define ATMEL_HSMC_TIMINGS(layout, cs) \
  60. ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
  61. #define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
  62. #define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
  63. #define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
  64. #define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
  65. #define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
  66. #define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
  67. #define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
  68. #define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
  69. struct atmel_hsmc_reg_layout {
  70. unsigned int timing_regs_offset;
  71. };
  72. /**
  73. * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
  74. * @setup: NCS/NWE/NRD setup timings (not applicable to at91rm9200)
  75. * @pulse: NCS/NWE/NRD pulse timings (not applicable to at91rm9200)
  76. * @cycle: NWE/NRD cycle timings (not applicable to at91rm9200)
  77. * @timings: advanced NAND related timings (only applicable to HSMC)
  78. * @mode: all kind of config parameters (see the fields definition above).
  79. * The mode fields are different on at91rm9200
  80. */
  81. struct atmel_smc_cs_conf {
  82. u32 setup;
  83. u32 pulse;
  84. u32 cycle;
  85. u32 timings;
  86. u32 mode;
  87. };
  88. void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
  89. int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
  90. unsigned int shift,
  91. unsigned int ncycles);
  92. int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
  93. unsigned int shift, unsigned int ncycles);
  94. int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
  95. unsigned int shift, unsigned int ncycles);
  96. int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
  97. unsigned int shift, unsigned int ncycles);
  98. void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
  99. const struct atmel_smc_cs_conf *conf);
  100. void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
  101. const struct atmel_hsmc_reg_layout *reglayout,
  102. int cs, const struct atmel_smc_cs_conf *conf);
  103. void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
  104. struct atmel_smc_cs_conf *conf);
  105. void atmel_hsmc_cs_conf_get(struct regmap *regmap,
  106. const struct atmel_hsmc_reg_layout *reglayout,
  107. int cs, struct atmel_smc_cs_conf *conf);
  108. const struct atmel_hsmc_reg_layout *
  109. atmel_hsmc_get_reg_layout(struct device_node *np);
  110. #endif /* _LINUX_MFD_SYSCON_ATMEL_SMC_H_ */