fsl_ifc.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /* Freescale Integrated Flash Controller
  3. *
  4. * Copyright 2011 Freescale Semiconductor, Inc
  5. *
  6. * Author: Dipen Dudhat <[email protected]>
  7. */
  8. #ifndef __ASM_FSL_IFC_H
  9. #define __ASM_FSL_IFC_H
  10. #include <linux/compiler.h>
  11. #include <linux/types.h>
  12. #include <linux/io.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/interrupt.h>
  15. /*
  16. * The actual number of banks implemented depends on the IFC version
  17. * - IFC version 1.0 implements 4 banks.
  18. * - IFC version 1.1 onward implements 8 banks.
  19. */
  20. #define FSL_IFC_BANK_COUNT 8
  21. #define FSL_IFC_VERSION_MASK 0x0F0F0000
  22. #define FSL_IFC_VERSION_1_0_0 0x01000000
  23. #define FSL_IFC_VERSION_1_1_0 0x01010000
  24. #define FSL_IFC_VERSION_2_0_0 0x02000000
  25. #define PGOFFSET_64K (64*1024)
  26. #define PGOFFSET_4K (4*1024)
  27. /*
  28. * CSPR - Chip Select Property Register
  29. */
  30. #define CSPR_BA 0xFFFF0000
  31. #define CSPR_BA_SHIFT 16
  32. #define CSPR_PORT_SIZE 0x00000180
  33. #define CSPR_PORT_SIZE_SHIFT 7
  34. /* Port Size 8 bit */
  35. #define CSPR_PORT_SIZE_8 0x00000080
  36. /* Port Size 16 bit */
  37. #define CSPR_PORT_SIZE_16 0x00000100
  38. /* Port Size 32 bit */
  39. #define CSPR_PORT_SIZE_32 0x00000180
  40. /* Write Protect */
  41. #define CSPR_WP 0x00000040
  42. #define CSPR_WP_SHIFT 6
  43. /* Machine Select */
  44. #define CSPR_MSEL 0x00000006
  45. #define CSPR_MSEL_SHIFT 1
  46. /* NOR */
  47. #define CSPR_MSEL_NOR 0x00000000
  48. /* NAND */
  49. #define CSPR_MSEL_NAND 0x00000002
  50. /* GPCM */
  51. #define CSPR_MSEL_GPCM 0x00000004
  52. /* Bank Valid */
  53. #define CSPR_V 0x00000001
  54. #define CSPR_V_SHIFT 0
  55. /*
  56. * Address Mask Register
  57. */
  58. #define IFC_AMASK_MASK 0xFFFF0000
  59. #define IFC_AMASK_SHIFT 16
  60. #define IFC_AMASK(n) (IFC_AMASK_MASK << \
  61. (__ilog2(n) - IFC_AMASK_SHIFT))
  62. /*
  63. * Chip Select Option Register IFC_NAND Machine
  64. */
  65. /* Enable ECC Encoder */
  66. #define CSOR_NAND_ECC_ENC_EN 0x80000000
  67. #define CSOR_NAND_ECC_MODE_MASK 0x30000000
  68. /* 4 bit correction per 520 Byte sector */
  69. #define CSOR_NAND_ECC_MODE_4 0x00000000
  70. /* 8 bit correction per 528 Byte sector */
  71. #define CSOR_NAND_ECC_MODE_8 0x10000000
  72. /* Enable ECC Decoder */
  73. #define CSOR_NAND_ECC_DEC_EN 0x04000000
  74. /* Row Address Length */
  75. #define CSOR_NAND_RAL_MASK 0x01800000
  76. #define CSOR_NAND_RAL_SHIFT 20
  77. #define CSOR_NAND_RAL_1 0x00000000
  78. #define CSOR_NAND_RAL_2 0x00800000
  79. #define CSOR_NAND_RAL_3 0x01000000
  80. #define CSOR_NAND_RAL_4 0x01800000
  81. /* Page Size 512b, 2k, 4k */
  82. #define CSOR_NAND_PGS_MASK 0x00180000
  83. #define CSOR_NAND_PGS_SHIFT 16
  84. #define CSOR_NAND_PGS_512 0x00000000
  85. #define CSOR_NAND_PGS_2K 0x00080000
  86. #define CSOR_NAND_PGS_4K 0x00100000
  87. #define CSOR_NAND_PGS_8K 0x00180000
  88. /* Spare region Size */
  89. #define CSOR_NAND_SPRZ_MASK 0x0000E000
  90. #define CSOR_NAND_SPRZ_SHIFT 13
  91. #define CSOR_NAND_SPRZ_16 0x00000000
  92. #define CSOR_NAND_SPRZ_64 0x00002000
  93. #define CSOR_NAND_SPRZ_128 0x00004000
  94. #define CSOR_NAND_SPRZ_210 0x00006000
  95. #define CSOR_NAND_SPRZ_218 0x00008000
  96. #define CSOR_NAND_SPRZ_224 0x0000A000
  97. #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
  98. /* Pages Per Block */
  99. #define CSOR_NAND_PB_MASK 0x00000700
  100. #define CSOR_NAND_PB_SHIFT 8
  101. #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
  102. /* Time for Read Enable High to Output High Impedance */
  103. #define CSOR_NAND_TRHZ_MASK 0x0000001C
  104. #define CSOR_NAND_TRHZ_SHIFT 2
  105. #define CSOR_NAND_TRHZ_20 0x00000000
  106. #define CSOR_NAND_TRHZ_40 0x00000004
  107. #define CSOR_NAND_TRHZ_60 0x00000008
  108. #define CSOR_NAND_TRHZ_80 0x0000000C
  109. #define CSOR_NAND_TRHZ_100 0x00000010
  110. /* Buffer control disable */
  111. #define CSOR_NAND_BCTLD 0x00000001
  112. /*
  113. * Chip Select Option Register - NOR Flash Mode
  114. */
  115. /* Enable Address shift Mode */
  116. #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
  117. /* Page Read Enable from NOR device */
  118. #define CSOR_NOR_PGRD_EN 0x10000000
  119. /* AVD Toggle Enable during Burst Program */
  120. #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
  121. /* Address Data Multiplexing Shift */
  122. #define CSOR_NOR_ADM_MASK 0x0003E000
  123. #define CSOR_NOR_ADM_SHIFT_SHIFT 13
  124. #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
  125. /* Type of the NOR device hooked */
  126. #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
  127. #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
  128. /* Time for Read Enable High to Output High Impedance */
  129. #define CSOR_NOR_TRHZ_MASK 0x0000001C
  130. #define CSOR_NOR_TRHZ_SHIFT 2
  131. #define CSOR_NOR_TRHZ_20 0x00000000
  132. #define CSOR_NOR_TRHZ_40 0x00000004
  133. #define CSOR_NOR_TRHZ_60 0x00000008
  134. #define CSOR_NOR_TRHZ_80 0x0000000C
  135. #define CSOR_NOR_TRHZ_100 0x00000010
  136. /* Buffer control disable */
  137. #define CSOR_NOR_BCTLD 0x00000001
  138. /*
  139. * Chip Select Option Register - GPCM Mode
  140. */
  141. /* GPCM Mode - Normal */
  142. #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
  143. /* GPCM Mode - GenericASIC */
  144. #define CSOR_GPCM_GPMODE_ASIC 0x80000000
  145. /* Parity Mode odd/even */
  146. #define CSOR_GPCM_PARITY_EVEN 0x40000000
  147. /* Parity Checking enable/disable */
  148. #define CSOR_GPCM_PAR_EN 0x20000000
  149. /* GPCM Timeout Count */
  150. #define CSOR_GPCM_GPTO_MASK 0x0F000000
  151. #define CSOR_GPCM_GPTO_SHIFT 24
  152. #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
  153. /* GPCM External Access Termination mode for read access */
  154. #define CSOR_GPCM_RGETA_EXT 0x00080000
  155. /* GPCM External Access Termination mode for write access */
  156. #define CSOR_GPCM_WGETA_EXT 0x00040000
  157. /* Address Data Multiplexing Shift */
  158. #define CSOR_GPCM_ADM_MASK 0x0003E000
  159. #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
  160. #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
  161. /* Generic ASIC Parity error indication delay */
  162. #define CSOR_GPCM_GAPERRD_MASK 0x00000180
  163. #define CSOR_GPCM_GAPERRD_SHIFT 7
  164. #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
  165. /* Time for Read Enable High to Output High Impedance */
  166. #define CSOR_GPCM_TRHZ_MASK 0x0000001C
  167. #define CSOR_GPCM_TRHZ_20 0x00000000
  168. #define CSOR_GPCM_TRHZ_40 0x00000004
  169. #define CSOR_GPCM_TRHZ_60 0x00000008
  170. #define CSOR_GPCM_TRHZ_80 0x0000000C
  171. #define CSOR_GPCM_TRHZ_100 0x00000010
  172. /* Buffer control disable */
  173. #define CSOR_GPCM_BCTLD 0x00000001
  174. /*
  175. * Ready Busy Status Register (RB_STAT)
  176. */
  177. /* CSn is READY */
  178. #define IFC_RB_STAT_READY_CS0 0x80000000
  179. #define IFC_RB_STAT_READY_CS1 0x40000000
  180. #define IFC_RB_STAT_READY_CS2 0x20000000
  181. #define IFC_RB_STAT_READY_CS3 0x10000000
  182. /*
  183. * General Control Register (GCR)
  184. */
  185. #define IFC_GCR_MASK 0x8000F800
  186. /* reset all IFC hardware */
  187. #define IFC_GCR_SOFT_RST_ALL 0x80000000
  188. /* Turnaroud Time of external buffer */
  189. #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
  190. #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
  191. /*
  192. * Common Event and Error Status Register (CM_EVTER_STAT)
  193. */
  194. /* Chip select error */
  195. #define IFC_CM_EVTER_STAT_CSER 0x80000000
  196. /*
  197. * Common Event and Error Enable Register (CM_EVTER_EN)
  198. */
  199. /* Chip select error checking enable */
  200. #define IFC_CM_EVTER_EN_CSEREN 0x80000000
  201. /*
  202. * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
  203. */
  204. /* Chip select error interrupt enable */
  205. #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
  206. /*
  207. * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
  208. */
  209. /* transaction type of error Read/Write */
  210. #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
  211. #define IFC_CM_ERATTR0_ERAID 0x0FF00000
  212. #define IFC_CM_ERATTR0_ERAID_SHIFT 20
  213. #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
  214. #define IFC_CM_ERATTR0_ESRCID_SHIFT 8
  215. /*
  216. * Clock Control Register (CCR)
  217. */
  218. #define IFC_CCR_MASK 0x0F0F8800
  219. /* Clock division ratio */
  220. #define IFC_CCR_CLK_DIV_MASK 0x0F000000
  221. #define IFC_CCR_CLK_DIV_SHIFT 24
  222. #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
  223. /* IFC Clock Delay */
  224. #define IFC_CCR_CLK_DLY_MASK 0x000F0000
  225. #define IFC_CCR_CLK_DLY_SHIFT 16
  226. #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
  227. /* Invert IFC clock before sending out */
  228. #define IFC_CCR_INV_CLK_EN 0x00008000
  229. /* Fedback IFC Clock */
  230. #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
  231. /*
  232. * Clock Status Register (CSR)
  233. */
  234. /* Clk is stable */
  235. #define IFC_CSR_CLK_STAT_STABLE 0x80000000
  236. /*
  237. * IFC_NAND Machine Specific Registers
  238. */
  239. /*
  240. * NAND Configuration Register (NCFGR)
  241. */
  242. /* Auto Boot Mode */
  243. #define IFC_NAND_NCFGR_BOOT 0x80000000
  244. /* SRAM Initialization */
  245. #define IFC_NAND_NCFGR_SRAM_INIT_EN 0x20000000
  246. /* Addressing Mode-ROW0+n/COL0 */
  247. #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
  248. /* Addressing Mode-ROW0+n/COL0+n */
  249. #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
  250. /* Number of loop iterations of FIR sequences for multi page operations */
  251. #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
  252. #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
  253. #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
  254. /* Number of wait cycles */
  255. #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
  256. #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
  257. /*
  258. * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
  259. */
  260. /* General purpose FCM flash command bytes CMD0-CMD7 */
  261. #define IFC_NAND_FCR0_CMD0 0xFF000000
  262. #define IFC_NAND_FCR0_CMD0_SHIFT 24
  263. #define IFC_NAND_FCR0_CMD1 0x00FF0000
  264. #define IFC_NAND_FCR0_CMD1_SHIFT 16
  265. #define IFC_NAND_FCR0_CMD2 0x0000FF00
  266. #define IFC_NAND_FCR0_CMD2_SHIFT 8
  267. #define IFC_NAND_FCR0_CMD3 0x000000FF
  268. #define IFC_NAND_FCR0_CMD3_SHIFT 0
  269. #define IFC_NAND_FCR1_CMD4 0xFF000000
  270. #define IFC_NAND_FCR1_CMD4_SHIFT 24
  271. #define IFC_NAND_FCR1_CMD5 0x00FF0000
  272. #define IFC_NAND_FCR1_CMD5_SHIFT 16
  273. #define IFC_NAND_FCR1_CMD6 0x0000FF00
  274. #define IFC_NAND_FCR1_CMD6_SHIFT 8
  275. #define IFC_NAND_FCR1_CMD7 0x000000FF
  276. #define IFC_NAND_FCR1_CMD7_SHIFT 0
  277. /*
  278. * Flash ROW and COL Address Register (ROWn, COLn)
  279. */
  280. /* Main/spare region locator */
  281. #define IFC_NAND_COL_MS 0x80000000
  282. /* Column Address */
  283. #define IFC_NAND_COL_CA_MASK 0x00000FFF
  284. /*
  285. * NAND Flash Byte Count Register (NAND_BC)
  286. */
  287. /* Byte Count for read/Write */
  288. #define IFC_NAND_BC 0x000001FF
  289. /*
  290. * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
  291. */
  292. /* NAND Machine specific opcodes OP0-OP14*/
  293. #define IFC_NAND_FIR0_OP0 0xFC000000
  294. #define IFC_NAND_FIR0_OP0_SHIFT 26
  295. #define IFC_NAND_FIR0_OP1 0x03F00000
  296. #define IFC_NAND_FIR0_OP1_SHIFT 20
  297. #define IFC_NAND_FIR0_OP2 0x000FC000
  298. #define IFC_NAND_FIR0_OP2_SHIFT 14
  299. #define IFC_NAND_FIR0_OP3 0x00003F00
  300. #define IFC_NAND_FIR0_OP3_SHIFT 8
  301. #define IFC_NAND_FIR0_OP4 0x000000FC
  302. #define IFC_NAND_FIR0_OP4_SHIFT 2
  303. #define IFC_NAND_FIR1_OP5 0xFC000000
  304. #define IFC_NAND_FIR1_OP5_SHIFT 26
  305. #define IFC_NAND_FIR1_OP6 0x03F00000
  306. #define IFC_NAND_FIR1_OP6_SHIFT 20
  307. #define IFC_NAND_FIR1_OP7 0x000FC000
  308. #define IFC_NAND_FIR1_OP7_SHIFT 14
  309. #define IFC_NAND_FIR1_OP8 0x00003F00
  310. #define IFC_NAND_FIR1_OP8_SHIFT 8
  311. #define IFC_NAND_FIR1_OP9 0x000000FC
  312. #define IFC_NAND_FIR1_OP9_SHIFT 2
  313. #define IFC_NAND_FIR2_OP10 0xFC000000
  314. #define IFC_NAND_FIR2_OP10_SHIFT 26
  315. #define IFC_NAND_FIR2_OP11 0x03F00000
  316. #define IFC_NAND_FIR2_OP11_SHIFT 20
  317. #define IFC_NAND_FIR2_OP12 0x000FC000
  318. #define IFC_NAND_FIR2_OP12_SHIFT 14
  319. #define IFC_NAND_FIR2_OP13 0x00003F00
  320. #define IFC_NAND_FIR2_OP13_SHIFT 8
  321. #define IFC_NAND_FIR2_OP14 0x000000FC
  322. #define IFC_NAND_FIR2_OP14_SHIFT 2
  323. /*
  324. * Instruction opcodes to be programmed
  325. * in FIR registers- 6bits
  326. */
  327. enum ifc_nand_fir_opcodes {
  328. IFC_FIR_OP_NOP,
  329. IFC_FIR_OP_CA0,
  330. IFC_FIR_OP_CA1,
  331. IFC_FIR_OP_CA2,
  332. IFC_FIR_OP_CA3,
  333. IFC_FIR_OP_RA0,
  334. IFC_FIR_OP_RA1,
  335. IFC_FIR_OP_RA2,
  336. IFC_FIR_OP_RA3,
  337. IFC_FIR_OP_CMD0,
  338. IFC_FIR_OP_CMD1,
  339. IFC_FIR_OP_CMD2,
  340. IFC_FIR_OP_CMD3,
  341. IFC_FIR_OP_CMD4,
  342. IFC_FIR_OP_CMD5,
  343. IFC_FIR_OP_CMD6,
  344. IFC_FIR_OP_CMD7,
  345. IFC_FIR_OP_CW0,
  346. IFC_FIR_OP_CW1,
  347. IFC_FIR_OP_CW2,
  348. IFC_FIR_OP_CW3,
  349. IFC_FIR_OP_CW4,
  350. IFC_FIR_OP_CW5,
  351. IFC_FIR_OP_CW6,
  352. IFC_FIR_OP_CW7,
  353. IFC_FIR_OP_WBCD,
  354. IFC_FIR_OP_RBCD,
  355. IFC_FIR_OP_BTRD,
  356. IFC_FIR_OP_RDSTAT,
  357. IFC_FIR_OP_NWAIT,
  358. IFC_FIR_OP_WFR,
  359. IFC_FIR_OP_SBRD,
  360. IFC_FIR_OP_UA,
  361. IFC_FIR_OP_RB,
  362. };
  363. /*
  364. * NAND Chip Select Register (NAND_CSEL)
  365. */
  366. #define IFC_NAND_CSEL 0x0C000000
  367. #define IFC_NAND_CSEL_SHIFT 26
  368. #define IFC_NAND_CSEL_CS0 0x00000000
  369. #define IFC_NAND_CSEL_CS1 0x04000000
  370. #define IFC_NAND_CSEL_CS2 0x08000000
  371. #define IFC_NAND_CSEL_CS3 0x0C000000
  372. /*
  373. * NAND Operation Sequence Start (NANDSEQ_STRT)
  374. */
  375. /* NAND Flash Operation Start */
  376. #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
  377. /* Automatic Erase */
  378. #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
  379. /* Automatic Program */
  380. #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
  381. /* Automatic Copyback */
  382. #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
  383. /* Automatic Read Operation */
  384. #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
  385. /* Automatic Status Read */
  386. #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
  387. /*
  388. * NAND Event and Error Status Register (NAND_EVTER_STAT)
  389. */
  390. /* Operation Complete */
  391. #define IFC_NAND_EVTER_STAT_OPC 0x80000000
  392. /* Flash Timeout Error */
  393. #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
  394. /* Write Protect Error */
  395. #define IFC_NAND_EVTER_STAT_WPER 0x04000000
  396. /* ECC Error */
  397. #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
  398. /* RCW Load Done */
  399. #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
  400. /* Boot Loadr Done */
  401. #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
  402. /* Bad Block Indicator search select */
  403. #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
  404. /*
  405. * NAND Flash Page Read Completion Event Status Register
  406. * (PGRDCMPL_EVT_STAT)
  407. */
  408. #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
  409. /* Small Page 0-15 Done */
  410. #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
  411. /* Large Page(2K) 0-3 Done */
  412. #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
  413. /* Large Page(4K) 0-1 Done */
  414. #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
  415. /*
  416. * NAND Event and Error Enable Register (NAND_EVTER_EN)
  417. */
  418. /* Operation complete event enable */
  419. #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
  420. /* Page read complete event enable */
  421. #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
  422. /* Flash Timeout error enable */
  423. #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
  424. /* Write Protect error enable */
  425. #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
  426. /* ECC error logging enable */
  427. #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
  428. /*
  429. * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
  430. */
  431. /* Enable interrupt for operation complete */
  432. #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
  433. /* Enable interrupt for Page read complete */
  434. #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
  435. /* Enable interrupt for Flash timeout error */
  436. #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
  437. /* Enable interrupt for Write protect error */
  438. #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
  439. /* Enable interrupt for ECC error*/
  440. #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
  441. /*
  442. * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
  443. */
  444. #define IFC_NAND_ERATTR0_MASK 0x0C080000
  445. /* Error on CS0-3 for NAND */
  446. #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
  447. #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
  448. #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
  449. #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
  450. /* Transaction type of error Read/Write */
  451. #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
  452. /*
  453. * NAND Flash Status Register (NAND_FSR)
  454. */
  455. /* First byte of data read from read status op */
  456. #define IFC_NAND_NFSR_RS0 0xFF000000
  457. /* Second byte of data read from read status op */
  458. #define IFC_NAND_NFSR_RS1 0x00FF0000
  459. /*
  460. * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
  461. */
  462. /* Number of ECC errors on sector n (n = 0-15) */
  463. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
  464. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
  465. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
  466. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
  467. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
  468. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
  469. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
  470. #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
  471. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
  472. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
  473. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
  474. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
  475. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
  476. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
  477. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
  478. #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
  479. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
  480. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
  481. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
  482. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
  483. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
  484. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
  485. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
  486. #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
  487. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
  488. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
  489. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
  490. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
  491. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
  492. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
  493. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
  494. #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
  495. /*
  496. * NAND Control Register (NANDCR)
  497. */
  498. #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
  499. #define IFC_NAND_NCR_FTOCNT_SHIFT 25
  500. #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
  501. /*
  502. * NAND_AUTOBOOT_TRGR
  503. */
  504. /* Trigger RCW load */
  505. #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
  506. /* Trigget Auto Boot */
  507. #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
  508. /*
  509. * NAND_MDR
  510. */
  511. /* 1st read data byte when opcode SBRD */
  512. #define IFC_NAND_MDR_RDATA0 0xFF000000
  513. /* 2nd read data byte when opcode SBRD */
  514. #define IFC_NAND_MDR_RDATA1 0x00FF0000
  515. /*
  516. * NOR Machine Specific Registers
  517. */
  518. /*
  519. * NOR Event and Error Status Register (NOR_EVTER_STAT)
  520. */
  521. /* NOR Command Sequence Operation Complete */
  522. #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
  523. /* Write Protect Error */
  524. #define IFC_NOR_EVTER_STAT_WPER 0x04000000
  525. /* Command Sequence Timeout Error */
  526. #define IFC_NOR_EVTER_STAT_STOER 0x01000000
  527. /*
  528. * NOR Event and Error Enable Register (NOR_EVTER_EN)
  529. */
  530. /* NOR Command Seq complete event enable */
  531. #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
  532. /* Write Protect Error Checking Enable */
  533. #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
  534. /* Timeout Error Enable */
  535. #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
  536. /*
  537. * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
  538. */
  539. /* Enable interrupt for OPC complete */
  540. #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
  541. /* Enable interrupt for write protect error */
  542. #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
  543. /* Enable interrupt for timeout error */
  544. #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
  545. /*
  546. * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
  547. */
  548. /* Source ID for error transaction */
  549. #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
  550. /* AXI ID for error transation */
  551. #define IFC_NOR_ERATTR0_ERAID 0x000FF000
  552. /* Chip select corresponds to NOR error */
  553. #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
  554. #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
  555. #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
  556. #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
  557. /* Type of transaction read/write */
  558. #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
  559. /*
  560. * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
  561. */
  562. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
  563. #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
  564. /*
  565. * NOR Control Register (NORCR)
  566. */
  567. #define IFC_NORCR_MASK 0x0F0F0000
  568. /* No. of Address/Data Phase */
  569. #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
  570. #define IFC_NORCR_NUM_PHASE_SHIFT 24
  571. #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
  572. /* Sequence Timeout Count */
  573. #define IFC_NORCR_STOCNT_MASK 0x000F0000
  574. #define IFC_NORCR_STOCNT_SHIFT 16
  575. #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
  576. /*
  577. * GPCM Machine specific registers
  578. */
  579. /*
  580. * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
  581. */
  582. /* Timeout error */
  583. #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
  584. /* Parity error */
  585. #define IFC_GPCM_EVTER_STAT_PER 0x01000000
  586. /*
  587. * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
  588. */
  589. /* Timeout error enable */
  590. #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
  591. /* Parity error enable */
  592. #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
  593. /*
  594. * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
  595. */
  596. /* Enable Interrupt for timeout error */
  597. #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
  598. /* Enable Interrupt for Parity error */
  599. #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
  600. /*
  601. * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
  602. */
  603. /* Source ID for error transaction */
  604. #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
  605. /* AXI ID for error transaction */
  606. #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
  607. /* Chip select corresponds to GPCM error */
  608. #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
  609. #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
  610. #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
  611. #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
  612. /* Type of transaction read/Write */
  613. #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
  614. /*
  615. * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
  616. */
  617. /* On which beat of address/data parity error is observed */
  618. #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
  619. /* Parity Error on byte */
  620. #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
  621. /* Parity Error reported in addr or data phase */
  622. #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
  623. /*
  624. * GPCM Status Register (GPCM_STAT)
  625. */
  626. #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
  627. /*
  628. * IFC Controller NAND Machine registers
  629. */
  630. struct fsl_ifc_nand {
  631. __be32 ncfgr;
  632. u32 res1[0x4];
  633. __be32 nand_fcr0;
  634. __be32 nand_fcr1;
  635. u32 res2[0x8];
  636. __be32 row0;
  637. u32 res3;
  638. __be32 col0;
  639. u32 res4;
  640. __be32 row1;
  641. u32 res5;
  642. __be32 col1;
  643. u32 res6;
  644. __be32 row2;
  645. u32 res7;
  646. __be32 col2;
  647. u32 res8;
  648. __be32 row3;
  649. u32 res9;
  650. __be32 col3;
  651. u32 res10[0x24];
  652. __be32 nand_fbcr;
  653. u32 res11;
  654. __be32 nand_fir0;
  655. __be32 nand_fir1;
  656. __be32 nand_fir2;
  657. u32 res12[0x10];
  658. __be32 nand_csel;
  659. u32 res13;
  660. __be32 nandseq_strt;
  661. u32 res14;
  662. __be32 nand_evter_stat;
  663. u32 res15;
  664. __be32 pgrdcmpl_evt_stat;
  665. u32 res16[0x2];
  666. __be32 nand_evter_en;
  667. u32 res17[0x2];
  668. __be32 nand_evter_intr_en;
  669. __be32 nand_vol_addr_stat;
  670. u32 res18;
  671. __be32 nand_erattr0;
  672. __be32 nand_erattr1;
  673. u32 res19[0x10];
  674. __be32 nand_fsr;
  675. u32 res20;
  676. __be32 nand_eccstat[8];
  677. u32 res21[0x1c];
  678. __be32 nanndcr;
  679. u32 res22[0x2];
  680. __be32 nand_autoboot_trgr;
  681. u32 res23;
  682. __be32 nand_mdr;
  683. u32 res24[0x1C];
  684. __be32 nand_dll_lowcfg0;
  685. __be32 nand_dll_lowcfg1;
  686. u32 res25;
  687. __be32 nand_dll_lowstat;
  688. u32 res26[0x3c];
  689. };
  690. /*
  691. * IFC controller NOR Machine registers
  692. */
  693. struct fsl_ifc_nor {
  694. __be32 nor_evter_stat;
  695. u32 res1[0x2];
  696. __be32 nor_evter_en;
  697. u32 res2[0x2];
  698. __be32 nor_evter_intr_en;
  699. u32 res3[0x2];
  700. __be32 nor_erattr0;
  701. __be32 nor_erattr1;
  702. __be32 nor_erattr2;
  703. u32 res4[0x4];
  704. __be32 norcr;
  705. u32 res5[0xEF];
  706. };
  707. /*
  708. * IFC controller GPCM Machine registers
  709. */
  710. struct fsl_ifc_gpcm {
  711. __be32 gpcm_evter_stat;
  712. u32 res1[0x2];
  713. __be32 gpcm_evter_en;
  714. u32 res2[0x2];
  715. __be32 gpcm_evter_intr_en;
  716. u32 res3[0x2];
  717. __be32 gpcm_erattr0;
  718. __be32 gpcm_erattr1;
  719. __be32 gpcm_erattr2;
  720. __be32 gpcm_stat;
  721. };
  722. /*
  723. * IFC Controller Registers
  724. */
  725. struct fsl_ifc_global {
  726. __be32 ifc_rev;
  727. u32 res1[0x2];
  728. struct {
  729. __be32 cspr_ext;
  730. __be32 cspr;
  731. u32 res2;
  732. } cspr_cs[FSL_IFC_BANK_COUNT];
  733. u32 res3[0xd];
  734. struct {
  735. __be32 amask;
  736. u32 res4[0x2];
  737. } amask_cs[FSL_IFC_BANK_COUNT];
  738. u32 res5[0xc];
  739. struct {
  740. __be32 csor;
  741. __be32 csor_ext;
  742. u32 res6;
  743. } csor_cs[FSL_IFC_BANK_COUNT];
  744. u32 res7[0xc];
  745. struct {
  746. __be32 ftim[4];
  747. u32 res8[0x8];
  748. } ftim_cs[FSL_IFC_BANK_COUNT];
  749. u32 res9[0x30];
  750. __be32 rb_stat;
  751. __be32 rb_map;
  752. __be32 wb_map;
  753. __be32 ifc_gcr;
  754. u32 res10[0x2];
  755. __be32 cm_evter_stat;
  756. u32 res11[0x2];
  757. __be32 cm_evter_en;
  758. u32 res12[0x2];
  759. __be32 cm_evter_intr_en;
  760. u32 res13[0x2];
  761. __be32 cm_erattr0;
  762. __be32 cm_erattr1;
  763. u32 res14[0x2];
  764. __be32 ifc_ccr;
  765. __be32 ifc_csr;
  766. __be32 ddr_ccr_low;
  767. };
  768. struct fsl_ifc_runtime {
  769. struct fsl_ifc_nand ifc_nand;
  770. struct fsl_ifc_nor ifc_nor;
  771. struct fsl_ifc_gpcm ifc_gpcm;
  772. };
  773. extern unsigned int convert_ifc_address(phys_addr_t addr_base);
  774. extern int fsl_ifc_find(phys_addr_t addr_base);
  775. /* overview of the fsl ifc controller */
  776. struct fsl_ifc_ctrl {
  777. /* device info */
  778. struct device *dev;
  779. struct fsl_ifc_global __iomem *gregs;
  780. struct fsl_ifc_runtime __iomem *rregs;
  781. int irq;
  782. int nand_irq;
  783. spinlock_t lock;
  784. void *nand;
  785. int version;
  786. int banks;
  787. u32 nand_stat;
  788. wait_queue_head_t nand_wait;
  789. bool little_endian;
  790. };
  791. extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
  792. static inline u32 ifc_in32(void __iomem *addr)
  793. {
  794. u32 val;
  795. if (fsl_ifc_ctrl_dev->little_endian)
  796. val = ioread32(addr);
  797. else
  798. val = ioread32be(addr);
  799. return val;
  800. }
  801. static inline u16 ifc_in16(void __iomem *addr)
  802. {
  803. u16 val;
  804. if (fsl_ifc_ctrl_dev->little_endian)
  805. val = ioread16(addr);
  806. else
  807. val = ioread16be(addr);
  808. return val;
  809. }
  810. static inline u8 ifc_in8(void __iomem *addr)
  811. {
  812. return ioread8(addr);
  813. }
  814. static inline void ifc_out32(u32 val, void __iomem *addr)
  815. {
  816. if (fsl_ifc_ctrl_dev->little_endian)
  817. iowrite32(val, addr);
  818. else
  819. iowrite32be(val, addr);
  820. }
  821. static inline void ifc_out16(u16 val, void __iomem *addr)
  822. {
  823. if (fsl_ifc_ctrl_dev->little_endian)
  824. iowrite16(val, addr);
  825. else
  826. iowrite16be(val, addr);
  827. }
  828. static inline void ifc_out8(u8 val, void __iomem *addr)
  829. {
  830. iowrite8(val, addr);
  831. }
  832. #endif /* __ASM_FSL_IFC_H */