cs5535.h 6.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * AMD CS5535/CS5536 definitions
  4. * Copyright (C) 2006 Advanced Micro Devices, Inc.
  5. * Copyright (C) 2009 Andres Salomon <[email protected]>
  6. */
  7. #ifndef _CS5535_H
  8. #define _CS5535_H
  9. #include <asm/msr.h>
  10. /* MSRs */
  11. #define MSR_GLIU_P2D_RO0 0x10000029
  12. #define MSR_LX_GLD_MSR_CONFIG 0x48002001
  13. #define MSR_LX_MSR_PADSEL 0x48002011 /* NOT 0x48000011; the data
  14. * sheet has the wrong value */
  15. #define MSR_GLCP_SYS_RSTPLL 0x4C000014
  16. #define MSR_GLCP_DOTPLL 0x4C000015
  17. #define MSR_LBAR_SMB 0x5140000B
  18. #define MSR_LBAR_GPIO 0x5140000C
  19. #define MSR_LBAR_MFGPT 0x5140000D
  20. #define MSR_LBAR_ACPI 0x5140000E
  21. #define MSR_LBAR_PMS 0x5140000F
  22. #define MSR_DIVIL_SOFT_RESET 0x51400017
  23. #define MSR_PIC_YSEL_LOW 0x51400020
  24. #define MSR_PIC_YSEL_HIGH 0x51400021
  25. #define MSR_PIC_ZSEL_LOW 0x51400022
  26. #define MSR_PIC_ZSEL_HIGH 0x51400023
  27. #define MSR_PIC_IRQM_LPC 0x51400025
  28. #define MSR_MFGPT_IRQ 0x51400028
  29. #define MSR_MFGPT_NR 0x51400029
  30. #define MSR_MFGPT_SETUP 0x5140002B
  31. #define MSR_RTC_DOMA_OFFSET 0x51400055
  32. #define MSR_RTC_MONA_OFFSET 0x51400056
  33. #define MSR_RTC_CEN_OFFSET 0x51400057
  34. #define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
  35. #define MSR_GX_GLD_MSR_CONFIG 0xC0002001
  36. #define MSR_GX_MSR_PADSEL 0xC0002011
  37. static inline int cs5535_pic_unreqz_select_high(unsigned int group,
  38. unsigned int irq)
  39. {
  40. uint32_t lo, hi;
  41. rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
  42. lo &= ~(0xF << (group * 4));
  43. lo |= (irq & 0xF) << (group * 4);
  44. wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
  45. return 0;
  46. }
  47. /* PIC registers */
  48. #define CS5536_PIC_INT_SEL1 0x4d0
  49. #define CS5536_PIC_INT_SEL2 0x4d1
  50. /* resource sizes */
  51. #define LBAR_GPIO_SIZE 0xFF
  52. #define LBAR_MFGPT_SIZE 0x40
  53. #define LBAR_ACPI_SIZE 0x40
  54. #define LBAR_PMS_SIZE 0x80
  55. /*
  56. * PMC registers (PMS block)
  57. * It is only safe to access these registers as dword accesses.
  58. * See CS5536 Specification Update erratas 17 & 18
  59. */
  60. #define CS5536_PM_SCLK 0x10
  61. #define CS5536_PM_IN_SLPCTL 0x20
  62. #define CS5536_PM_WKXD 0x34
  63. #define CS5536_PM_WKD 0x30
  64. #define CS5536_PM_SSC 0x54
  65. /*
  66. * PM registers (ACPI block)
  67. * It is only safe to access these registers as dword accesses.
  68. * See CS5536 Specification Update erratas 17 & 18
  69. */
  70. #define CS5536_PM1_STS 0x00
  71. #define CS5536_PM1_EN 0x02
  72. #define CS5536_PM1_CNT 0x08
  73. #define CS5536_PM_GPE0_STS 0x18
  74. #define CS5536_PM_GPE0_EN 0x1c
  75. /* CS5536_PM1_STS bits */
  76. #define CS5536_WAK_FLAG (1 << 15)
  77. #define CS5536_RTC_FLAG (1 << 10)
  78. #define CS5536_PWRBTN_FLAG (1 << 8)
  79. /* CS5536_PM1_EN bits */
  80. #define CS5536_PM_PWRBTN (1 << 8)
  81. #define CS5536_PM_RTC (1 << 10)
  82. /* CS5536_PM_GPE0_STS bits */
  83. #define CS5536_GPIOM7_PME_FLAG (1 << 31)
  84. #define CS5536_GPIOM6_PME_FLAG (1 << 30)
  85. /* CS5536_PM_GPE0_EN bits */
  86. #define CS5536_GPIOM7_PME_EN (1 << 31)
  87. #define CS5536_GPIOM6_PME_EN (1 << 30)
  88. /* VSA2 magic values */
  89. #define VSA_VRC_INDEX 0xAC1C
  90. #define VSA_VRC_DATA 0xAC1E
  91. #define VSA_VR_UNLOCK 0xFC53 /* unlock virtual register */
  92. #define VSA_VR_SIGNATURE 0x0003
  93. #define VSA_VR_MEM_SIZE 0x0200
  94. #define AMD_VSA_SIG 0x4132 /* signature is ascii 'VSA2' */
  95. #define GSW_VSA_SIG 0x534d /* General Software signature */
  96. #include <linux/io.h>
  97. static inline int cs5535_has_vsa2(void)
  98. {
  99. static int has_vsa2 = -1;
  100. if (has_vsa2 == -1) {
  101. uint16_t val;
  102. /*
  103. * The VSA has virtual registers that we can query for a
  104. * signature.
  105. */
  106. outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
  107. outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
  108. val = inw(VSA_VRC_DATA);
  109. has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
  110. }
  111. return has_vsa2;
  112. }
  113. /* GPIOs */
  114. #define GPIO_OUTPUT_VAL 0x00
  115. #define GPIO_OUTPUT_ENABLE 0x04
  116. #define GPIO_OUTPUT_OPEN_DRAIN 0x08
  117. #define GPIO_OUTPUT_INVERT 0x0C
  118. #define GPIO_OUTPUT_AUX1 0x10
  119. #define GPIO_OUTPUT_AUX2 0x14
  120. #define GPIO_PULL_UP 0x18
  121. #define GPIO_PULL_DOWN 0x1C
  122. #define GPIO_INPUT_ENABLE 0x20
  123. #define GPIO_INPUT_INVERT 0x24
  124. #define GPIO_INPUT_FILTER 0x28
  125. #define GPIO_INPUT_EVENT_COUNT 0x2C
  126. #define GPIO_READ_BACK 0x30
  127. #define GPIO_INPUT_AUX1 0x34
  128. #define GPIO_EVENTS_ENABLE 0x38
  129. #define GPIO_LOCK_ENABLE 0x3C
  130. #define GPIO_POSITIVE_EDGE_EN 0x40
  131. #define GPIO_NEGATIVE_EDGE_EN 0x44
  132. #define GPIO_POSITIVE_EDGE_STS 0x48
  133. #define GPIO_NEGATIVE_EDGE_STS 0x4C
  134. #define GPIO_FLTR7_AMOUNT 0xD8
  135. #define GPIO_MAP_X 0xE0
  136. #define GPIO_MAP_Y 0xE4
  137. #define GPIO_MAP_Z 0xE8
  138. #define GPIO_MAP_W 0xEC
  139. #define GPIO_FE7_SEL 0xF7
  140. void cs5535_gpio_set(unsigned offset, unsigned int reg);
  141. void cs5535_gpio_clear(unsigned offset, unsigned int reg);
  142. int cs5535_gpio_isset(unsigned offset, unsigned int reg);
  143. int cs5535_gpio_set_irq(unsigned group, unsigned irq);
  144. void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
  145. /* MFGPTs */
  146. #define MFGPT_MAX_TIMERS 8
  147. #define MFGPT_TIMER_ANY (-1)
  148. #define MFGPT_DOMAIN_WORKING 1
  149. #define MFGPT_DOMAIN_STANDBY 2
  150. #define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
  151. #define MFGPT_CMP1 0
  152. #define MFGPT_CMP2 1
  153. #define MFGPT_EVENT_IRQ 0
  154. #define MFGPT_EVENT_NMI 1
  155. #define MFGPT_EVENT_RESET 3
  156. #define MFGPT_REG_CMP1 0
  157. #define MFGPT_REG_CMP2 2
  158. #define MFGPT_REG_COUNTER 4
  159. #define MFGPT_REG_SETUP 6
  160. #define MFGPT_SETUP_CNTEN (1 << 15)
  161. #define MFGPT_SETUP_CMP2 (1 << 14)
  162. #define MFGPT_SETUP_CMP1 (1 << 13)
  163. #define MFGPT_SETUP_SETUP (1 << 12)
  164. #define MFGPT_SETUP_STOPEN (1 << 11)
  165. #define MFGPT_SETUP_EXTEN (1 << 10)
  166. #define MFGPT_SETUP_REVEN (1 << 5)
  167. #define MFGPT_SETUP_CLKSEL (1 << 4)
  168. struct cs5535_mfgpt_timer;
  169. extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
  170. uint16_t reg);
  171. extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
  172. uint16_t value);
  173. extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
  174. int event, int enable);
  175. extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
  176. int *irq, int enable);
  177. extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
  178. int domain);
  179. extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
  180. static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
  181. int cmp, int *irq)
  182. {
  183. return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
  184. }
  185. static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
  186. int cmp, int *irq)
  187. {
  188. return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
  189. }
  190. #endif