sja1000.h 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. #ifndef _CAN_PLATFORM_SJA1000_H
  3. #define _CAN_PLATFORM_SJA1000_H
  4. /* clock divider register */
  5. #define CDR_CLKOUT_MASK 0x07
  6. #define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */
  7. #define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */
  8. #define CDR_CBP 0x40 /* CAN input comparator bypass */
  9. #define CDR_PELICAN 0x80 /* PeliCAN mode */
  10. /* output control register */
  11. #define OCR_MODE_BIPHASE 0x00
  12. #define OCR_MODE_TEST 0x01
  13. #define OCR_MODE_NORMAL 0x02
  14. #define OCR_MODE_CLOCK 0x03
  15. #define OCR_MODE_MASK 0x03
  16. #define OCR_TX0_INVERT 0x04
  17. #define OCR_TX0_PULLDOWN 0x08
  18. #define OCR_TX0_PULLUP 0x10
  19. #define OCR_TX0_PUSHPULL 0x18
  20. #define OCR_TX1_INVERT 0x20
  21. #define OCR_TX1_PULLDOWN 0x40
  22. #define OCR_TX1_PULLUP 0x80
  23. #define OCR_TX1_PUSHPULL 0xc0
  24. #define OCR_TX_MASK 0xfc
  25. #define OCR_TX_SHIFT 2
  26. struct sja1000_platform_data {
  27. u32 osc_freq; /* CAN bus oscillator frequency in Hz */
  28. u8 ocr; /* output control register */
  29. u8 cdr; /* clock divider register */
  30. };
  31. #endif /* !_CAN_PLATFORM_SJA1000_H */