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pl093.h

pl093.h 2.0 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /* linux/amba/pl093.h
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2008 Simtec Electronics
    5. 

  5.  *	http://armlinux.simtec.co.uk/
    6. 

  6.  *	Ben Dooks <[email protected]>
    7. 

  7.  *
    8. 

  8.  * AMBA PL093 SSMC (synchronous static memory controller)
    9. 

  9.  *  See DDI0236.pdf (r0p4) for more details
    10. 

  10. */
    11. 

  11. 

  12. #define SMB_BANK(x)	((x) * 0x20) /* each bank control set is 0x20 apart */
    13. 

  13. 

  14. /* Offsets for SMBxxxxRy registers */
    15. 

  15. 

  16. #define SMBIDCYR	(0x00)
    17. 

  17. #define SMBWSTRDR	(0x04)
    18. 

  18. #define SMBWSTWRR	(0x08)
    19. 

  19. #define SMBWSTOENR	(0x0C)
    20. 

  20. #define SMBWSTWENR	(0x10)
    21. 

  21. #define SMBCR		(0x14)
    22. 

  22. #define SMBSR		(0x18)
    23. 

  23. #define SMBWSTBRDR	(0x1C)
    24. 

  24. 

  25. /* Masks for SMB registers */
    26. 

  26. #define IDCY_MASK	(0xf)
    27. 

  27. #define WSTRD_MASK	(0xf)
    28. 

  28. #define WSTWR_MASK	(0xf)
    29. 

  29. #define WSTOEN_MASK	(0xf)
    30. 

  30. #define WSTWEN_MASK	(0xf)
    31. 

  31. 

  32. /* Notes from datasheet:
    33. 

  33.  *	WSTOEN <= WSTRD
    34. 

  34.  *	WSTWEN <= WSTWR
    35. 

  35.  *
    36. 

  36.  * WSTOEN is not used with nWAIT
    37. 

  37.  */
    38. 

  38. 

  39. /* SMBCR bit definitions */
    40. 

  40. #define SMBCR_BIWRITEEN		(1 << 21)
    41. 

  41. #define SMBCR_ADDRVALIDWRITEEN	(1 << 20)
    42. 

  42. #define SMBCR_SYNCWRITE		(1 << 17)
    43. 

  43. #define SMBCR_BMWRITE		(1 << 16)
    44. 

  44. #define SMBCR_WRAPREAD		(1 << 14)
    45. 

  45. #define SMBCR_BIREADEN		(1 << 13)
    46. 

  46. #define SMBCR_ADDRVALIDREADEN	(1 << 12)
    47. 

  47. #define SMBCR_SYNCREAD		(1 << 9)
    48. 

  48. #define SMBCR_BMREAD		(1 << 8)
    49. 

  49. #define SMBCR_SMBLSPOL		(1 << 6)
    50. 

  50. #define SMBCR_WP		(1 << 3)
    51. 

  51. #define SMBCR_WAITEN		(1 << 2)
    52. 

  52. #define SMBCR_WAITPOL		(1 << 1)
    53. 

  53. #define SMBCR_RBLE		(1 << 0)
    54. 

  54. 

  55. #define SMBCR_BURSTLENWRITE_MASK	(3 << 18)
    56. 

  56. #define SMBCR_BURSTLENWRITE_4		(0 << 18)
    57. 

  57. #define SMBCR_BURSTLENWRITE_8		(1 << 18)
    58. 

  58. #define SMBCR_BURSTLENWRITE_RESERVED	(2 << 18)
    59. 

  59. #define SMBCR_BURSTLENWRITE_CONTINUOUS	(3 << 18)
    60. 

  60. 

  61. #define SMBCR_BURSTLENREAD_MASK		(3 << 10)
    62. 

  62. #define SMBCR_BURSTLENREAD_4		(0 << 10)
    63. 

  63. #define SMBCR_BURSTLENREAD_8		(1 << 10)
    64. 

  64. #define SMBCR_BURSTLENREAD_16		(2 << 10)
    65. 

  65. #define SMBCR_BURSTLENREAD_CONTINUOUS	(3 << 10)
    66. 

  66. 

  67. #define SMBCR_MW_MASK			(3 << 4)
    68. 

  68. #define SMBCR_MW_8BIT			(0 << 4)
    69. 

  69. #define SMBCR_MW_16BIT			(1 << 4)
    70. 

  70. #define SMBCR_MW_M32BIT			(2 << 4)
    71. 

  71. 

  72. /* SSMC status registers */
    73. 

  73. #define SSMCCSR		(0x200)
    74. 

  74. #define SSMCCR		(0x204)
    75. 

  75. #define SSMCITCR	(0x208)
    76. 

  76. #define SSMCITIP	(0x20C)
    77. 

  77. #define SSMCITIOP	(0x210)
    78.