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- /* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
- /*
- * Copyright (c) 2020 Yangtao Li <[email protected]>
- */
- #ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_
- #define _DT_BINDINGS_RESET_SUN50I_A100_H_
- #define RST_MBUS 0
- #define RST_BUS_DE 1
- #define RST_BUS_G2D 2
- #define RST_BUS_GPU 3
- #define RST_BUS_CE 4
- #define RST_BUS_VE 5
- #define RST_BUS_DMA 6
- #define RST_BUS_MSGBOX 7
- #define RST_BUS_SPINLOCK 8
- #define RST_BUS_HSTIMER 9
- #define RST_BUS_DBG 10
- #define RST_BUS_PSI 11
- #define RST_BUS_PWM 12
- #define RST_BUS_DRAM 13
- #define RST_BUS_NAND 14
- #define RST_BUS_MMC0 15
- #define RST_BUS_MMC1 16
- #define RST_BUS_MMC2 17
- #define RST_BUS_UART0 18
- #define RST_BUS_UART1 19
- #define RST_BUS_UART2 20
- #define RST_BUS_UART3 21
- #define RST_BUS_UART4 22
- #define RST_BUS_I2C0 23
- #define RST_BUS_I2C1 24
- #define RST_BUS_I2C2 25
- #define RST_BUS_I2C3 26
- #define RST_BUS_SPI0 27
- #define RST_BUS_SPI1 28
- #define RST_BUS_SPI2 29
- #define RST_BUS_EMAC 30
- #define RST_BUS_IR_RX 31
- #define RST_BUS_IR_TX 32
- #define RST_BUS_GPADC 33
- #define RST_BUS_THS 34
- #define RST_BUS_I2S0 35
- #define RST_BUS_I2S1 36
- #define RST_BUS_I2S2 37
- #define RST_BUS_I2S3 38
- #define RST_BUS_SPDIF 39
- #define RST_BUS_DMIC 40
- #define RST_BUS_AUDIO_CODEC 41
- #define RST_USB_PHY0 42
- #define RST_USB_PHY1 43
- #define RST_BUS_OHCI0 44
- #define RST_BUS_OHCI1 45
- #define RST_BUS_EHCI0 46
- #define RST_BUS_EHCI1 47
- #define RST_BUS_OTG 48
- #define RST_BUS_LRADC 49
- #define RST_BUS_DPSS_TOP0 50
- #define RST_BUS_DPSS_TOP1 51
- #define RST_BUS_MIPI_DSI 52
- #define RST_BUS_TCON_LCD 53
- #define RST_BUS_LVDS 54
- #define RST_BUS_LEDC 55
- #define RST_BUS_CSI 56
- #define RST_BUS_CSI_ISP 57
- #endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */
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