starfive-jh7100.h 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126
  1. /* SPDX-License-Identifier: GPL-2.0 OR MIT */
  2. /*
  3. * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
  4. */
  5. #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
  6. #define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__
  7. #define JH7100_RSTN_DOM3AHB_BUS 0
  8. #define JH7100_RSTN_DOM7AHB_BUS 1
  9. #define JH7100_RST_U74 2
  10. #define JH7100_RSTN_U74_AXI 3
  11. #define JH7100_RSTN_SGDMA2P_AHB 4
  12. #define JH7100_RSTN_SGDMA2P_AXI 5
  13. #define JH7100_RSTN_DMA2PNOC_AXI 6
  14. #define JH7100_RSTN_DLA_AXI 7
  15. #define JH7100_RSTN_DLANOC_AXI 8
  16. #define JH7100_RSTN_DLA_APB 9
  17. #define JH7100_RST_VP6_DRESET 10
  18. #define JH7100_RST_VP6_BRESET 11
  19. #define JH7100_RSTN_VP6_AXI 12
  20. #define JH7100_RSTN_VDECBRG_MAIN 13
  21. #define JH7100_RSTN_VDEC_AXI 14
  22. #define JH7100_RSTN_VDEC_BCLK 15
  23. #define JH7100_RSTN_VDEC_CCLK 16
  24. #define JH7100_RSTN_VDEC_APB 17
  25. #define JH7100_RSTN_JPEG_AXI 18
  26. #define JH7100_RSTN_JPEG_CCLK 19
  27. #define JH7100_RSTN_JPEG_APB 20
  28. #define JH7100_RSTN_JPCGC300_MAIN 21
  29. #define JH7100_RSTN_GC300_2X 22
  30. #define JH7100_RSTN_GC300_AXI 23
  31. #define JH7100_RSTN_GC300_AHB 24
  32. #define JH7100_RSTN_VENC_AXI 25
  33. #define JH7100_RSTN_VENCBRG_MAIN 26
  34. #define JH7100_RSTN_VENC_BCLK 27
  35. #define JH7100_RSTN_VENC_CCLK 28
  36. #define JH7100_RSTN_VENC_APB 29
  37. #define JH7100_RSTN_DDRPHY_APB 30
  38. #define JH7100_RSTN_NOC_ROB 31
  39. #define JH7100_RSTN_NOC_COG 32
  40. #define JH7100_RSTN_HIFI4_AXI 33
  41. #define JH7100_RSTN_HIFI4NOC_AXI 34
  42. #define JH7100_RST_HIFI4_DRESET 35
  43. #define JH7100_RST_HIFI4_BRESET 36
  44. #define JH7100_RSTN_USB_AXI 37
  45. #define JH7100_RSTN_USBNOC_AXI 38
  46. #define JH7100_RSTN_SGDMA1P_AXI 39
  47. #define JH7100_RSTN_DMA1P_AXI 40
  48. #define JH7100_RSTN_X2C_AXI 41
  49. #define JH7100_RSTN_NNE_AHB 42
  50. #define JH7100_RSTN_NNE_AXI 43
  51. #define JH7100_RSTN_NNENOC_AXI 44
  52. #define JH7100_RSTN_DLASLV_AXI 45
  53. #define JH7100_RSTN_DSPX2C_AXI 46
  54. #define JH7100_RSTN_VIN_SRC 47
  55. #define JH7100_RSTN_ISPSLV_AXI 48
  56. #define JH7100_RSTN_VIN_AXI 49
  57. #define JH7100_RSTN_VINNOC_AXI 50
  58. #define JH7100_RSTN_ISP0_AXI 51
  59. #define JH7100_RSTN_ISP0NOC_AXI 52
  60. #define JH7100_RSTN_ISP1_AXI 53
  61. #define JH7100_RSTN_ISP1NOC_AXI 54
  62. #define JH7100_RSTN_VOUT_SRC 55
  63. #define JH7100_RSTN_DISP_AXI 56
  64. #define JH7100_RSTN_DISPNOC_AXI 57
  65. #define JH7100_RSTN_SDIO0_AHB 58
  66. #define JH7100_RSTN_SDIO1_AHB 59
  67. #define JH7100_RSTN_GMAC_AHB 60
  68. #define JH7100_RSTN_SPI2AHB_AHB 61
  69. #define JH7100_RSTN_SPI2AHB_CORE 62
  70. #define JH7100_RSTN_EZMASTER_AHB 63
  71. #define JH7100_RST_E24 64
  72. #define JH7100_RSTN_QSPI_AHB 65
  73. #define JH7100_RSTN_QSPI_CORE 66
  74. #define JH7100_RSTN_QSPI_APB 67
  75. #define JH7100_RSTN_SEC_AHB 68
  76. #define JH7100_RSTN_AES 69
  77. #define JH7100_RSTN_PKA 70
  78. #define JH7100_RSTN_SHA 71
  79. #define JH7100_RSTN_TRNG_APB 72
  80. #define JH7100_RSTN_OTP_APB 73
  81. #define JH7100_RSTN_UART0_APB 74
  82. #define JH7100_RSTN_UART0_CORE 75
  83. #define JH7100_RSTN_UART1_APB 76
  84. #define JH7100_RSTN_UART1_CORE 77
  85. #define JH7100_RSTN_SPI0_APB 78
  86. #define JH7100_RSTN_SPI0_CORE 79
  87. #define JH7100_RSTN_SPI1_APB 80
  88. #define JH7100_RSTN_SPI1_CORE 81
  89. #define JH7100_RSTN_I2C0_APB 82
  90. #define JH7100_RSTN_I2C0_CORE 83
  91. #define JH7100_RSTN_I2C1_APB 84
  92. #define JH7100_RSTN_I2C1_CORE 85
  93. #define JH7100_RSTN_GPIO_APB 86
  94. #define JH7100_RSTN_UART2_APB 87
  95. #define JH7100_RSTN_UART2_CORE 88
  96. #define JH7100_RSTN_UART3_APB 89
  97. #define JH7100_RSTN_UART3_CORE 90
  98. #define JH7100_RSTN_SPI2_APB 91
  99. #define JH7100_RSTN_SPI2_CORE 92
  100. #define JH7100_RSTN_SPI3_APB 93
  101. #define JH7100_RSTN_SPI3_CORE 94
  102. #define JH7100_RSTN_I2C2_APB 95
  103. #define JH7100_RSTN_I2C2_CORE 96
  104. #define JH7100_RSTN_I2C3_APB 97
  105. #define JH7100_RSTN_I2C3_CORE 98
  106. #define JH7100_RSTN_WDTIMER_APB 99
  107. #define JH7100_RSTN_WDT 100
  108. #define JH7100_RSTN_TIMER0 101
  109. #define JH7100_RSTN_TIMER1 102
  110. #define JH7100_RSTN_TIMER2 103
  111. #define JH7100_RSTN_TIMER3 104
  112. #define JH7100_RSTN_TIMER4 105
  113. #define JH7100_RSTN_TIMER5 106
  114. #define JH7100_RSTN_TIMER6 107
  115. #define JH7100_RSTN_VP6INTC_APB 108
  116. #define JH7100_RSTN_PWM_APB 109
  117. #define JH7100_RSTN_MSI_APB 110
  118. #define JH7100_RSTN_TEMP_APB 111
  119. #define JH7100_RSTN_TEMP_SENSE 112
  120. #define JH7100_RSTN_SYSERR_APB 113
  121. #define JH7100_RSTN_END 114
  122. #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */