android_kernel_samsung_sm8650_ksu/include/dt-bindings/phy/qcom,usb3-4lpx-qmp.h

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_PHY_QCOM_4LPX_QMP_COMBO_USB_H
#define _DT_BINDINGS_PHY_QCOM_4LPX_QMP_COMBO_USB_H

/* USB3-DP Combo PHY register offsets */
/* Module: USB3_DP_PHY_USB3_DP_COM_USB3_DP_COM_USB3_DP_COM */
#define USB3_DP_COM_PHY_MODE_CTRL                 (0x0000 + 0x0000)
#define USB3_DP_COM_SW_RESET                      (0x0000 + 0x0004)
#define USB3_DP_COM_POWER_DOWN_CTRL               (0x0000 + 0x0008)
#define USB3_DP_COM_SWI_CTRL                      (0x0000 + 0x000c)
#define USB3_DP_COM_TYPEC_CTRL                    (0x0000 + 0x0010)
#define USB3_DP_COM_TYPEC_PWRDN_CTRL              (0x0000 + 0x0014)
#define USB3_DP_COM_DP_BIST_CFG_0                 (0x0000 + 0x0018)
#define USB3_DP_COM_RESET_OVRD_CTRL               (0x0000 + 0x001c)
#define USB3_DP_COM_DBG_CLK_MUX_CTRL              (0x0000 + 0x0020)
#define USB3_DP_COM_TYPEC_STATUS                  (0x0000 + 0x0024)
#define USB3_DP_COM_PLACEHOLDER_STATUS            (0x0000 + 0x0028)
#define USB3_DP_COM_REVISION_ID0                  (0x0000 + 0x002c)
#define USB3_DP_COM_REVISION_ID1                  (0x0000 + 0x0030)
#define USB3_DP_COM_REVISION_ID2                  (0x0000 + 0x0034)
#define USB3_DP_COM_REVISION_ID3                  (0x0000 + 0x0038)

/* Module: USB3_DP_PHY_USB3_DP_DBGINT_USB3_DP_DBGINT_USB3_PCS_DEBUG_INT */
#define USB3_DP_DBGINT_INTGEN_STATUS1             (0x0200 + 0x0000)
#define USB3_DP_DBGINT_INTGEN_STATUS2             (0x0200 + 0x0004)
#define USB3_DP_DBGINT_CONFIG1                    (0x0200 + 0x0008)
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG1         (0x0200 + 0x000c)
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG2         (0x0200 + 0x0010)
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG3         (0x0200 + 0x0014)
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG4         (0x0200 + 0x0018)
#define USB3_DP_DBGINT_SIGNALBLK1_CONFIG5         (0x0200 + 0x001c)
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG1         (0x0200 + 0x0020)
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG2         (0x0200 + 0x0024)
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG3         (0x0200 + 0x0028)
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG4         (0x0200 + 0x002c)
#define USB3_DP_DBGINT_SIGNALBLK2_CONFIG5         (0x0200 + 0x0030)
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG1         (0x0200 + 0x0034)
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG2         (0x0200 + 0x0038)
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG3         (0x0200 + 0x003c)
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG4         (0x0200 + 0x0040)
#define USB3_DP_DBGINT_STRINGBLK1_CONFIG5         (0x0200 + 0x0044)
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG1         (0x0200 + 0x0048)
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG2         (0x0200 + 0x004c)
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG3         (0x0200 + 0x0050)
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG4         (0x0200 + 0x0054)
#define USB3_DP_DBGINT_STRINGBLK2_CONFIG5         (0x0200 + 0x0058)

/* Module: USB3_DP_PHY_USB3_QSERDES_COM_USB3_QSERDES_COM_USB3_DP_QMP_PLL */
#define USB3_QSERDES_COM_ATB_SEL1                 (0x1000 + 0x0000)
#define USB3_QSERDES_COM_ATB_SEL2                 (0x1000 + 0x0004)
#define USB3_QSERDES_COM_FREQ_UPDATE              (0x1000 + 0x0008)
#define USB3_QSERDES_COM_BG_TIMER                 (0x1000 + 0x000c)
#define USB3_QSERDES_COM_SSC_EN_CENTER            (0x1000 + 0x0010)
#define USB3_QSERDES_COM_SSC_ADJ_PER1             (0x1000 + 0x0014)
#define USB3_QSERDES_COM_SSC_ADJ_PER2             (0x1000 + 0x0018)
#define USB3_QSERDES_COM_SSC_PER1                 (0x1000 + 0x001c)
#define USB3_QSERDES_COM_SSC_PER2                 (0x1000 + 0x0020)
#define USB3_QSERDES_COM_SSC_STEP_SIZE1_MODE0     (0x1000 + 0x0024)
#define USB3_QSERDES_COM_SSC_STEP_SIZE2_MODE0     (0x1000 + 0x0028)
#define USB3_QSERDES_COM_SSC_STEP_SIZE3_MODE0     (0x1000 + 0x002c)
#define USB3_QSERDES_COM_SSC_STEP_SIZE1_MODE1     (0x1000 + 0x0030)
#define USB3_QSERDES_COM_SSC_STEP_SIZE2_MODE1     (0x1000 + 0x0034)
#define USB3_QSERDES_COM_SSC_STEP_SIZE3_MODE1     (0x1000 + 0x0038)
#define USB3_QSERDES_COM_POST_DIV                 (0x1000 + 0x003c)
#define USB3_QSERDES_COM_POST_DIV_MUX             (0x1000 + 0x0040)
#define USB3_QSERDES_COM_BIAS_EN_CLKBUFLR_EN      (0x1000 + 0x0044)
#define USB3_QSERDES_COM_CLK_ENABLE1              (0x1000 + 0x0048)
#define USB3_QSERDES_COM_SYS_CLK_CTRL             (0x1000 + 0x004c)
#define USB3_QSERDES_COM_SYSCLK_BUF_ENABLE        (0x1000 + 0x0050)
#define USB3_QSERDES_COM_PLL_EN                   (0x1000 + 0x0054)
#define USB3_QSERDES_COM_PLL_IVCO                 (0x1000 + 0x0058)
#define USB3_QSERDES_COM_CMN_IETRIM               (0x1000 + 0x005c)
#define USB3_QSERDES_COM_CMN_IPTRIM               (0x1000 + 0x0060)
#define USB3_QSERDES_COM_EP_CLOCK_DETECT_CTRL     (0x1000 + 0x0064)
#define USB3_QSERDES_COM_SYSCLK_DET_COMP_STATUS   (0x1000 + 0x0068)
#define USB3_QSERDES_COM_CLK_EP_DIV_MODE0         (0x1000 + 0x006c)
#define USB3_QSERDES_COM_CLK_EP_DIV_MODE1         (0x1000 + 0x0070)
#define USB3_QSERDES_COM_CP_CTRL_MODE0            (0x1000 + 0x0074)
#define USB3_QSERDES_COM_CP_CTRL_MODE1            (0x1000 + 0x0078)
#define USB3_QSERDES_COM_PLL_RCTRL_MODE0          (0x1000 + 0x007c)
#define USB3_QSERDES_COM_PLL_RCTRL_MODE1          (0x1000 + 0x0080)
#define USB3_QSERDES_COM_PLL_CCTRL_MODE0          (0x1000 + 0x0084)
#define USB3_QSERDES_COM_PLL_CCTRL_MODE1          (0x1000 + 0x0088)
#define USB3_QSERDES_COM_PLL_CNTRL                (0x1000 + 0x008c)
#define USB3_QSERDES_COM_BIAS_EN_CTRL_BY_PSM      (0x1000 + 0x0090)
#define USB3_QSERDES_COM_SYSCLK_EN_SEL            (0x1000 + 0x0094)
#define USB3_QSERDES_COM_CML_SYSCLK_SEL           (0x1000 + 0x0098)
#define USB3_QSERDES_COM_RESETSM_CNTRL            (0x1000 + 0x009c)
#define USB3_QSERDES_COM_RESETSM_CNTRL2           (0x1000 + 0x00a0)
#define USB3_QSERDES_COM_LOCK_CMP_EN              (0x1000 + 0x00a4)
#define USB3_QSERDES_COM_LOCK_CMP_CFG             (0x1000 + 0x00a8)
#define USB3_QSERDES_COM_LOCK_CMP1_MODE0          (0x1000 + 0x00ac)
#define USB3_QSERDES_COM_LOCK_CMP2_MODE0          (0x1000 + 0x00b0)
#define USB3_QSERDES_COM_LOCK_CMP1_MODE1          (0x1000 + 0x00b4)
#define USB3_QSERDES_COM_LOCK_CMP2_MODE1          (0x1000 + 0x00b8)
#define USB3_QSERDES_COM_DEC_START_MODE0          (0x1000 + 0x00bc)
#define USB3_QSERDES_COM_DEC_START_MSB_MODE0      (0x1000 + 0x00c0)
#define USB3_QSERDES_COM_DEC_START_MODE1          (0x1000 + 0x00c4)
#define USB3_QSERDES_COM_DEC_START_MSB_MODE1      (0x1000 + 0x00c8)
#define USB3_QSERDES_COM_DIV_FRAC_START1_MODE0    (0x1000 + 0x00cc)
#define USB3_QSERDES_COM_DIV_FRAC_START2_MODE0    (0x1000 + 0x00d0)
#define USB3_QSERDES_COM_DIV_FRAC_START3_MODE0    (0x1000 + 0x00d4)
#define USB3_QSERDES_COM_DIV_FRAC_START1_MODE1    (0x1000 + 0x00d8)
#define USB3_QSERDES_COM_DIV_FRAC_START2_MODE1    (0x1000 + 0x00dc)
#define USB3_QSERDES_COM_DIV_FRAC_START3_MODE1    (0x1000 + 0x00e0)
#define USB3_QSERDES_COM_INTEGLOOP_INITVAL        (0x1000 + 0x00e4)
#define USB3_QSERDES_COM_INTEGLOOP_EN             (0x1000 + 0x00e8)
#define USB3_QSERDES_COM_INTEGLOOP_GAIN0_MODE0    (0x1000 + 0x00ec)
#define USB3_QSERDES_COM_INTEGLOOP_GAIN1_MODE0    (0x1000 + 0x00f0)
#define USB3_QSERDES_COM_INTEGLOOP_GAIN0_MODE1    (0x1000 + 0x00f4)
#define USB3_QSERDES_COM_INTEGLOOP_GAIN1_MODE1    (0x1000 + 0x00f8)
#define USB3_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0   (0x1000 + 0x00fc)
#define USB3_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1   (0x1000 + 0x0100)
#define USB3_QSERDES_COM_VCOCAL_DEADMAN_CTRL      (0x1000 + 0x0104)
#define USB3_QSERDES_COM_VCO_TUNE_CTRL            (0x1000 + 0x0108)
#define USB3_QSERDES_COM_VCO_TUNE_MAP             (0x1000 + 0x010c)
#define USB3_QSERDES_COM_VCO_TUNE1_MODE0          (0x1000 + 0x0110)
#define USB3_QSERDES_COM_VCO_TUNE2_MODE0          (0x1000 + 0x0114)
#define USB3_QSERDES_COM_VCO_TUNE1_MODE1          (0x1000 + 0x0118)
#define USB3_QSERDES_COM_VCO_TUNE2_MODE1          (0x1000 + 0x011c)
#define USB3_QSERDES_COM_VCO_TUNE_INITVAL1        (0x1000 + 0x0120)
#define USB3_QSERDES_COM_VCO_TUNE_INITVAL2        (0x1000 + 0x0124)
#define USB3_QSERDES_COM_VCO_TUNE_MINVAL1         (0x1000 + 0x0128)
#define USB3_QSERDES_COM_VCO_TUNE_MINVAL2         (0x1000 + 0x012c)
#define USB3_QSERDES_COM_VCO_TUNE_MAXVAL1         (0x1000 + 0x0130)
#define USB3_QSERDES_COM_VCO_TUNE_MAXVAL2         (0x1000 + 0x0134)
#define USB3_QSERDES_COM_VCO_TUNE_TIMER1          (0x1000 + 0x0138)
#define USB3_QSERDES_COM_VCO_TUNE_TIMER2          (0x1000 + 0x013c)
#define USB3_QSERDES_COM_CMN_STATUS               (0x1000 + 0x0140)
#define USB3_QSERDES_COM_RESET_SM_STATUS          (0x1000 + 0x0144)
#define USB3_QSERDES_COM_RESTRIM_CODE_STATUS      (0x1000 + 0x0148)
#define USB3_QSERDES_COM_PLLCAL_CODE1_STATUS      (0x1000 + 0x014c)
#define USB3_QSERDES_COM_PLLCAL_CODE2_STATUS      (0x1000 + 0x0150)
#define USB3_QSERDES_COM_CLK_SELECT               (0x1000 + 0x0154)
#define USB3_QSERDES_COM_HSCLK_SEL                (0x1000 + 0x0158)
#define USB3_QSERDES_COM_HSCLK_HS_SWITCH_SEL      (0x1000 + 0x015c)
#define USB3_QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x1000 + 0x0160)
#define USB3_QSERDES_COM_PLL_ANALOG               (0x1000 + 0x0164)
#define USB3_QSERDES_COM_CORECLK_DIV_MODE0        (0x1000 + 0x0168)
#define USB3_QSERDES_COM_CORECLK_DIV_MODE1        (0x1000 + 0x016c)
#define USB3_QSERDES_COM_SW_RESET                 (0x1000 + 0x0170)
#define USB3_QSERDES_COM_CORE_CLK_EN              (0x1000 + 0x0174)
#define USB3_QSERDES_COM_C_READY_STATUS           (0x1000 + 0x0178)
#define USB3_QSERDES_COM_CMN_CONFIG               (0x1000 + 0x017c)
#define USB3_QSERDES_COM_CMN_RATE_OVERRIDE        (0x1000 + 0x0180)
#define USB3_QSERDES_COM_SVS_MODE_CLK_SEL         (0x1000 + 0x0184)
#define USB3_QSERDES_COM_DEBUG_BUS0               (0x1000 + 0x0188)
#define USB3_QSERDES_COM_DEBUG_BUS1               (0x1000 + 0x018c)
#define USB3_QSERDES_COM_DEBUG_BUS2               (0x1000 + 0x0190)
#define USB3_QSERDES_COM_DEBUG_BUS3               (0x1000 + 0x0194)
#define USB3_QSERDES_COM_DEBUG_BUS_SEL            (0x1000 + 0x0198)
#define USB3_QSERDES_COM_CMN_MISC1                (0x1000 + 0x019c)
#define USB3_QSERDES_COM_CMN_MODE                 (0x1000 + 0x01a0)
#define USB3_QSERDES_COM_CMN_MODE_CONTD           (0x1000 + 0x01a4)
#define USB3_QSERDES_COM_VCO_DC_LEVEL_CTRL        (0x1000 + 0x01a8)
#define USB3_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (0x1000 + 0x01ac)
#define USB3_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (0x1000 + 0x01b0)
#define USB3_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 (0x1000 + 0x01b4)
#define USB3_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 (0x1000 + 0x01b8)
#define USB3_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL     (0x1000 + 0x01bc)
#define USB3_QSERDES_COM_RESERVED_1               (0x1000 + 0x01c0)
#define USB3_QSERDES_COM_MODE_OPERATION_STATUS    (0x1000 + 0x01c4)

/* Module: USB3_DP_PHY_USB3_QSERDES_TXA_USB3_QSERDES_TXA_USB3_DP_QMP_TX */
#define USB3_QSERDES_TXA_BIST_MODE_LANENO         (0x1200 + 0x0000)
#define USB3_QSERDES_TXA_BIST_INVERT              (0x1200 + 0x0004)
#define USB3_QSERDES_TXA_CLKBUF_ENABLE            (0x1200 + 0x0008)
#define USB3_QSERDES_TXA_TX_EMP_POST1_LVL         (0x1200 + 0x000c)
#define USB3_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP    (0x1200 + 0x0010)
#define USB3_QSERDES_TXA_TX_DRV_LVL               (0x1200 + 0x0014)
#define USB3_QSERDES_TXA_TX_DRV_LVL_OFFSET        (0x1200 + 0x0018)
#define USB3_QSERDES_TXA_RESET_TSYNC_EN           (0x1200 + 0x001c)
#define USB3_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN   (0x1200 + 0x0020)
#define USB3_QSERDES_TXA_TX_BAND                  (0x1200 + 0x0024)
#define USB3_QSERDES_TXA_SLEW_CNTL                (0x1200 + 0x0028)
#define USB3_QSERDES_TXA_INTERFACE_SELECT         (0x1200 + 0x002c)
#define USB3_QSERDES_TXA_LPB_EN                   (0x1200 + 0x0030)
#define USB3_QSERDES_TXA_RES_CODE_LANE_TX         (0x1200 + 0x0034)
#define USB3_QSERDES_TXA_RES_CODE_LANE_RX         (0x1200 + 0x0038)
#define USB3_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX  (0x1200 + 0x003c)
#define USB3_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX  (0x1200 + 0x0040)
#define USB3_QSERDES_TXA_PERL_LENGTH1             (0x1200 + 0x0044)
#define USB3_QSERDES_TXA_PERL_LENGTH2             (0x1200 + 0x0048)
#define USB3_QSERDES_TXA_SERDES_BYP_EN_OUT        (0x1200 + 0x004c)
#define USB3_QSERDES_TXA_DEBUG_BUS_SEL            (0x1200 + 0x0050)
#define USB3_QSERDES_TXA_TRANSCEIVER_BIAS_EN      (0x1200 + 0x0054)
#define USB3_QSERDES_TXA_HIGHZ_DRVR_EN            (0x1200 + 0x0058)
#define USB3_QSERDES_TXA_TX_POL_INV               (0x1200 + 0x005c)
#define USB3_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN (0x1200 + 0x0060)
#define USB3_QSERDES_TXA_BIST_PATTERN1            (0x1200 + 0x0064)
#define USB3_QSERDES_TXA_BIST_PATTERN2            (0x1200 + 0x0068)
#define USB3_QSERDES_TXA_BIST_PATTERN3            (0x1200 + 0x006c)
#define USB3_QSERDES_TXA_BIST_PATTERN4            (0x1200 + 0x0070)
#define USB3_QSERDES_TXA_BIST_PATTERN5            (0x1200 + 0x0074)
#define USB3_QSERDES_TXA_BIST_PATTERN6            (0x1200 + 0x0078)
#define USB3_QSERDES_TXA_BIST_PATTERN7            (0x1200 + 0x007c)
#define USB3_QSERDES_TXA_BIST_PATTERN8            (0x1200 + 0x0080)
#define USB3_QSERDES_TXA_LANE_MODE_1              (0x1200 + 0x0084)
#define USB3_QSERDES_TXA_LANE_MODE_2              (0x1200 + 0x0088)
#define USB3_QSERDES_TXA_LANE_MODE_3              (0x1200 + 0x008c)
#define USB3_QSERDES_TXA_LANE_MODE_4              (0x1200 + 0x0090)
#define USB3_QSERDES_TXA_LANE_MODE_5              (0x1200 + 0x0094)
#define USB3_QSERDES_TXA_ATB_SEL1                 (0x1200 + 0x0098)
#define USB3_QSERDES_TXA_ATB_SEL2                 (0x1200 + 0x009c)
#define USB3_QSERDES_TXA_RCV_DETECT_LVL           (0x1200 + 0x00a0)
#define USB3_QSERDES_TXA_RCV_DETECT_LVL_2         (0x1200 + 0x00a4)
#define USB3_QSERDES_TXA_PRBS_SEED1               (0x1200 + 0x00a8)
#define USB3_QSERDES_TXA_PRBS_SEED2               (0x1200 + 0x00ac)
#define USB3_QSERDES_TXA_PRBS_SEED3               (0x1200 + 0x00b0)
#define USB3_QSERDES_TXA_PRBS_SEED4               (0x1200 + 0x00b4)
#define USB3_QSERDES_TXA_RESET_GEN                (0x1200 + 0x00b8)
#define USB3_QSERDES_TXA_RESET_GEN_MUXES          (0x1200 + 0x00bc)
#define USB3_QSERDES_TXA_TRAN_DRVR_EMP_EN         (0x1200 + 0x00c0)
#define USB3_QSERDES_TXA_TX_INTERFACE_MODE        (0x1200 + 0x00c4)
#define USB3_QSERDES_TXA_VMODE_CTRL1              (0x1200 + 0x00c8)
#define USB3_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1     (0x1200 + 0x00cc)
#define USB3_QSERDES_TXA_BIST_STATUS              (0x1200 + 0x00d0)
#define USB3_QSERDES_TXA_BIST_ERROR_COUNT1        (0x1200 + 0x00d4)
#define USB3_QSERDES_TXA_BIST_ERROR_COUNT2        (0x1200 + 0x00d8)
#define USB3_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1   (0x1200 + 0x00dc)
#define USB3_QSERDES_TXA_LANE_DIG_CONFIG          (0x1200 + 0x00e0)
#define USB3_QSERDES_TXA_PI_QEC_CTRL              (0x1200 + 0x00e4)
#define USB3_QSERDES_TXA_PRE_EMPH                 (0x1200 + 0x00e8)
#define USB3_QSERDES_TXA_SW_RESET                 (0x1200 + 0x00ec)
#define USB3_QSERDES_TXA_DCC_OFFSET               (0x1200 + 0x00f0)
#define USB3_QSERDES_TXA_DCC_CMUX_POSTCAL_OFFSET  (0x1200 + 0x00f4)
#define USB3_QSERDES_TXA_DCC_CMUX_CAL_CTRL1       (0x1200 + 0x00f8)
#define USB3_QSERDES_TXA_DCC_CMUX_CAL_CTRL2       (0x1200 + 0x00fc)
#define USB3_QSERDES_TXA_DIG_BKUP_CTRL            (0x1200 + 0x0100)
#define USB3_QSERDES_TXA_DEBUG_BUS0               (0x1200 + 0x0104)
#define USB3_QSERDES_TXA_DEBUG_BUS1               (0x1200 + 0x0108)
#define USB3_QSERDES_TXA_DEBUG_BUS2               (0x1200 + 0x010c)
#define USB3_QSERDES_TXA_DEBUG_BUS3               (0x1200 + 0x0110)
#define USB3_QSERDES_TXA_READ_EQCODE              (0x1200 + 0x0114)
#define USB3_QSERDES_TXA_READ_OFFSETCODE          (0x1200 + 0x0118)
#define USB3_QSERDES_TXA_IA_ERROR_COUNTER_LOW     (0x1200 + 0x011c)
#define USB3_QSERDES_TXA_IA_ERROR_COUNTER_HIGH    (0x1200 + 0x0120)
#define USB3_QSERDES_TXA_VGA_READ_CODE            (0x1200 + 0x0124)
#define USB3_QSERDES_TXA_VTH_READ_CODE            (0x1200 + 0x0128)
#define USB3_QSERDES_TXA_DFE_TAP1_READ_CODE       (0x1200 + 0x012c)
#define USB3_QSERDES_TXA_DFE_TAP2_READ_CODE       (0x1200 + 0x0130)
#define USB3_QSERDES_TXA_IDAC_STATUS_I            (0x1200 + 0x0134)
#define USB3_QSERDES_TXA_IDAC_STATUS_IBAR         (0x1200 + 0x0138)
#define USB3_QSERDES_TXA_IDAC_STATUS_Q            (0x1200 + 0x013c)
#define USB3_QSERDES_TXA_IDAC_STATUS_QBAR         (0x1200 + 0x0140)
#define USB3_QSERDES_TXA_IDAC_STATUS_A            (0x1200 + 0x0144)
#define USB3_QSERDES_TXA_IDAC_STATUS_ABAR         (0x1200 + 0x0148)
#define USB3_QSERDES_TXA_IDAC_STATUS_SM_ON        (0x1200 + 0x014c)
#define USB3_QSERDES_TXA_IDAC_STATUS_CAL_DONE     (0x1200 + 0x0150)
#define USB3_QSERDES_TXA_IDAC_STATUS_SIGNERROR    (0x1200 + 0x0154)
#define USB3_QSERDES_TXA_DCC_CAL_STATUS           (0x1200 + 0x0158)
#define USB3_QSERDES_TXA_DCC_READ_CODE_STATUS     (0x1200 + 0x015c)

/* Module: USB3_DP_PHY_USB3_QSERDES_RXA_USB3_QSERDES_RXA_USB3_DP_QMP_RX */
#define USB3_QSERDES_RXA_UCDR_FO_GAIN_HALF        (0x1400 + 0x0000)
#define USB3_QSERDES_RXA_UCDR_FO_GAIN_QUARTER     (0x1400 + 0x0004)
#define USB3_QSERDES_RXA_UCDR_FO_GAIN             (0x1400 + 0x0008)
#define USB3_QSERDES_RXA_UCDR_SO_GAIN_HALF        (0x1400 + 0x000c)
#define USB3_QSERDES_RXA_UCDR_SO_GAIN_QUARTER     (0x1400 + 0x0010)
#define USB3_QSERDES_RXA_UCDR_SO_GAIN             (0x1400 + 0x0014)
#define USB3_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF    (0x1400 + 0x0018)
#define USB3_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER (0x1400 + 0x001c)
#define USB3_QSERDES_RXA_UCDR_SVS_FO_GAIN         (0x1400 + 0x0020)
#define USB3_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF    (0x1400 + 0x0024)
#define USB3_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER (0x1400 + 0x0028)
#define USB3_QSERDES_RXA_UCDR_SVS_SO_GAIN         (0x1400 + 0x002c)
#define USB3_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN    (0x1400 + 0x0030)
#define USB3_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE (0x1400 + 0x0034)
#define USB3_QSERDES_RXA_UCDR_FO_TO_SO_DELAY      (0x1400 + 0x0038)
#define USB3_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW  (0x1400 + 0x003c)
#define USB3_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH (0x1400 + 0x0040)
#define USB3_QSERDES_RXA_UCDR_PI_CONTROLS         (0x1400 + 0x0044)
#define USB3_QSERDES_RXA_UCDR_PI_CTRL2            (0x1400 + 0x0048)
#define USB3_QSERDES_RXA_UCDR_SB2_THRESH1         (0x1400 + 0x004c)
#define USB3_QSERDES_RXA_UCDR_SB2_THRESH2         (0x1400 + 0x0050)
#define USB3_QSERDES_RXA_UCDR_SB2_GAIN1           (0x1400 + 0x0054)
#define USB3_QSERDES_RXA_UCDR_SB2_GAIN2           (0x1400 + 0x0058)
#define USB3_QSERDES_RXA_AUX_CONTROL              (0x1400 + 0x005c)
#define USB3_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE   (0x1400 + 0x0060)
#define USB3_QSERDES_RXA_RCLK_AUXDATA_SEL         (0x1400 + 0x0064)
#define USB3_QSERDES_RXA_AC_JTAG_ENABLE           (0x1400 + 0x0068)
#define USB3_QSERDES_RXA_AC_JTAG_INITP            (0x1400 + 0x006c)
#define USB3_QSERDES_RXA_AC_JTAG_INITN            (0x1400 + 0x0070)
#define USB3_QSERDES_RXA_AC_JTAG_LVL              (0x1400 + 0x0074)
#define USB3_QSERDES_RXA_AC_JTAG_MODE             (0x1400 + 0x0078)
#define USB3_QSERDES_RXA_AC_JTAG_RESET            (0x1400 + 0x007c)
#define USB3_QSERDES_RXA_RX_TERM_BW               (0x1400 + 0x0080)
#define USB3_QSERDES_RXA_RX_RCVR_IQ_EN            (0x1400 + 0x0084)
#define USB3_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS     (0x1400 + 0x0088)
#define USB3_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS  (0x1400 + 0x008c)
#define USB3_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS     (0x1400 + 0x0090)
#define USB3_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS  (0x1400 + 0x0094)
#define USB3_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS     (0x1400 + 0x0098)
#define USB3_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS  (0x1400 + 0x009c)
#define USB3_QSERDES_RXA_RX_IDAC_EN               (0x1400 + 0x00a0)
#define USB3_QSERDES_RXA_RX_IDAC_ENABLES          (0x1400 + 0x00a4)
#define USB3_QSERDES_RXA_RX_IDAC_SIGN             (0x1400 + 0x00a8)
#define USB3_QSERDES_RXA_RX_HIGHZ_HIGHRATE        (0x1400 + 0x00ac)
#define USB3_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x1400 + 0x00b0)
#define USB3_QSERDES_RXA_DFE_1                    (0x1400 + 0x00b4)
#define USB3_QSERDES_RXA_DFE_2                    (0x1400 + 0x00b8)
#define USB3_QSERDES_RXA_DFE_3                    (0x1400 + 0x00bc)
#define USB3_QSERDES_RXA_DFE_4                    (0x1400 + 0x00c0)
#define USB3_QSERDES_RXA_TX_ADAPT_PRE_THRESH1     (0x1400 + 0x00c4)
#define USB3_QSERDES_RXA_TX_ADAPT_PRE_THRESH2     (0x1400 + 0x00c8)
#define USB3_QSERDES_RXA_TX_ADAPT_POST_THRESH     (0x1400 + 0x00cc)
#define USB3_QSERDES_RXA_TX_ADAPT_MAIN_THRESH     (0x1400 + 0x00d0)
#define USB3_QSERDES_RXA_VGA_CAL_CNTRL1           (0x1400 + 0x00d4)
#define USB3_QSERDES_RXA_VGA_CAL_CNTRL2           (0x1400 + 0x00d8)
#define USB3_QSERDES_RXA_GM_CAL                   (0x1400 + 0x00dc)
#define USB3_QSERDES_RXA_RX_VGA_GAIN2_LSB         (0x1400 + 0x00e0)
#define USB3_QSERDES_RXA_RX_VGA_GAIN2_MSB         (0x1400 + 0x00e4)
#define USB3_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1    (0x1400 + 0x00e8)
#define USB3_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2    (0x1400 + 0x00ec)
#define USB3_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3    (0x1400 + 0x00f0)
#define USB3_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4    (0x1400 + 0x00f4)
#define USB3_QSERDES_RXA_RX_IDAC_TSETTLE_LOW      (0x1400 + 0x00f8)
#define USB3_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH     (0x1400 + 0x00fc)
#define USB3_QSERDES_RXA_RX_IDAC_MEASURE_TIME     (0x1400 + 0x0100)
#define USB3_QSERDES_RXA_RX_IDAC_ACCUMULATOR      (0x1400 + 0x0104)
#define USB3_QSERDES_RXA_RX_EQ_OFFSET_LSB         (0x1400 + 0x0108)
#define USB3_QSERDES_RXA_RX_EQ_OFFSET_MSB         (0x1400 + 0x010c)
#define USB3_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x1400 + 0x0110)
#define USB3_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 (0x1400 + 0x0114)
#define USB3_QSERDES_RXA_SIGDET_ENABLES           (0x1400 + 0x0118)
#define USB3_QSERDES_RXA_SIGDET_CNTRL             (0x1400 + 0x011c)
#define USB3_QSERDES_RXA_SIGDET_LVL               (0x1400 + 0x0120)
#define USB3_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL    (0x1400 + 0x0124)
#define USB3_QSERDES_RXA_RX_BAND                  (0x1400 + 0x0128)
#define USB3_QSERDES_RXA_CDR_FREEZE_UP_DN         (0x1400 + 0x012c)
#define USB3_QSERDES_RXA_CDR_RESET_OVERRIDE       (0x1400 + 0x0130)
#define USB3_QSERDES_RXA_RX_INTERFACE_MODE        (0x1400 + 0x0134)
#define USB3_QSERDES_RXA_JITTER_GEN_MODE          (0x1400 + 0x0138)
#define USB3_QSERDES_RXA_SJ_AMP1                  (0x1400 + 0x013c)
#define USB3_QSERDES_RXA_SJ_AMP2                  (0x1400 + 0x0140)
#define USB3_QSERDES_RXA_SJ_PER1                  (0x1400 + 0x0144)
#define USB3_QSERDES_RXA_SJ_PER2                  (0x1400 + 0x0148)
#define USB3_QSERDES_RXA_PPM_OFFSET1              (0x1400 + 0x014c)
#define USB3_QSERDES_RXA_PPM_OFFSET2              (0x1400 + 0x0150)
#define USB3_QSERDES_RXA_SIGN_PPM_PERIOD1         (0x1400 + 0x0154)
#define USB3_QSERDES_RXA_SIGN_PPM_PERIOD2         (0x1400 + 0x0158)
#define USB3_QSERDES_RXA_RX_MODE_00_LOW           (0x1400 + 0x015c)
#define USB3_QSERDES_RXA_RX_MODE_00_HIGH          (0x1400 + 0x0160)
#define USB3_QSERDES_RXA_RX_MODE_00_HIGH2         (0x1400 + 0x0164)
#define USB3_QSERDES_RXA_RX_MODE_00_HIGH3         (0x1400 + 0x0168)
#define USB3_QSERDES_RXA_RX_MODE_00_HIGH4         (0x1400 + 0x016c)
#define USB3_QSERDES_RXA_RX_MODE_01_LOW           (0x1400 + 0x0170)
#define USB3_QSERDES_RXA_RX_MODE_01_HIGH          (0x1400 + 0x0174)
#define USB3_QSERDES_RXA_RX_MODE_01_HIGH2         (0x1400 + 0x0178)
#define USB3_QSERDES_RXA_RX_MODE_01_HIGH3         (0x1400 + 0x017c)
#define USB3_QSERDES_RXA_RX_MODE_01_HIGH4         (0x1400 + 0x0180)
#define USB3_QSERDES_RXA_RX_MODE_10_LOW           (0x1400 + 0x0184)
#define USB3_QSERDES_RXA_RX_MODE_10_HIGH          (0x1400 + 0x0188)
#define USB3_QSERDES_RXA_RX_MODE_10_HIGH2         (0x1400 + 0x018c)
#define USB3_QSERDES_RXA_RX_MODE_10_HIGH3         (0x1400 + 0x0190)
#define USB3_QSERDES_RXA_RX_MODE_10_HIGH4         (0x1400 + 0x0194)
#define USB3_QSERDES_RXA_PHPRE_CTRL               (0x1400 + 0x0198)
#define USB3_QSERDES_RXA_PHPRE_INITVAL            (0x1400 + 0x019c)
#define USB3_QSERDES_RXA_DFE_EN_TIMER             (0x1400 + 0x01a0)
#define USB3_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET (0x1400 + 0x01a4)
#define USB3_QSERDES_RXA_DCC_CTRL1                (0x1400 + 0x01a8)
#define USB3_QSERDES_RXA_DCC_CTRL2                (0x1400 + 0x01ac)
#define USB3_QSERDES_RXA_VTH_CODE                 (0x1400 + 0x01b0)
#define USB3_QSERDES_RXA_VTH_MIN_THRESH           (0x1400 + 0x01b4)
#define USB3_QSERDES_RXA_VTH_MAX_THRESH           (0x1400 + 0x01b8)
#define USB3_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1     (0x1400 + 0x01bc)
#define USB3_QSERDES_RXA_PI_CTRL1                 (0x1400 + 0x01c0)
#define USB3_QSERDES_RXA_PI_CTRL2                 (0x1400 + 0x01c4)
#define USB3_QSERDES_RXA_PI_QUAD                  (0x1400 + 0x01c8)
#define USB3_QSERDES_RXA_IDATA1                   (0x1400 + 0x01cc)
#define USB3_QSERDES_RXA_IDATA2                   (0x1400 + 0x01d0)
#define USB3_QSERDES_RXA_AUX_DATA1                (0x1400 + 0x01d4)
#define USB3_QSERDES_RXA_AUX_DATA2                (0x1400 + 0x01d8)
#define USB3_QSERDES_RXA_AC_JTAG_OUTP             (0x1400 + 0x01dc)
#define USB3_QSERDES_RXA_AC_JTAG_OUTN             (0x1400 + 0x01e0)
#define USB3_QSERDES_RXA_RX_SIGDET                (0x1400 + 0x01e4)
#define USB3_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1   (0x1400 + 0x01e8)

/* Module: USB3_DP_PHY_USB3_QSERDES_TXB_USB3_QSERDES_TXB_USB3_DP_QMP_TX */
#define USB3_QSERDES_TXB_BIST_MODE_LANENO         (0x1600 + 0x0000)
#define USB3_QSERDES_TXB_BIST_INVERT              (0x1600 + 0x0004)
#define USB3_QSERDES_TXB_CLKBUF_ENABLE            (0x1600 + 0x0008)
#define USB3_QSERDES_TXB_TX_EMP_POST1_LVL         (0x1600 + 0x000c)
#define USB3_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP    (0x1600 + 0x0010)
#define USB3_QSERDES_TXB_TX_DRV_LVL               (0x1600 + 0x0014)
#define USB3_QSERDES_TXB_TX_DRV_LVL_OFFSET        (0x1600 + 0x0018)
#define USB3_QSERDES_TXB_RESET_TSYNC_EN           (0x1600 + 0x001c)
#define USB3_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN   (0x1600 + 0x0020)
#define USB3_QSERDES_TXB_TX_BAND                  (0x1600 + 0x0024)
#define USB3_QSERDES_TXB_SLEW_CNTL                (0x1600 + 0x0028)
#define USB3_QSERDES_TXB_INTERFACE_SELECT         (0x1600 + 0x002c)
#define USB3_QSERDES_TXB_LPB_EN                   (0x1600 + 0x0030)
#define USB3_QSERDES_TXB_RES_CODE_LANE_TX         (0x1600 + 0x0034)
#define USB3_QSERDES_TXB_RES_CODE_LANE_RX         (0x1600 + 0x0038)
#define USB3_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX  (0x1600 + 0x003c)
#define USB3_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX  (0x1600 + 0x0040)
#define USB3_QSERDES_TXB_PERL_LENGTH1             (0x1600 + 0x0044)
#define USB3_QSERDES_TXB_PERL_LENGTH2             (0x1600 + 0x0048)
#define USB3_QSERDES_TXB_SERDES_BYP_EN_OUT        (0x1600 + 0x004c)
#define USB3_QSERDES_TXB_DEBUG_BUS_SEL            (0x1600 + 0x0050)
#define USB3_QSERDES_TXB_TRANSCEIVER_BIAS_EN      (0x1600 + 0x0054)
#define USB3_QSERDES_TXB_HIGHZ_DRVR_EN            (0x1600 + 0x0058)
#define USB3_QSERDES_TXB_TX_POL_INV               (0x1600 + 0x005c)
#define USB3_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN (0x1600 + 0x0060)
#define USB3_QSERDES_TXB_BIST_PATTERN1            (0x1600 + 0x0064)
#define USB3_QSERDES_TXB_BIST_PATTERN2            (0x1600 + 0x0068)
#define USB3_QSERDES_TXB_BIST_PATTERN3            (0x1600 + 0x006c)
#define USB3_QSERDES_TXB_BIST_PATTERN4            (0x1600 + 0x0070)
#define USB3_QSERDES_TXB_BIST_PATTERN5            (0x1600 + 0x0074)
#define USB3_QSERDES_TXB_BIST_PATTERN6            (0x1600 + 0x0078)
#define USB3_QSERDES_TXB_BIST_PATTERN7            (0x1600 + 0x007c)
#define USB3_QSERDES_TXB_BIST_PATTERN8            (0x1600 + 0x0080)
#define USB3_QSERDES_TXB_LANE_MODE_1              (0x1600 + 0x0084)
#define USB3_QSERDES_TXB_LANE_MODE_2              (0x1600 + 0x0088)
#define USB3_QSERDES_TXB_LANE_MODE_3              (0x1600 + 0x008c)
#define USB3_QSERDES_TXB_LANE_MODE_4              (0x1600 + 0x0090)
#define USB3_QSERDES_TXB_LANE_MODE_5              (0x1600 + 0x0094)
#define USB3_QSERDES_TXB_ATB_SEL1                 (0x1600 + 0x0098)
#define USB3_QSERDES_TXB_ATB_SEL2                 (0x1600 + 0x009c)
#define USB3_QSERDES_TXB_RCV_DETECT_LVL           (0x1600 + 0x00a0)
#define USB3_QSERDES_TXB_RCV_DETECT_LVL_2         (0x1600 + 0x00a4)
#define USB3_QSERDES_TXB_PRBS_SEED1               (0x1600 + 0x00a8)
#define USB3_QSERDES_TXB_PRBS_SEED2               (0x1600 + 0x00ac)
#define USB3_QSERDES_TXB_PRBS_SEED3               (0x1600 + 0x00b0)
#define USB3_QSERDES_TXB_PRBS_SEED4               (0x1600 + 0x00b4)
#define USB3_QSERDES_TXB_RESET_GEN                (0x1600 + 0x00b8)
#define USB3_QSERDES_TXB_RESET_GEN_MUXES          (0x1600 + 0x00bc)
#define USB3_QSERDES_TXB_TRAN_DRVR_EMP_EN         (0x1600 + 0x00c0)
#define USB3_QSERDES_TXB_TX_INTERFACE_MODE        (0x1600 + 0x00c4)
#define USB3_QSERDES_TXB_VMODE_CTRL1              (0x1600 + 0x00c8)
#define USB3_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1     (0x1600 + 0x00cc)
#define USB3_QSERDES_TXB_BIST_STATUS              (0x1600 + 0x00d0)
#define USB3_QSERDES_TXB_BIST_ERROR_COUNT1        (0x1600 + 0x00d4)
#define USB3_QSERDES_TXB_BIST_ERROR_COUNT2        (0x1600 + 0x00d8)
#define USB3_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1   (0x1600 + 0x00dc)
#define USB3_QSERDES_TXB_LANE_DIG_CONFIG          (0x1600 + 0x00e0)
#define USB3_QSERDES_TXB_PI_QEC_CTRL              (0x1600 + 0x00e4)
#define USB3_QSERDES_TXB_PRE_EMPH                 (0x1600 + 0x00e8)
#define USB3_QSERDES_TXB_SW_RESET                 (0x1600 + 0x00ec)
#define USB3_QSERDES_TXB_DCC_OFFSET               (0x1600 + 0x00f0)
#define USB3_QSERDES_TXB_DCC_CMUX_POSTCAL_OFFSET  (0x1600 + 0x00f4)
#define USB3_QSERDES_TXB_DCC_CMUX_CAL_CTRL1       (0x1600 + 0x00f8)
#define USB3_QSERDES_TXB_DCC_CMUX_CAL_CTRL2       (0x1600 + 0x00fc)
#define USB3_QSERDES_TXB_DIG_BKUP_CTRL            (0x1600 + 0x0100)
#define USB3_QSERDES_TXB_DEBUG_BUS0               (0x1600 + 0x0104)
#define USB3_QSERDES_TXB_DEBUG_BUS1               (0x1600 + 0x0108)
#define USB3_QSERDES_TXB_DEBUG_BUS2               (0x1600 + 0x010c)
#define USB3_QSERDES_TXB_DEBUG_BUS3               (0x1600 + 0x0110)
#define USB3_QSERDES_TXB_READ_EQCODE              (0x1600 + 0x0114)
#define USB3_QSERDES_TXB_READ_OFFSETCODE          (0x1600 + 0x0118)
#define USB3_QSERDES_TXB_IA_ERROR_COUNTER_LOW     (0x1600 + 0x011c)
#define USB3_QSERDES_TXB_IA_ERROR_COUNTER_HIGH    (0x1600 + 0x0120)
#define USB3_QSERDES_TXB_VGA_READ_CODE            (0x1600 + 0x0124)
#define USB3_QSERDES_TXB_VTH_READ_CODE            (0x1600 + 0x0128)
#define USB3_QSERDES_TXB_DFE_TAP1_READ_CODE       (0x1600 + 0x012c)
#define USB3_QSERDES_TXB_DFE_TAP2_READ_CODE       (0x1600 + 0x0130)
#define USB3_QSERDES_TXB_IDAC_STATUS_I            (0x1600 + 0x0134)
#define USB3_QSERDES_TXB_IDAC_STATUS_IBAR         (0x1600 + 0x0138)
#define USB3_QSERDES_TXB_IDAC_STATUS_Q            (0x1600 + 0x013c)
#define USB3_QSERDES_TXB_IDAC_STATUS_QBAR         (0x1600 + 0x0140)
#define USB3_QSERDES_TXB_IDAC_STATUS_A            (0x1600 + 0x0144)
#define USB3_QSERDES_TXB_IDAC_STATUS_ABAR         (0x1600 + 0x0148)
#define USB3_QSERDES_TXB_IDAC_STATUS_SM_ON        (0x1600 + 0x014c)
#define USB3_QSERDES_TXB_IDAC_STATUS_CAL_DONE     (0x1600 + 0x0150)
#define USB3_QSERDES_TXB_IDAC_STATUS_SIGNERROR    (0x1600 + 0x0154)
#define USB3_QSERDES_TXB_DCC_CAL_STATUS           (0x1600 + 0x0158)
#define USB3_QSERDES_TXB_DCC_READ_CODE_STATUS     (0x1600 + 0x015c)

/* Module: USB3_DP_PHY_USB3_QSERDES_RXB_USB3_QSERDES_RXB_USB3_DP_QMP_RX */
#define USB3_QSERDES_RXB_UCDR_FO_GAIN_HALF        (0x1800 + 0x0000)
#define USB3_QSERDES_RXB_UCDR_FO_GAIN_QUARTER     (0x1800 + 0x0004)
#define USB3_QSERDES_RXB_UCDR_FO_GAIN             (0x1800 + 0x0008)
#define USB3_QSERDES_RXB_UCDR_SO_GAIN_HALF        (0x1800 + 0x000c)
#define USB3_QSERDES_RXB_UCDR_SO_GAIN_QUARTER     (0x1800 + 0x0010)
#define USB3_QSERDES_RXB_UCDR_SO_GAIN             (0x1800 + 0x0014)
#define USB3_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF    (0x1800 + 0x0018)
#define USB3_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER (0x1800 + 0x001c)
#define USB3_QSERDES_RXB_UCDR_SVS_FO_GAIN         (0x1800 + 0x0020)
#define USB3_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF    (0x1800 + 0x0024)
#define USB3_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER (0x1800 + 0x0028)
#define USB3_QSERDES_RXB_UCDR_SVS_SO_GAIN         (0x1800 + 0x002c)
#define USB3_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN    (0x1800 + 0x0030)
#define USB3_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE (0x1800 + 0x0034)
#define USB3_QSERDES_RXB_UCDR_FO_TO_SO_DELAY      (0x1800 + 0x0038)
#define USB3_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW  (0x1800 + 0x003c)
#define USB3_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH (0x1800 + 0x0040)
#define USB3_QSERDES_RXB_UCDR_PI_CONTROLS         (0x1800 + 0x0044)
#define USB3_QSERDES_RXB_UCDR_PI_CTRL2            (0x1800 + 0x0048)
#define USB3_QSERDES_RXB_UCDR_SB2_THRESH1         (0x1800 + 0x004c)
#define USB3_QSERDES_RXB_UCDR_SB2_THRESH2         (0x1800 + 0x0050)
#define USB3_QSERDES_RXB_UCDR_SB2_GAIN1           (0x1800 + 0x0054)
#define USB3_QSERDES_RXB_UCDR_SB2_GAIN2           (0x1800 + 0x0058)
#define USB3_QSERDES_RXB_AUX_CONTROL              (0x1800 + 0x005c)
#define USB3_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE   (0x1800 + 0x0060)
#define USB3_QSERDES_RXB_RCLK_AUXDATA_SEL         (0x1800 + 0x0064)
#define USB3_QSERDES_RXB_AC_JTAG_ENABLE           (0x1800 + 0x0068)
#define USB3_QSERDES_RXB_AC_JTAG_INITP            (0x1800 + 0x006c)
#define USB3_QSERDES_RXB_AC_JTAG_INITN            (0x1800 + 0x0070)
#define USB3_QSERDES_RXB_AC_JTAG_LVL              (0x1800 + 0x0074)
#define USB3_QSERDES_RXB_AC_JTAG_MODE             (0x1800 + 0x0078)
#define USB3_QSERDES_RXB_AC_JTAG_RESET            (0x1800 + 0x007c)
#define USB3_QSERDES_RXB_RX_TERM_BW               (0x1800 + 0x0080)
#define USB3_QSERDES_RXB_RX_RCVR_IQ_EN            (0x1800 + 0x0084)
#define USB3_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS     (0x1800 + 0x0088)
#define USB3_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS  (0x1800 + 0x008c)
#define USB3_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS     (0x1800 + 0x0090)
#define USB3_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS  (0x1800 + 0x0094)
#define USB3_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS     (0x1800 + 0x0098)
#define USB3_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS  (0x1800 + 0x009c)
#define USB3_QSERDES_RXB_RX_IDAC_EN               (0x1800 + 0x00a0)
#define USB3_QSERDES_RXB_RX_IDAC_ENABLES          (0x1800 + 0x00a4)
#define USB3_QSERDES_RXB_RX_IDAC_SIGN             (0x1800 + 0x00a8)
#define USB3_QSERDES_RXB_RX_HIGHZ_HIGHRATE        (0x1800 + 0x00ac)
#define USB3_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x1800 + 0x00b0)
#define USB3_QSERDES_RXB_DFE_1                    (0x1800 + 0x00b4)
#define USB3_QSERDES_RXB_DFE_2                    (0x1800 + 0x00b8)
#define USB3_QSERDES_RXB_DFE_3                    (0x1800 + 0x00bc)
#define USB3_QSERDES_RXB_DFE_4                    (0x1800 + 0x00c0)
#define USB3_QSERDES_RXB_TX_ADAPT_PRE_THRESH1     (0x1800 + 0x00c4)
#define USB3_QSERDES_RXB_TX_ADAPT_PRE_THRESH2     (0x1800 + 0x00c8)
#define USB3_QSERDES_RXB_TX_ADAPT_POST_THRESH     (0x1800 + 0x00cc)
#define USB3_QSERDES_RXB_TX_ADAPT_MAIN_THRESH     (0x1800 + 0x00d0)
#define USB3_QSERDES_RXB_VGA_CAL_CNTRL1           (0x1800 + 0x00d4)
#define USB3_QSERDES_RXB_VGA_CAL_CNTRL2           (0x1800 + 0x00d8)
#define USB3_QSERDES_RXB_GM_CAL                   (0x1800 + 0x00dc)
#define USB3_QSERDES_RXB_RX_VGA_GAIN2_LSB         (0x1800 + 0x00e0)
#define USB3_QSERDES_RXB_RX_VGA_GAIN2_MSB         (0x1800 + 0x00e4)
#define USB3_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1    (0x1800 + 0x00e8)
#define USB3_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2    (0x1800 + 0x00ec)
#define USB3_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3    (0x1800 + 0x00f0)
#define USB3_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4    (0x1800 + 0x00f4)
#define USB3_QSERDES_RXB_RX_IDAC_TSETTLE_LOW      (0x1800 + 0x00f8)
#define USB3_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH     (0x1800 + 0x00fc)
#define USB3_QSERDES_RXB_RX_IDAC_MEASURE_TIME     (0x1800 + 0x0100)
#define USB3_QSERDES_RXB_RX_IDAC_ACCUMULATOR      (0x1800 + 0x0104)
#define USB3_QSERDES_RXB_RX_EQ_OFFSET_LSB         (0x1800 + 0x0108)
#define USB3_QSERDES_RXB_RX_EQ_OFFSET_MSB         (0x1800 + 0x010c)
#define USB3_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x1800 + 0x0110)
#define USB3_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 (0x1800 + 0x0114)
#define USB3_QSERDES_RXB_SIGDET_ENABLES           (0x1800 + 0x0118)
#define USB3_QSERDES_RXB_SIGDET_CNTRL             (0x1800 + 0x011c)
#define USB3_QSERDES_RXB_SIGDET_LVL               (0x1800 + 0x0120)
#define USB3_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL    (0x1800 + 0x0124)
#define USB3_QSERDES_RXB_RX_BAND                  (0x1800 + 0x0128)
#define USB3_QSERDES_RXB_CDR_FREEZE_UP_DN         (0x1800 + 0x012c)
#define USB3_QSERDES_RXB_CDR_RESET_OVERRIDE       (0x1800 + 0x0130)
#define USB3_QSERDES_RXB_RX_INTERFACE_MODE        (0x1800 + 0x0134)
#define USB3_QSERDES_RXB_JITTER_GEN_MODE          (0x1800 + 0x0138)
#define USB3_QSERDES_RXB_SJ_AMP1                  (0x1800 + 0x013c)
#define USB3_QSERDES_RXB_SJ_AMP2                  (0x1800 + 0x0140)
#define USB3_QSERDES_RXB_SJ_PER1                  (0x1800 + 0x0144)
#define USB3_QSERDES_RXB_SJ_PER2                  (0x1800 + 0x0148)
#define USB3_QSERDES_RXB_PPM_OFFSET1              (0x1800 + 0x014c)
#define USB3_QSERDES_RXB_PPM_OFFSET2              (0x1800 + 0x0150)
#define USB3_QSERDES_RXB_SIGN_PPM_PERIOD1         (0x1800 + 0x0154)
#define USB3_QSERDES_RXB_SIGN_PPM_PERIOD2         (0x1800 + 0x0158)
#define USB3_QSERDES_RXB_RX_MODE_00_LOW           (0x1800 + 0x015c)
#define USB3_QSERDES_RXB_RX_MODE_00_HIGH          (0x1800 + 0x0160)
#define USB3_QSERDES_RXB_RX_MODE_00_HIGH2         (0x1800 + 0x0164)
#define USB3_QSERDES_RXB_RX_MODE_00_HIGH3         (0x1800 + 0x0168)
#define USB3_QSERDES_RXB_RX_MODE_00_HIGH4         (0x1800 + 0x016c)
#define USB3_QSERDES_RXB_RX_MODE_01_LOW           (0x1800 + 0x0170)
#define USB3_QSERDES_RXB_RX_MODE_01_HIGH          (0x1800 + 0x0174)
#define USB3_QSERDES_RXB_RX_MODE_01_HIGH2         (0x1800 + 0x0178)
#define USB3_QSERDES_RXB_RX_MODE_01_HIGH3         (0x1800 + 0x017c)
#define USB3_QSERDES_RXB_RX_MODE_01_HIGH4         (0x1800 + 0x0180)
#define USB3_QSERDES_RXB_RX_MODE_10_LOW           (0x1800 + 0x0184)
#define USB3_QSERDES_RXB_RX_MODE_10_HIGH          (0x1800 + 0x0188)
#define USB3_QSERDES_RXB_RX_MODE_10_HIGH2         (0x1800 + 0x018c)
#define USB3_QSERDES_RXB_RX_MODE_10_HIGH3         (0x1800 + 0x0190)
#define USB3_QSERDES_RXB_RX_MODE_10_HIGH4         (0x1800 + 0x0194)
#define USB3_QSERDES_RXB_PHPRE_CTRL               (0x1800 + 0x0198)
#define USB3_QSERDES_RXB_PHPRE_INITVAL            (0x1800 + 0x019c)
#define USB3_QSERDES_RXB_DFE_EN_TIMER             (0x1800 + 0x01a0)
#define USB3_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET (0x1800 + 0x01a4)
#define USB3_QSERDES_RXB_DCC_CTRL1                (0x1800 + 0x01a8)
#define USB3_QSERDES_RXB_DCC_CTRL2                (0x1800 + 0x01ac)
#define USB3_QSERDES_RXB_VTH_CODE                 (0x1800 + 0x01b0)
#define USB3_QSERDES_RXB_VTH_MIN_THRESH           (0x1800 + 0x01b4)
#define USB3_QSERDES_RXB_VTH_MAX_THRESH           (0x1800 + 0x01b8)
#define USB3_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1     (0x1800 + 0x01bc)
#define USB3_QSERDES_RXB_PI_CTRL1                 (0x1800 + 0x01c0)
#define USB3_QSERDES_RXB_PI_CTRL2                 (0x1800 + 0x01c4)
#define USB3_QSERDES_RXB_PI_QUAD                  (0x1800 + 0x01c8)
#define USB3_QSERDES_RXB_IDATA1                   (0x1800 + 0x01cc)
#define USB3_QSERDES_RXB_IDATA2                   (0x1800 + 0x01d0)
#define USB3_QSERDES_RXB_AUX_DATA1                (0x1800 + 0x01d4)
#define USB3_QSERDES_RXB_AUX_DATA2                (0x1800 + 0x01d8)
#define USB3_QSERDES_RXB_AC_JTAG_OUTP             (0x1800 + 0x01dc)
#define USB3_QSERDES_RXB_AC_JTAG_OUTN             (0x1800 + 0x01e0)
#define USB3_QSERDES_RXB_RX_SIGDET                (0x1800 + 0x01e4)
#define USB3_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1   (0x1800 + 0x01e8)

/* Module: USB3_DP_PHY_USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_PCS_MISC_TYPEC_CTRL                  (0x1a00 + 0x0000)
#define USB3_PCS_MISC_TYPEC_PWRDN_CTRL            (0x1a00 + 0x0004)
#define USB3_PCS_MISC_PCS_MISC_CONFIG1            (0x1a00 + 0x0008)
#define USB3_PCS_MISC_CLAMP_ENABLE                (0x1a00 + 0x000c)
#define USB3_PCS_MISC_TYPEC_STATUS                (0x1a00 + 0x0010)
#define USB3_PCS_MISC_PLACEHOLDER_STATUS          (0x1a00 + 0x0014)

/* Module: USB3_DP_PHY_USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */
#define USB3_PCS_LN_PCS_STATUS1                   (0x1b00 + 0x0000)
#define USB3_PCS_LN_PCS_STATUS2                   (0x1b00 + 0x0004)
#define USB3_PCS_LN_PCS_STATUS2_CLEAR             (0x1b00 + 0x0008)
#define USB3_PCS_LN_PCS_STATUS3                   (0x1b00 + 0x000c)
#define USB3_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS     (0x1b00 + 0x0010)
#define USB3_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS     (0x1b00 + 0x0014)
#define USB3_PCS_LN_BIST_CHK_STATUS               (0x1b00 + 0x0018)
#define USB3_PCS_LN_INSIG_SW_CTRL1                (0x1b00 + 0x001c)
#define USB3_PCS_LN_INSIG_MX_CTRL1                (0x1b00 + 0x0020)
#define USB3_PCS_LN_OUTSIG_SW_CTRL1               (0x1b00 + 0x0024)
#define USB3_PCS_LN_OUTSIG_MX_CTRL1               (0x1b00 + 0x0028)
#define USB3_PCS_LN_TEST_CONTROL1                 (0x1b00 + 0x002c)
#define USB3_PCS_LN_BIST_CTRL                     (0x1b00 + 0x0030)
#define USB3_PCS_LN_PRBS_SEED0                    (0x1b00 + 0x0034)
#define USB3_PCS_LN_PRBS_SEED1                    (0x1b00 + 0x0038)
#define USB3_PCS_LN_FIXED_PAT_CTRL                (0x1b00 + 0x003c)
#define USB3_PCS_LN_EQ_CONFIG                     (0x1b00 + 0x0040)
#define USB3_PCS_LN_TEST_CONTROL2                 (0x1b00 + 0x0044)
#define USB3_PCS_LN_TEST_CONTROL3                 (0x1b00 + 0x0048)

/* Module: USB3_DP_PHY_USB3_PCS_USB3_PCS_USB3_PCS */
#define USB3_PCS_SW_RESET                         (0x1c00 + 0x0000)
#define USB3_PCS_REVISION_ID0                     (0x1c00 + 0x0004)
#define USB3_PCS_REVISION_ID1                     (0x1c00 + 0x0008)
#define USB3_PCS_REVISION_ID2                     (0x1c00 + 0x000c)
#define USB3_PCS_REVISION_ID3                     (0x1c00 + 0x0010)
#define USB3_PCS_PCS_STATUS1                      (0x1c00 + 0x0014)
#define USB3_PCS_PCS_STATUS2                      (0x1c00 + 0x0018)
#define USB3_PCS_PCS_STATUS3                      (0x1c00 + 0x001c)
#define USB3_PCS_PCS_STATUS4                      (0x1c00 + 0x0020)
#define USB3_PCS_PCS_STATUS5                      (0x1c00 + 0x0024)
#define USB3_PCS_PCS_STATUS6                      (0x1c00 + 0x0028)
#define USB3_PCS_PCS_STATUS7                      (0x1c00 + 0x002c)
#define USB3_PCS_DEBUG_BUS_0_STATUS               (0x1c00 + 0x0030)
#define USB3_PCS_DEBUG_BUS_1_STATUS               (0x1c00 + 0x0034)
#define USB3_PCS_DEBUG_BUS_2_STATUS               (0x1c00 + 0x0038)
#define USB3_PCS_DEBUG_BUS_3_STATUS               (0x1c00 + 0x003c)
#define USB3_PCS_POWER_DOWN_CONTROL               (0x1c00 + 0x0040)
#define USB3_PCS_START_CONTROL                    (0x1c00 + 0x0044)
#define USB3_PCS_INSIG_SW_CTRL1                   (0x1c00 + 0x0048)
#define USB3_PCS_INSIG_SW_CTRL2                   (0x1c00 + 0x004c)
#define USB3_PCS_INSIG_SW_CTRL3                   (0x1c00 + 0x0050)
#define USB3_PCS_INSIG_SW_CTRL4                   (0x1c00 + 0x0054)
#define USB3_PCS_INSIG_SW_CTRL5                   (0x1c00 + 0x0058)
#define USB3_PCS_INSIG_SW_CTRL6                   (0x1c00 + 0x005c)
#define USB3_PCS_INSIG_SW_CTRL7                   (0x1c00 + 0x0060)
#define USB3_PCS_INSIG_SW_CTRL8                   (0x1c00 + 0x0064)
#define USB3_PCS_INSIG_MX_CTRL1                   (0x1c00 + 0x0068)
#define USB3_PCS_INSIG_MX_CTRL2                   (0x1c00 + 0x006c)
#define USB3_PCS_INSIG_MX_CTRL3                   (0x1c00 + 0x0070)
#define USB3_PCS_INSIG_MX_CTRL4                   (0x1c00 + 0x0074)
#define USB3_PCS_INSIG_MX_CTRL5                   (0x1c00 + 0x0078)
#define USB3_PCS_INSIG_MX_CTRL7                   (0x1c00 + 0x007c)
#define USB3_PCS_INSIG_MX_CTRL8                   (0x1c00 + 0x0080)
#define USB3_PCS_OUTSIG_SW_CTRL1                  (0x1c00 + 0x0084)
#define USB3_PCS_OUTSIG_MX_CTRL1                  (0x1c00 + 0x0088)
#define USB3_PCS_CLAMP_ENABLE                     (0x1c00 + 0x008c)
#define USB3_PCS_POWER_STATE_CONFIG1              (0x1c00 + 0x0090)
#define USB3_PCS_POWER_STATE_CONFIG2              (0x1c00 + 0x0094)
#define USB3_PCS_FLL_CNTRL1                       (0x1c00 + 0x0098)
#define USB3_PCS_FLL_CNTRL2                       (0x1c00 + 0x009c)
#define USB3_PCS_FLL_CNT_VAL_L                    (0x1c00 + 0x00a0)
#define USB3_PCS_FLL_CNT_VAL_H_TOL                (0x1c00 + 0x00a4)
#define USB3_PCS_FLL_MAN_CODE                     (0x1c00 + 0x00a8)
#define USB3_PCS_TEST_CONTROL1                    (0x1c00 + 0x00ac)
#define USB3_PCS_TEST_CONTROL2                    (0x1c00 + 0x00b0)
#define USB3_PCS_TEST_CONTROL3                    (0x1c00 + 0x00b4)
#define USB3_PCS_TEST_CONTROL4                    (0x1c00 + 0x00b8)
#define USB3_PCS_TEST_CONTROL5                    (0x1c00 + 0x00bc)
#define USB3_PCS_TEST_CONTROL6                    (0x1c00 + 0x00c0)
#define USB3_PCS_LOCK_DETECT_CONFIG1              (0x1c00 + 0x00c4)
#define USB3_PCS_LOCK_DETECT_CONFIG2              (0x1c00 + 0x00c8)
#define USB3_PCS_LOCK_DETECT_CONFIG3              (0x1c00 + 0x00cc)
#define USB3_PCS_LOCK_DETECT_CONFIG4              (0x1c00 + 0x00d0)
#define USB3_PCS_LOCK_DETECT_CONFIG5              (0x1c00 + 0x00d4)
#define USB3_PCS_LOCK_DETECT_CONFIG6              (0x1c00 + 0x00d8)
#define USB3_PCS_REFGEN_REQ_CONFIG1               (0x1c00 + 0x00dc)
#define USB3_PCS_REFGEN_REQ_CONFIG2               (0x1c00 + 0x00e0)
#define USB3_PCS_REFGEN_REQ_CONFIG3               (0x1c00 + 0x00e4)
#define USB3_PCS_BIST_CTRL                        (0x1c00 + 0x00e8)
#define USB3_PCS_PRBS_POLY0                       (0x1c00 + 0x00ec)
#define USB3_PCS_PRBS_POLY1                       (0x1c00 + 0x00f0)
#define USB3_PCS_FIXED_PAT0                       (0x1c00 + 0x00f4)
#define USB3_PCS_FIXED_PAT1                       (0x1c00 + 0x00f8)
#define USB3_PCS_FIXED_PAT2                       (0x1c00 + 0x00fc)
#define USB3_PCS_FIXED_PAT3                       (0x1c00 + 0x0100)
#define USB3_PCS_FIXED_PAT4                       (0x1c00 + 0x0104)
#define USB3_PCS_FIXED_PAT5                       (0x1c00 + 0x0108)
#define USB3_PCS_FIXED_PAT6                       (0x1c00 + 0x010c)
#define USB3_PCS_FIXED_PAT7                       (0x1c00 + 0x0110)
#define USB3_PCS_FIXED_PAT8                       (0x1c00 + 0x0114)
#define USB3_PCS_FIXED_PAT9                       (0x1c00 + 0x0118)
#define USB3_PCS_FIXED_PAT10                      (0x1c00 + 0x011c)
#define USB3_PCS_FIXED_PAT11                      (0x1c00 + 0x0120)
#define USB3_PCS_FIXED_PAT12                      (0x1c00 + 0x0124)
#define USB3_PCS_FIXED_PAT13                      (0x1c00 + 0x0128)
#define USB3_PCS_FIXED_PAT14                      (0x1c00 + 0x012c)
#define USB3_PCS_FIXED_PAT15                      (0x1c00 + 0x0130)
#define USB3_PCS_TXMGN_CONFIG                     (0x1c00 + 0x0134)
#define USB3_PCS_G12S1_TXMGN_V0                   (0x1c00 + 0x0138)
#define USB3_PCS_G12S1_TXMGN_V1                   (0x1c00 + 0x013c)
#define USB3_PCS_G12S1_TXMGN_V2                   (0x1c00 + 0x0140)
#define USB3_PCS_G12S1_TXMGN_V3                   (0x1c00 + 0x0144)
#define USB3_PCS_G12S1_TXMGN_V4                   (0x1c00 + 0x0148)
#define USB3_PCS_G12S1_TXMGN_V0_RS                (0x1c00 + 0x014c)
#define USB3_PCS_G12S1_TXMGN_V1_RS                (0x1c00 + 0x0150)
#define USB3_PCS_G12S1_TXMGN_V2_RS                (0x1c00 + 0x0154)
#define USB3_PCS_G12S1_TXMGN_V3_RS                (0x1c00 + 0x0158)
#define USB3_PCS_G12S1_TXMGN_V4_RS                (0x1c00 + 0x015c)
#define USB3_PCS_G3S2_TXMGN_MAIN                  (0x1c00 + 0x0160)
#define USB3_PCS_G3S2_TXMGN_MAIN_RS               (0x1c00 + 0x0164)
#define USB3_PCS_G12S1_TXDEEMPH_M6DB              (0x1c00 + 0x0168)
#define USB3_PCS_G12S1_TXDEEMPH_M3P5DB            (0x1c00 + 0x016c)
#define USB3_PCS_G3S2_PRE_GAIN                    (0x1c00 + 0x0170)
#define USB3_PCS_G3S2_POST_GAIN                   (0x1c00 + 0x0174)
#define USB3_PCS_G3S2_PRE_POST_OFFSET             (0x1c00 + 0x0178)
#define USB3_PCS_G3S2_PRE_GAIN_RS                 (0x1c00 + 0x017c)
#define USB3_PCS_G3S2_POST_GAIN_RS                (0x1c00 + 0x0180)
#define USB3_PCS_G3S2_PRE_POST_OFFSET_RS          (0x1c00 + 0x0184)
#define USB3_PCS_RX_SIGDET_LVL                    (0x1c00 + 0x0188)
#define USB3_PCS_RX_SIGDET_DTCT_CNTRL             (0x1c00 + 0x018c)
#define USB3_PCS_RCVR_DTCT_DLY_P1U2_L             (0x1c00 + 0x0190)
#define USB3_PCS_RCVR_DTCT_DLY_P1U2_H             (0x1c00 + 0x0194)
#define USB3_PCS_RATE_SLEW_CNTRL1                 (0x1c00 + 0x0198)
#define USB3_PCS_RATE_SLEW_CNTRL2                 (0x1c00 + 0x019c)
#define USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK      (0x1c00 + 0x01a0)
#define USB3_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L    (0x1c00 + 0x01a4)
#define USB3_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H    (0x1c00 + 0x01a8)
#define USB3_PCS_TSYNC_RSYNC_TIME                 (0x1c00 + 0x01ac)
#define USB3_PCS_CDR_RESET_TIME                   (0x1c00 + 0x01b0)
#define USB3_PCS_TSYNC_DLY_TIME                   (0x1c00 + 0x01b4)
#define USB3_PCS_ELECIDLE_DLY_SEL                 (0x1c00 + 0x01b8)
#define USB3_PCS_CMN_ACK_OUT_SEL                  (0x1c00 + 0x01bc)
#define USB3_PCS_ALIGN_DETECT_CONFIG1             (0x1c00 + 0x01c0)
#define USB3_PCS_ALIGN_DETECT_CONFIG2             (0x1c00 + 0x01c4)
#define USB3_PCS_ALIGN_DETECT_CONFIG3             (0x1c00 + 0x01c8)
#define USB3_PCS_ALIGN_DETECT_CONFIG4             (0x1c00 + 0x01cc)
#define USB3_PCS_PCS_TX_RX_CONFIG                 (0x1c00 + 0x01d0)
#define USB3_PCS_RX_IDLE_DTCT_CNTRL               (0x1c00 + 0x01d4)
#define USB3_PCS_RX_DCC_CAL_CONFIG                (0x1c00 + 0x01d8)
#define USB3_PCS_EQ_CONFIG1                       (0x1c00 + 0x01dc)
#define USB3_PCS_EQ_CONFIG2                       (0x1c00 + 0x01e0)
#define USB3_PCS_EQ_CONFIG3                       (0x1c00 + 0x01e4)
#define USB3_PCS_EQ_CONFIG4                       (0x1c00 + 0x01e8)
#define USB3_PCS_EQ_CONFIG5                       (0x1c00 + 0x01ec)

/* Module: USB3_DP_PHY_USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */
#define USB3_PCS_USB3_POWER_STATE_CONFIG1         (0x1f00 + 0x0000)
#define USB3_PCS_USB3_AUTONOMOUS_MODE_STATUS      (0x1f00 + 0x0004)
#define USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL        (0x1f00 + 0x0008)
#define USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL2       (0x1f00 + 0x000c)
#define USB3_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS (0x1f00 + 0x0010)
#define USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR       (0x1f00 + 0x0014)
#define USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL     (0x1f00 + 0x0018)
#define USB3_PCS_USB3_LFPS_TX_ECSTART             (0x1f00 + 0x001c)
#define USB3_PCS_USB3_LFPS_PER_TIMER_VAL          (0x1f00 + 0x0020)
#define USB3_PCS_USB3_LFPS_TX_END_CNT_U3_START    (0x1f00 + 0x0024)
#define USB3_PCS_USB3_LFPS_CONFIG1                (0x1f00 + 0x0028)
#define USB3_PCS_USB3_RXEQTRAINING_LOCK_TIME      (0x1f00 + 0x002c)
#define USB3_PCS_USB3_RXEQTRAINING_WAIT_TIME      (0x1f00 + 0x0030)
#define USB3_PCS_USB3_RXEQTRAINING_CTLE_TIME      (0x1f00 + 0x0034)
#define USB3_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2   (0x1f00 + 0x0038)
#define USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2    (0x1f00 + 0x003c)
#define USB3_PCS_USB3_RCVR_DTCT_DLY_U3_L          (0x1f00 + 0x0040)
#define USB3_PCS_USB3_RCVR_DTCT_DLY_U3_H          (0x1f00 + 0x0044)
#define USB3_PCS_USB3_ARCVR_DTCT_EN_PERIOD        (0x1f00 + 0x0048)
#define USB3_PCS_USB3_ARCVR_DTCT_CM_DLY           (0x1f00 + 0x004c)
#define USB3_PCS_USB3_TXONESZEROS_RUN_LENGTH      (0x1f00 + 0x0050)
#define USB3_PCS_USB3_ALFPS_DEGLITCH_VAL          (0x1f00 + 0x0054)
#define USB3_PCS_USB3_SIGDET_STARTUP_TIMER_VAL    (0x1f00 + 0x0058)
#define USB3_PCS_USB3_TEST_CONTROL                (0x1f00 + 0x005c)
#define USB3_PCS_USB3_RXTERMINATION_DLY_SEL       (0x1f00 + 0x0060)

/* Module: USB3_DP_PHY_DP_QSERDES_COM_DP_QSERDES_COM_USB3_DP_QMP_PLL */
#define DP_QSERDES_COM_ATB_SEL1                   (0x2000 + 0x0000)
#define DP_QSERDES_COM_ATB_SEL2                   (0x2000 + 0x0004)
#define DP_QSERDES_COM_FREQ_UPDATE                (0x2000 + 0x0008)
#define DP_QSERDES_COM_BG_TIMER                   (0x2000 + 0x000c)
#define DP_QSERDES_COM_SSC_EN_CENTER              (0x2000 + 0x0010)
#define DP_QSERDES_COM_SSC_ADJ_PER1               (0x2000 + 0x0014)
#define DP_QSERDES_COM_SSC_ADJ_PER2               (0x2000 + 0x0018)
#define DP_QSERDES_COM_SSC_PER1                   (0x2000 + 0x001c)
#define DP_QSERDES_COM_SSC_PER2                   (0x2000 + 0x0020)
#define DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0       (0x2000 + 0x0024)
#define DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0       (0x2000 + 0x0028)
#define DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0       (0x2000 + 0x002c)
#define DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1       (0x2000 + 0x0030)
#define DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1       (0x2000 + 0x0034)
#define DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1       (0x2000 + 0x0038)
#define DP_QSERDES_COM_POST_DIV                   (0x2000 + 0x003c)
#define DP_QSERDES_COM_POST_DIV_MUX               (0x2000 + 0x0040)
#define DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN        (0x2000 + 0x0044)
#define DP_QSERDES_COM_CLK_ENABLE1                (0x2000 + 0x0048)
#define DP_QSERDES_COM_SYS_CLK_CTRL               (0x2000 + 0x004c)
#define DP_QSERDES_COM_SYSCLK_BUF_ENABLE          (0x2000 + 0x0050)
#define DP_QSERDES_COM_PLL_EN                     (0x2000 + 0x0054)
#define DP_QSERDES_COM_PLL_IVCO                   (0x2000 + 0x0058)
#define DP_QSERDES_COM_CMN_IETRIM                 (0x2000 + 0x005c)
#define DP_QSERDES_COM_CMN_IPTRIM                 (0x2000 + 0x0060)
#define DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL       (0x2000 + 0x0064)
#define DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS     (0x2000 + 0x0068)
#define DP_QSERDES_COM_CLK_EP_DIV_MODE0           (0x2000 + 0x006c)
#define DP_QSERDES_COM_CLK_EP_DIV_MODE1           (0x2000 + 0x0070)
#define DP_QSERDES_COM_CP_CTRL_MODE0              (0x2000 + 0x0074)
#define DP_QSERDES_COM_CP_CTRL_MODE1              (0x2000 + 0x0078)
#define DP_QSERDES_COM_PLL_RCTRL_MODE0            (0x2000 + 0x007c)
#define DP_QSERDES_COM_PLL_RCTRL_MODE1            (0x2000 + 0x0080)
#define DP_QSERDES_COM_PLL_CCTRL_MODE0            (0x2000 + 0x0084)
#define DP_QSERDES_COM_PLL_CCTRL_MODE1            (0x2000 + 0x0088)
#define DP_QSERDES_COM_PLL_CNTRL                  (0x2000 + 0x008c)
#define DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM        (0x2000 + 0x0090)
#define DP_QSERDES_COM_SYSCLK_EN_SEL              (0x2000 + 0x0094)
#define DP_QSERDES_COM_CML_SYSCLK_SEL             (0x2000 + 0x0098)
#define DP_QSERDES_COM_RESETSM_CNTRL              (0x2000 + 0x009c)
#define DP_QSERDES_COM_RESETSM_CNTRL2             (0x2000 + 0x00a0)
#define DP_QSERDES_COM_LOCK_CMP_EN                (0x2000 + 0x00a4)
#define DP_QSERDES_COM_LOCK_CMP_CFG               (0x2000 + 0x00a8)
#define DP_QSERDES_COM_LOCK_CMP1_MODE0            (0x2000 + 0x00ac)
#define DP_QSERDES_COM_LOCK_CMP2_MODE0            (0x2000 + 0x00b0)
#define DP_QSERDES_COM_LOCK_CMP1_MODE1            (0x2000 + 0x00b4)
#define DP_QSERDES_COM_LOCK_CMP2_MODE1            (0x2000 + 0x00b8)
#define DP_QSERDES_COM_DEC_START_MODE0            (0x2000 + 0x00bc)
#define DP_QSERDES_COM_DEC_START_MSB_MODE0        (0x2000 + 0x00c0)
#define DP_QSERDES_COM_DEC_START_MODE1            (0x2000 + 0x00c4)
#define DP_QSERDES_COM_DEC_START_MSB_MODE1        (0x2000 + 0x00c8)
#define DP_QSERDES_COM_DIV_FRAC_START1_MODE0      (0x2000 + 0x00cc)
#define DP_QSERDES_COM_DIV_FRAC_START2_MODE0      (0x2000 + 0x00d0)
#define DP_QSERDES_COM_DIV_FRAC_START3_MODE0      (0x2000 + 0x00d4)
#define DP_QSERDES_COM_DIV_FRAC_START1_MODE1      (0x2000 + 0x00d8)
#define DP_QSERDES_COM_DIV_FRAC_START2_MODE1      (0x2000 + 0x00dc)
#define DP_QSERDES_COM_DIV_FRAC_START3_MODE1      (0x2000 + 0x00e0)
#define DP_QSERDES_COM_INTEGLOOP_INITVAL          (0x2000 + 0x00e4)
#define DP_QSERDES_COM_INTEGLOOP_EN               (0x2000 + 0x00e8)
#define DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0      (0x2000 + 0x00ec)
#define DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0      (0x2000 + 0x00f0)
#define DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1      (0x2000 + 0x00f4)
#define DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1      (0x2000 + 0x00f8)
#define DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0     (0x2000 + 0x00fc)
#define DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1     (0x2000 + 0x0100)
#define DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL        (0x2000 + 0x0104)
#define DP_QSERDES_COM_VCO_TUNE_CTRL              (0x2000 + 0x0108)
#define DP_QSERDES_COM_VCO_TUNE_MAP               (0x2000 + 0x010c)
#define DP_QSERDES_COM_VCO_TUNE1_MODE0            (0x2000 + 0x0110)
#define DP_QSERDES_COM_VCO_TUNE2_MODE0            (0x2000 + 0x0114)
#define DP_QSERDES_COM_VCO_TUNE1_MODE1            (0x2000 + 0x0118)
#define DP_QSERDES_COM_VCO_TUNE2_MODE1            (0x2000 + 0x011c)
#define DP_QSERDES_COM_VCO_TUNE_INITVAL1          (0x2000 + 0x0120)
#define DP_QSERDES_COM_VCO_TUNE_INITVAL2          (0x2000 + 0x0124)
#define DP_QSERDES_COM_VCO_TUNE_MINVAL1           (0x2000 + 0x0128)
#define DP_QSERDES_COM_VCO_TUNE_MINVAL2           (0x2000 + 0x012c)
#define DP_QSERDES_COM_VCO_TUNE_MAXVAL1           (0x2000 + 0x0130)
#define DP_QSERDES_COM_VCO_TUNE_MAXVAL2           (0x2000 + 0x0134)
#define DP_QSERDES_COM_VCO_TUNE_TIMER1            (0x2000 + 0x0138)
#define DP_QSERDES_COM_VCO_TUNE_TIMER2            (0x2000 + 0x013c)
#define DP_QSERDES_COM_CMN_STATUS                 (0x2000 + 0x0140)
#define DP_QSERDES_COM_RESET_SM_STATUS            (0x2000 + 0x0144)
#define DP_QSERDES_COM_RESTRIM_CODE_STATUS        (0x2000 + 0x0148)
#define DP_QSERDES_COM_PLLCAL_CODE1_STATUS        (0x2000 + 0x014c)
#define DP_QSERDES_COM_PLLCAL_CODE2_STATUS        (0x2000 + 0x0150)
#define DP_QSERDES_COM_CLK_SELECT                 (0x2000 + 0x0154)
#define DP_QSERDES_COM_HSCLK_SEL                  (0x2000 + 0x0158)
#define DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL        (0x2000 + 0x015c)
#define DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS   (0x2000 + 0x0160)
#define DP_QSERDES_COM_PLL_ANALOG                 (0x2000 + 0x0164)
#define DP_QSERDES_COM_CORECLK_DIV_MODE0          (0x2000 + 0x0168)
#define DP_QSERDES_COM_CORECLK_DIV_MODE1          (0x2000 + 0x016c)
#define DP_QSERDES_COM_SW_RESET                   (0x2000 + 0x0170)
#define DP_QSERDES_COM_CORE_CLK_EN                (0x2000 + 0x0174)
#define DP_QSERDES_COM_C_READY_STATUS             (0x2000 + 0x0178)
#define DP_QSERDES_COM_CMN_CONFIG                 (0x2000 + 0x017c)
#define DP_QSERDES_COM_CMN_RATE_OVERRIDE          (0x2000 + 0x0180)
#define DP_QSERDES_COM_SVS_MODE_CLK_SEL           (0x2000 + 0x0184)
#define DP_QSERDES_COM_DEBUG_BUS0                 (0x2000 + 0x0188)
#define DP_QSERDES_COM_DEBUG_BUS1                 (0x2000 + 0x018c)
#define DP_QSERDES_COM_DEBUG_BUS2                 (0x2000 + 0x0190)
#define DP_QSERDES_COM_DEBUG_BUS3                 (0x2000 + 0x0194)
#define DP_QSERDES_COM_DEBUG_BUS_SEL              (0x2000 + 0x0198)
#define DP_QSERDES_COM_CMN_MISC1                  (0x2000 + 0x019c)
#define DP_QSERDES_COM_CMN_MODE                   (0x2000 + 0x01a0)
#define DP_QSERDES_COM_CMN_MODE_CONTD             (0x2000 + 0x01a4)
#define DP_QSERDES_COM_VCO_DC_LEVEL_CTRL          (0x2000 + 0x01a8)
#define DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (0x2000 + 0x01ac)
#define DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (0x2000 + 0x01b0)
#define DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 (0x2000 + 0x01b4)
#define DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 (0x2000 + 0x01b8)
#define DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL       (0x2000 + 0x01bc)
#define DP_QSERDES_COM_RESERVED_1                 (0x2000 + 0x01c0)
#define DP_QSERDES_COM_MODE_OPERATION_STATUS      (0x2000 + 0x01c4)

/* Module: USB3_DP_PHY_DP_QSERDES_TX0_DP_QSERDES_TX0_USB3_DP_QMP_TX */
#define DP_QSERDES_TX0_BIST_MODE_LANENO           (0x2200 + 0x0000)
#define DP_QSERDES_TX0_BIST_INVERT                (0x2200 + 0x0004)
#define DP_QSERDES_TX0_CLKBUF_ENABLE              (0x2200 + 0x0008)
#define DP_QSERDES_TX0_TX_EMP_POST1_LVL           (0x2200 + 0x000c)
#define DP_QSERDES_TX0_TX_IDLE_LVL_LARGE_AMP      (0x2200 + 0x0010)
#define DP_QSERDES_TX0_TX_DRV_LVL                 (0x2200 + 0x0014)
#define DP_QSERDES_TX0_TX_DRV_LVL_OFFSET          (0x2200 + 0x0018)
#define DP_QSERDES_TX0_RESET_TSYNC_EN             (0x2200 + 0x001c)
#define DP_QSERDES_TX0_PRE_STALL_LDO_BOOST_EN     (0x2200 + 0x0020)
#define DP_QSERDES_TX0_TX_BAND                    (0x2200 + 0x0024)
#define DP_QSERDES_TX0_SLEW_CNTL                  (0x2200 + 0x0028)
#define DP_QSERDES_TX0_INTERFACE_SELECT           (0x2200 + 0x002c)
#define DP_QSERDES_TX0_LPB_EN                     (0x2200 + 0x0030)
#define DP_QSERDES_TX0_RES_CODE_LANE_TX           (0x2200 + 0x0034)
#define DP_QSERDES_TX0_RES_CODE_LANE_RX           (0x2200 + 0x0038)
#define DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_TX    (0x2200 + 0x003c)
#define DP_QSERDES_TX0_RES_CODE_LANE_OFFSET_RX    (0x2200 + 0x0040)
#define DP_QSERDES_TX0_PERL_LENGTH1               (0x2200 + 0x0044)
#define DP_QSERDES_TX0_PERL_LENGTH2               (0x2200 + 0x0048)
#define DP_QSERDES_TX0_SERDES_BYP_EN_OUT          (0x2200 + 0x004c)
#define DP_QSERDES_TX0_DEBUG_BUS_SEL              (0x2200 + 0x0050)
#define DP_QSERDES_TX0_TRANSCEIVER_BIAS_EN        (0x2200 + 0x0054)
#define DP_QSERDES_TX0_HIGHZ_DRVR_EN              (0x2200 + 0x0058)
#define DP_QSERDES_TX0_TX_POL_INV                 (0x2200 + 0x005c)
#define DP_QSERDES_TX0_PARRATE_REC_DETECT_IDLE_EN (0x2200 + 0x0060)
#define DP_QSERDES_TX0_BIST_PATTERN1              (0x2200 + 0x0064)
#define DP_QSERDES_TX0_BIST_PATTERN2              (0x2200 + 0x0068)
#define DP_QSERDES_TX0_BIST_PATTERN3              (0x2200 + 0x006c)
#define DP_QSERDES_TX0_BIST_PATTERN4              (0x2200 + 0x0070)
#define DP_QSERDES_TX0_BIST_PATTERN5              (0x2200 + 0x0074)
#define DP_QSERDES_TX0_BIST_PATTERN6              (0x2200 + 0x0078)
#define DP_QSERDES_TX0_BIST_PATTERN7              (0x2200 + 0x007c)
#define DP_QSERDES_TX0_BIST_PATTERN8              (0x2200 + 0x0080)
#define DP_QSERDES_TX0_LANE_MODE_1                (0x2200 + 0x0084)
#define DP_QSERDES_TX0_LANE_MODE_2                (0x2200 + 0x0088)
#define DP_QSERDES_TX0_LANE_MODE_3                (0x2200 + 0x008c)
#define DP_QSERDES_TX0_LANE_MODE_4                (0x2200 + 0x0090)
#define DP_QSERDES_TX0_LANE_MODE_5                (0x2200 + 0x0094)
#define DP_QSERDES_TX0_ATB_SEL1                   (0x2200 + 0x0098)
#define DP_QSERDES_TX0_ATB_SEL2                   (0x2200 + 0x009c)
#define DP_QSERDES_TX0_RCV_DETECT_LVL             (0x2200 + 0x00a0)
#define DP_QSERDES_TX0_RCV_DETECT_LVL_2           (0x2200 + 0x00a4)
#define DP_QSERDES_TX0_PRBS_SEED1                 (0x2200 + 0x00a8)
#define DP_QSERDES_TX0_PRBS_SEED2                 (0x2200 + 0x00ac)
#define DP_QSERDES_TX0_PRBS_SEED3                 (0x2200 + 0x00b0)
#define DP_QSERDES_TX0_PRBS_SEED4                 (0x2200 + 0x00b4)
#define DP_QSERDES_TX0_RESET_GEN                  (0x2200 + 0x00b8)
#define DP_QSERDES_TX0_RESET_GEN_MUXES            (0x2200 + 0x00bc)
#define DP_QSERDES_TX0_TRAN_DRVR_EMP_EN           (0x2200 + 0x00c0)
#define DP_QSERDES_TX0_TX_INTERFACE_MODE          (0x2200 + 0x00c4)
#define DP_QSERDES_TX0_VMODE_CTRL1                (0x2200 + 0x00c8)
#define DP_QSERDES_TX0_ALOG_OBSV_BUS_CTRL_1       (0x2200 + 0x00cc)
#define DP_QSERDES_TX0_BIST_STATUS                (0x2200 + 0x00d0)
#define DP_QSERDES_TX0_BIST_ERROR_COUNT1          (0x2200 + 0x00d4)
#define DP_QSERDES_TX0_BIST_ERROR_COUNT2          (0x2200 + 0x00d8)
#define DP_QSERDES_TX0_ALOG_OBSV_BUS_STATUS_1     (0x2200 + 0x00dc)
#define DP_QSERDES_TX0_LANE_DIG_CONFIG            (0x2200 + 0x00e0)
#define DP_QSERDES_TX0_PI_QEC_CTRL                (0x2200 + 0x00e4)
#define DP_QSERDES_TX0_PRE_EMPH                   (0x2200 + 0x00e8)
#define DP_QSERDES_TX0_SW_RESET                   (0x2200 + 0x00ec)
#define DP_QSERDES_TX0_DCC_OFFSET                 (0x2200 + 0x00f0)
#define DP_QSERDES_TX0_DCC_CMUX_POSTCAL_OFFSET    (0x2200 + 0x00f4)
#define DP_QSERDES_TX0_DCC_CMUX_CAL_CTRL1         (0x2200 + 0x00f8)
#define DP_QSERDES_TX0_DCC_CMUX_CAL_CTRL2         (0x2200 + 0x00fc)
#define DP_QSERDES_TX0_DIG_BKUP_CTRL              (0x2200 + 0x0100)
#define DP_QSERDES_TX0_DEBUG_BUS0                 (0x2200 + 0x0104)
#define DP_QSERDES_TX0_DEBUG_BUS1                 (0x2200 + 0x0108)
#define DP_QSERDES_TX0_DEBUG_BUS2                 (0x2200 + 0x010c)
#define DP_QSERDES_TX0_DEBUG_BUS3                 (0x2200 + 0x0110)
#define DP_QSERDES_TX0_READ_EQCODE                (0x2200 + 0x0114)
#define DP_QSERDES_TX0_READ_OFFSETCODE            (0x2200 + 0x0118)
#define DP_QSERDES_TX0_IA_ERROR_COUNTER_LOW       (0x2200 + 0x011c)
#define DP_QSERDES_TX0_IA_ERROR_COUNTER_HIGH      (0x2200 + 0x0120)
#define DP_QSERDES_TX0_VGA_READ_CODE              (0x2200 + 0x0124)
#define DP_QSERDES_TX0_VTH_READ_CODE              (0x2200 + 0x0128)
#define DP_QSERDES_TX0_DFE_TAP1_READ_CODE         (0x2200 + 0x012c)
#define DP_QSERDES_TX0_DFE_TAP2_READ_CODE         (0x2200 + 0x0130)
#define DP_QSERDES_TX0_IDAC_STATUS_I              (0x2200 + 0x0134)
#define DP_QSERDES_TX0_IDAC_STATUS_IBAR           (0x2200 + 0x0138)
#define DP_QSERDES_TX0_IDAC_STATUS_Q              (0x2200 + 0x013c)
#define DP_QSERDES_TX0_IDAC_STATUS_QBAR           (0x2200 + 0x0140)
#define DP_QSERDES_TX0_IDAC_STATUS_A              (0x2200 + 0x0144)
#define DP_QSERDES_TX0_IDAC_STATUS_ABAR           (0x2200 + 0x0148)
#define DP_QSERDES_TX0_IDAC_STATUS_SM_ON          (0x2200 + 0x014c)
#define DP_QSERDES_TX0_IDAC_STATUS_CAL_DONE       (0x2200 + 0x0150)
#define DP_QSERDES_TX0_IDAC_STATUS_SIGNERROR      (0x2200 + 0x0154)
#define DP_QSERDES_TX0_DCC_CAL_STATUS             (0x2200 + 0x0158)
#define DP_QSERDES_TX0_DCC_READ_CODE_STATUS       (0x2200 + 0x015c)

/* Module: USB3_DP_PHY_DP_QSERDES_RX0_DP_QSERDES_RX0_USB3_DP_QMP_RX */
#define DP_QSERDES_RX0_UCDR_FO_GAIN_HALF          (0x2400 + 0x0000)
#define DP_QSERDES_RX0_UCDR_FO_GAIN_QUARTER       (0x2400 + 0x0004)
#define DP_QSERDES_RX0_UCDR_FO_GAIN               (0x2400 + 0x0008)
#define DP_QSERDES_RX0_UCDR_SO_GAIN_HALF          (0x2400 + 0x000c)
#define DP_QSERDES_RX0_UCDR_SO_GAIN_QUARTER       (0x2400 + 0x0010)
#define DP_QSERDES_RX0_UCDR_SO_GAIN               (0x2400 + 0x0014)
#define DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_HALF      (0x2400 + 0x0018)
#define DP_QSERDES_RX0_UCDR_SVS_FO_GAIN_QUARTER   (0x2400 + 0x001c)
#define DP_QSERDES_RX0_UCDR_SVS_FO_GAIN           (0x2400 + 0x0020)
#define DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_HALF      (0x2400 + 0x0024)
#define DP_QSERDES_RX0_UCDR_SVS_SO_GAIN_QUARTER   (0x2400 + 0x0028)
#define DP_QSERDES_RX0_UCDR_SVS_SO_GAIN           (0x2400 + 0x002c)
#define DP_QSERDES_RX0_UCDR_FASTLOCK_FO_GAIN      (0x2400 + 0x0030)
#define DP_QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE (0x2400 + 0x0034)
#define DP_QSERDES_RX0_UCDR_FO_TO_SO_DELAY        (0x2400 + 0x0038)
#define DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_LOW    (0x2400 + 0x003c)
#define DP_QSERDES_RX0_UCDR_FASTLOCK_COUNT_HIGH   (0x2400 + 0x0040)
#define DP_QSERDES_RX0_UCDR_PI_CONTROLS           (0x2400 + 0x0044)
#define DP_QSERDES_RX0_UCDR_PI_CTRL2              (0x2400 + 0x0048)
#define DP_QSERDES_RX0_UCDR_SB2_THRESH1           (0x2400 + 0x004c)
#define DP_QSERDES_RX0_UCDR_SB2_THRESH2           (0x2400 + 0x0050)
#define DP_QSERDES_RX0_UCDR_SB2_GAIN1             (0x2400 + 0x0054)
#define DP_QSERDES_RX0_UCDR_SB2_GAIN2             (0x2400 + 0x0058)
#define DP_QSERDES_RX0_AUX_CONTROL                (0x2400 + 0x005c)
#define DP_QSERDES_RX0_AUX_DATA_TCOARSE_TFINE     (0x2400 + 0x0060)
#define DP_QSERDES_RX0_RCLK_AUXDATA_SEL           (0x2400 + 0x0064)
#define DP_QSERDES_RX0_AC_JTAG_ENABLE             (0x2400 + 0x0068)
#define DP_QSERDES_RX0_AC_JTAG_INITP              (0x2400 + 0x006c)
#define DP_QSERDES_RX0_AC_JTAG_INITN              (0x2400 + 0x0070)
#define DP_QSERDES_RX0_AC_JTAG_LVL                (0x2400 + 0x0074)
#define DP_QSERDES_RX0_AC_JTAG_MODE               (0x2400 + 0x0078)
#define DP_QSERDES_RX0_AC_JTAG_RESET              (0x2400 + 0x007c)
#define DP_QSERDES_RX0_RX_TERM_BW                 (0x2400 + 0x0080)
#define DP_QSERDES_RX0_RX_RCVR_IQ_EN              (0x2400 + 0x0084)
#define DP_QSERDES_RX0_RX_IDAC_I_DC_OFFSETS       (0x2400 + 0x0088)
#define DP_QSERDES_RX0_RX_IDAC_IBAR_DC_OFFSETS    (0x2400 + 0x008c)
#define DP_QSERDES_RX0_RX_IDAC_Q_DC_OFFSETS       (0x2400 + 0x0090)
#define DP_QSERDES_RX0_RX_IDAC_QBAR_DC_OFFSETS    (0x2400 + 0x0094)
#define DP_QSERDES_RX0_RX_IDAC_A_DC_OFFSETS       (0x2400 + 0x0098)
#define DP_QSERDES_RX0_RX_IDAC_ABAR_DC_OFFSETS    (0x2400 + 0x009c)
#define DP_QSERDES_RX0_RX_IDAC_EN                 (0x2400 + 0x00a0)
#define DP_QSERDES_RX0_RX_IDAC_ENABLES            (0x2400 + 0x00a4)
#define DP_QSERDES_RX0_RX_IDAC_SIGN               (0x2400 + 0x00a8)
#define DP_QSERDES_RX0_RX_HIGHZ_HIGHRATE          (0x2400 + 0x00ac)
#define DP_QSERDES_RX0_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x2400 + 0x00b0)
#define DP_QSERDES_RX0_DFE_1                      (0x2400 + 0x00b4)
#define DP_QSERDES_RX0_DFE_2                      (0x2400 + 0x00b8)
#define DP_QSERDES_RX0_DFE_3                      (0x2400 + 0x00bc)
#define DP_QSERDES_RX0_DFE_4                      (0x2400 + 0x00c0)
#define DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH1       (0x2400 + 0x00c4)
#define DP_QSERDES_RX0_TX_ADAPT_PRE_THRESH2       (0x2400 + 0x00c8)
#define DP_QSERDES_RX0_TX_ADAPT_POST_THRESH       (0x2400 + 0x00cc)
#define DP_QSERDES_RX0_TX_ADAPT_MAIN_THRESH       (0x2400 + 0x00d0)
#define DP_QSERDES_RX0_VGA_CAL_CNTRL1             (0x2400 + 0x00d4)
#define DP_QSERDES_RX0_VGA_CAL_CNTRL2             (0x2400 + 0x00d8)
#define DP_QSERDES_RX0_GM_CAL                     (0x2400 + 0x00dc)
#define DP_QSERDES_RX0_RX_VGA_GAIN2_LSB           (0x2400 + 0x00e0)
#define DP_QSERDES_RX0_RX_VGA_GAIN2_MSB           (0x2400 + 0x00e4)
#define DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL1      (0x2400 + 0x00e8)
#define DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2      (0x2400 + 0x00ec)
#define DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3      (0x2400 + 0x00f0)
#define DP_QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4      (0x2400 + 0x00f4)
#define DP_QSERDES_RX0_RX_IDAC_TSETTLE_LOW        (0x2400 + 0x00f8)
#define DP_QSERDES_RX0_RX_IDAC_TSETTLE_HIGH       (0x2400 + 0x00fc)
#define DP_QSERDES_RX0_RX_IDAC_MEASURE_TIME       (0x2400 + 0x0100)
#define DP_QSERDES_RX0_RX_IDAC_ACCUMULATOR        (0x2400 + 0x0104)
#define DP_QSERDES_RX0_RX_EQ_OFFSET_LSB           (0x2400 + 0x0108)
#define DP_QSERDES_RX0_RX_EQ_OFFSET_MSB           (0x2400 + 0x010c)
#define DP_QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2400 + 0x0110)
#define DP_QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2   (0x2400 + 0x0114)
#define DP_QSERDES_RX0_SIGDET_ENABLES             (0x2400 + 0x0118)
#define DP_QSERDES_RX0_SIGDET_CNTRL               (0x2400 + 0x011c)
#define DP_QSERDES_RX0_SIGDET_LVL                 (0x2400 + 0x0120)
#define DP_QSERDES_RX0_SIGDET_DEGLITCH_CNTRL      (0x2400 + 0x0124)
#define DP_QSERDES_RX0_RX_BAND                    (0x2400 + 0x0128)
#define DP_QSERDES_RX0_CDR_FREEZE_UP_DN           (0x2400 + 0x012c)
#define DP_QSERDES_RX0_CDR_RESET_OVERRIDE         (0x2400 + 0x0130)
#define DP_QSERDES_RX0_RX_INTERFACE_MODE          (0x2400 + 0x0134)
#define DP_QSERDES_RX0_JITTER_GEN_MODE            (0x2400 + 0x0138)
#define DP_QSERDES_RX0_SJ_AMP1                    (0x2400 + 0x013c)
#define DP_QSERDES_RX0_SJ_AMP2                    (0x2400 + 0x0140)
#define DP_QSERDES_RX0_SJ_PER1                    (0x2400 + 0x0144)
#define DP_QSERDES_RX0_SJ_PER2                    (0x2400 + 0x0148)
#define DP_QSERDES_RX0_PPM_OFFSET1                (0x2400 + 0x014c)
#define DP_QSERDES_RX0_PPM_OFFSET2                (0x2400 + 0x0150)
#define DP_QSERDES_RX0_SIGN_PPM_PERIOD1           (0x2400 + 0x0154)
#define DP_QSERDES_RX0_SIGN_PPM_PERIOD2           (0x2400 + 0x0158)
#define DP_QSERDES_RX0_RX_MODE_00_LOW             (0x2400 + 0x015c)
#define DP_QSERDES_RX0_RX_MODE_00_HIGH            (0x2400 + 0x0160)
#define DP_QSERDES_RX0_RX_MODE_00_HIGH2           (0x2400 + 0x0164)
#define DP_QSERDES_RX0_RX_MODE_00_HIGH3           (0x2400 + 0x0168)
#define DP_QSERDES_RX0_RX_MODE_00_HIGH4           (0x2400 + 0x016c)
#define DP_QSERDES_RX0_RX_MODE_01_LOW             (0x2400 + 0x0170)
#define DP_QSERDES_RX0_RX_MODE_01_HIGH            (0x2400 + 0x0174)
#define DP_QSERDES_RX0_RX_MODE_01_HIGH2           (0x2400 + 0x0178)
#define DP_QSERDES_RX0_RX_MODE_01_HIGH3           (0x2400 + 0x017c)
#define DP_QSERDES_RX0_RX_MODE_01_HIGH4           (0x2400 + 0x0180)
#define DP_QSERDES_RX0_RX_MODE_10_LOW             (0x2400 + 0x0184)
#define DP_QSERDES_RX0_RX_MODE_10_HIGH            (0x2400 + 0x0188)
#define DP_QSERDES_RX0_RX_MODE_10_HIGH2           (0x2400 + 0x018c)
#define DP_QSERDES_RX0_RX_MODE_10_HIGH3           (0x2400 + 0x0190)
#define DP_QSERDES_RX0_RX_MODE_10_HIGH4           (0x2400 + 0x0194)
#define DP_QSERDES_RX0_PHPRE_CTRL                 (0x2400 + 0x0198)
#define DP_QSERDES_RX0_PHPRE_INITVAL              (0x2400 + 0x019c)
#define DP_QSERDES_RX0_DFE_EN_TIMER               (0x2400 + 0x01a0)
#define DP_QSERDES_RX0_DFE_CTLE_POST_CAL_OFFSET   (0x2400 + 0x01a4)
#define DP_QSERDES_RX0_DCC_CTRL1                  (0x2400 + 0x01a8)
#define DP_QSERDES_RX0_DCC_CTRL2                  (0x2400 + 0x01ac)
#define DP_QSERDES_RX0_VTH_CODE                   (0x2400 + 0x01b0)
#define DP_QSERDES_RX0_VTH_MIN_THRESH             (0x2400 + 0x01b4)
#define DP_QSERDES_RX0_VTH_MAX_THRESH             (0x2400 + 0x01b8)
#define DP_QSERDES_RX0_ALOG_OBSV_BUS_CTRL_1       (0x2400 + 0x01bc)
#define DP_QSERDES_RX0_PI_CTRL1                   (0x2400 + 0x01c0)
#define DP_QSERDES_RX0_PI_CTRL2                   (0x2400 + 0x01c4)
#define DP_QSERDES_RX0_PI_QUAD                    (0x2400 + 0x01c8)
#define DP_QSERDES_RX0_IDATA1                     (0x2400 + 0x01cc)
#define DP_QSERDES_RX0_IDATA2                     (0x2400 + 0x01d0)
#define DP_QSERDES_RX0_AUX_DATA1                  (0x2400 + 0x01d4)
#define DP_QSERDES_RX0_AUX_DATA2                  (0x2400 + 0x01d8)
#define DP_QSERDES_RX0_AC_JTAG_OUTP               (0x2400 + 0x01dc)
#define DP_QSERDES_RX0_AC_JTAG_OUTN               (0x2400 + 0x01e0)
#define DP_QSERDES_RX0_RX_SIGDET                  (0x2400 + 0x01e4)
#define DP_QSERDES_RX0_ALOG_OBSV_BUS_STATUS_1     (0x2400 + 0x01e8)

/* Module: USB3_DP_PHY_DP_QSERDES_TX1_DP_QSERDES_TX1_USB3_DP_QMP_TX */
#define DP_QSERDES_TX1_BIST_MODE_LANENO           (0x2600 + 0x0000)
#define DP_QSERDES_TX1_BIST_INVERT                (0x2600 + 0x0004)
#define DP_QSERDES_TX1_CLKBUF_ENABLE              (0x2600 + 0x0008)
#define DP_QSERDES_TX1_TX_EMP_POST1_LVL           (0x2600 + 0x000c)
#define DP_QSERDES_TX1_TX_IDLE_LVL_LARGE_AMP      (0x2600 + 0x0010)
#define DP_QSERDES_TX1_TX_DRV_LVL                 (0x2600 + 0x0014)
#define DP_QSERDES_TX1_TX_DRV_LVL_OFFSET          (0x2600 + 0x0018)
#define DP_QSERDES_TX1_RESET_TSYNC_EN             (0x2600 + 0x001c)
#define DP_QSERDES_TX1_PRE_STALL_LDO_BOOST_EN     (0x2600 + 0x0020)
#define DP_QSERDES_TX1_TX_BAND                    (0x2600 + 0x0024)
#define DP_QSERDES_TX1_SLEW_CNTL                  (0x2600 + 0x0028)
#define DP_QSERDES_TX1_INTERFACE_SELECT           (0x2600 + 0x002c)
#define DP_QSERDES_TX1_LPB_EN                     (0x2600 + 0x0030)
#define DP_QSERDES_TX1_RES_CODE_LANE_TX           (0x2600 + 0x0034)
#define DP_QSERDES_TX1_RES_CODE_LANE_RX           (0x2600 + 0x0038)
#define DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_TX    (0x2600 + 0x003c)
#define DP_QSERDES_TX1_RES_CODE_LANE_OFFSET_RX    (0x2600 + 0x0040)
#define DP_QSERDES_TX1_PERL_LENGTH1               (0x2600 + 0x0044)
#define DP_QSERDES_TX1_PERL_LENGTH2               (0x2600 + 0x0048)
#define DP_QSERDES_TX1_SERDES_BYP_EN_OUT          (0x2600 + 0x004c)
#define DP_QSERDES_TX1_DEBUG_BUS_SEL              (0x2600 + 0x0050)
#define DP_QSERDES_TX1_TRANSCEIVER_BIAS_EN        (0x2600 + 0x0054)
#define DP_QSERDES_TX1_HIGHZ_DRVR_EN              (0x2600 + 0x0058)
#define DP_QSERDES_TX1_TX_POL_INV                 (0x2600 + 0x005c)
#define DP_QSERDES_TX1_PARRATE_REC_DETECT_IDLE_EN (0x2600 + 0x0060)
#define DP_QSERDES_TX1_BIST_PATTERN1              (0x2600 + 0x0064)
#define DP_QSERDES_TX1_BIST_PATTERN2              (0x2600 + 0x0068)
#define DP_QSERDES_TX1_BIST_PATTERN3              (0x2600 + 0x006c)
#define DP_QSERDES_TX1_BIST_PATTERN4              (0x2600 + 0x0070)
#define DP_QSERDES_TX1_BIST_PATTERN5              (0x2600 + 0x0074)
#define DP_QSERDES_TX1_BIST_PATTERN6              (0x2600 + 0x0078)
#define DP_QSERDES_TX1_BIST_PATTERN7              (0x2600 + 0x007c)
#define DP_QSERDES_TX1_BIST_PATTERN8              (0x2600 + 0x0080)
#define DP_QSERDES_TX1_LANE_MODE_1                (0x2600 + 0x0084)
#define DP_QSERDES_TX1_LANE_MODE_2                (0x2600 + 0x0088)
#define DP_QSERDES_TX1_LANE_MODE_3                (0x2600 + 0x008c)
#define DP_QSERDES_TX1_LANE_MODE_4                (0x2600 + 0x0090)
#define DP_QSERDES_TX1_LANE_MODE_5                (0x2600 + 0x0094)
#define DP_QSERDES_TX1_ATB_SEL1                   (0x2600 + 0x0098)
#define DP_QSERDES_TX1_ATB_SEL2                   (0x2600 + 0x009c)
#define DP_QSERDES_TX1_RCV_DETECT_LVL             (0x2600 + 0x00a0)
#define DP_QSERDES_TX1_RCV_DETECT_LVL_2           (0x2600 + 0x00a4)
#define DP_QSERDES_TX1_PRBS_SEED1                 (0x2600 + 0x00a8)
#define DP_QSERDES_TX1_PRBS_SEED2                 (0x2600 + 0x00ac)
#define DP_QSERDES_TX1_PRBS_SEED3                 (0x2600 + 0x00b0)
#define DP_QSERDES_TX1_PRBS_SEED4                 (0x2600 + 0x00b4)
#define DP_QSERDES_TX1_RESET_GEN                  (0x2600 + 0x00b8)
#define DP_QSERDES_TX1_RESET_GEN_MUXES            (0x2600 + 0x00bc)
#define DP_QSERDES_TX1_TRAN_DRVR_EMP_EN           (0x2600 + 0x00c0)
#define DP_QSERDES_TX1_TX_INTERFACE_MODE          (0x2600 + 0x00c4)
#define DP_QSERDES_TX1_VMODE_CTRL1                (0x2600 + 0x00c8)
#define DP_QSERDES_TX1_ALOG_OBSV_BUS_CTRL_1       (0x2600 + 0x00cc)
#define DP_QSERDES_TX1_BIST_STATUS                (0x2600 + 0x00d0)
#define DP_QSERDES_TX1_BIST_ERROR_COUNT1          (0x2600 + 0x00d4)
#define DP_QSERDES_TX1_BIST_ERROR_COUNT2          (0x2600 + 0x00d8)
#define DP_QSERDES_TX1_ALOG_OBSV_BUS_STATUS_1     (0x2600 + 0x00dc)
#define DP_QSERDES_TX1_LANE_DIG_CONFIG            (0x2600 + 0x00e0)
#define DP_QSERDES_TX1_PI_QEC_CTRL                (0x2600 + 0x00e4)
#define DP_QSERDES_TX1_PRE_EMPH                   (0x2600 + 0x00e8)
#define DP_QSERDES_TX1_SW_RESET                   (0x2600 + 0x00ec)
#define DP_QSERDES_TX1_DCC_OFFSET                 (0x2600 + 0x00f0)
#define DP_QSERDES_TX1_DCC_CMUX_POSTCAL_OFFSET    (0x2600 + 0x00f4)
#define DP_QSERDES_TX1_DCC_CMUX_CAL_CTRL1         (0x2600 + 0x00f8)
#define DP_QSERDES_TX1_DCC_CMUX_CAL_CTRL2         (0x2600 + 0x00fc)
#define DP_QSERDES_TX1_DIG_BKUP_CTRL              (0x2600 + 0x0100)
#define DP_QSERDES_TX1_DEBUG_BUS0                 (0x2600 + 0x0104)
#define DP_QSERDES_TX1_DEBUG_BUS1                 (0x2600 + 0x0108)
#define DP_QSERDES_TX1_DEBUG_BUS2                 (0x2600 + 0x010c)
#define DP_QSERDES_TX1_DEBUG_BUS3                 (0x2600 + 0x0110)
#define DP_QSERDES_TX1_READ_EQCODE                (0x2600 + 0x0114)
#define DP_QSERDES_TX1_READ_OFFSETCODE            (0x2600 + 0x0118)
#define DP_QSERDES_TX1_IA_ERROR_COUNTER_LOW       (0x2600 + 0x011c)
#define DP_QSERDES_TX1_IA_ERROR_COUNTER_HIGH      (0x2600 + 0x0120)
#define DP_QSERDES_TX1_VGA_READ_CODE              (0x2600 + 0x0124)
#define DP_QSERDES_TX1_VTH_READ_CODE              (0x2600 + 0x0128)
#define DP_QSERDES_TX1_DFE_TAP1_READ_CODE         (0x2600 + 0x012c)
#define DP_QSERDES_TX1_DFE_TAP2_READ_CODE         (0x2600 + 0x0130)
#define DP_QSERDES_TX1_IDAC_STATUS_I              (0x2600 + 0x0134)
#define DP_QSERDES_TX1_IDAC_STATUS_IBAR           (0x2600 + 0x0138)
#define DP_QSERDES_TX1_IDAC_STATUS_Q              (0x2600 + 0x013c)
#define DP_QSERDES_TX1_IDAC_STATUS_QBAR           (0x2600 + 0x0140)
#define DP_QSERDES_TX1_IDAC_STATUS_A              (0x2600 + 0x0144)
#define DP_QSERDES_TX1_IDAC_STATUS_ABAR           (0x2600 + 0x0148)
#define DP_QSERDES_TX1_IDAC_STATUS_SM_ON          (0x2600 + 0x014c)
#define DP_QSERDES_TX1_IDAC_STATUS_CAL_DONE       (0x2600 + 0x0150)
#define DP_QSERDES_TX1_IDAC_STATUS_SIGNERROR      (0x2600 + 0x0154)
#define DP_QSERDES_TX1_DCC_CAL_STATUS             (0x2600 + 0x0158)
#define DP_QSERDES_TX1_DCC_READ_CODE_STATUS       (0x2600 + 0x015c)

/* Module: USB3_DP_PHY_DP_QSERDES_RX1_DP_QSERDES_RX1_USB3_DP_QMP_RX */
#define DP_QSERDES_RX1_UCDR_FO_GAIN_HALF          (0x2800 + 0x0000)
#define DP_QSERDES_RX1_UCDR_FO_GAIN_QUARTER       (0x2800 + 0x0004)
#define DP_QSERDES_RX1_UCDR_FO_GAIN               (0x2800 + 0x0008)
#define DP_QSERDES_RX1_UCDR_SO_GAIN_HALF          (0x2800 + 0x000c)
#define DP_QSERDES_RX1_UCDR_SO_GAIN_QUARTER       (0x2800 + 0x0010)
#define DP_QSERDES_RX1_UCDR_SO_GAIN               (0x2800 + 0x0014)
#define DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_HALF      (0x2800 + 0x0018)
#define DP_QSERDES_RX1_UCDR_SVS_FO_GAIN_QUARTER   (0x2800 + 0x001c)
#define DP_QSERDES_RX1_UCDR_SVS_FO_GAIN           (0x2800 + 0x0020)
#define DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_HALF      (0x2800 + 0x0024)
#define DP_QSERDES_RX1_UCDR_SVS_SO_GAIN_QUARTER   (0x2800 + 0x0028)
#define DP_QSERDES_RX1_UCDR_SVS_SO_GAIN           (0x2800 + 0x002c)
#define DP_QSERDES_RX1_UCDR_FASTLOCK_FO_GAIN      (0x2800 + 0x0030)
#define DP_QSERDES_RX1_UCDR_SO_SATURATION_AND_ENABLE (0x2800 + 0x0034)
#define DP_QSERDES_RX1_UCDR_FO_TO_SO_DELAY        (0x2800 + 0x0038)
#define DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_LOW    (0x2800 + 0x003c)
#define DP_QSERDES_RX1_UCDR_FASTLOCK_COUNT_HIGH   (0x2800 + 0x0040)
#define DP_QSERDES_RX1_UCDR_PI_CONTROLS           (0x2800 + 0x0044)
#define DP_QSERDES_RX1_UCDR_PI_CTRL2              (0x2800 + 0x0048)
#define DP_QSERDES_RX1_UCDR_SB2_THRESH1           (0x2800 + 0x004c)
#define DP_QSERDES_RX1_UCDR_SB2_THRESH2           (0x2800 + 0x0050)
#define DP_QSERDES_RX1_UCDR_SB2_GAIN1             (0x2800 + 0x0054)
#define DP_QSERDES_RX1_UCDR_SB2_GAIN2             (0x2800 + 0x0058)
#define DP_QSERDES_RX1_AUX_CONTROL                (0x2800 + 0x005c)
#define DP_QSERDES_RX1_AUX_DATA_TCOARSE_TFINE     (0x2800 + 0x0060)
#define DP_QSERDES_RX1_RCLK_AUXDATA_SEL           (0x2800 + 0x0064)
#define DP_QSERDES_RX1_AC_JTAG_ENABLE             (0x2800 + 0x0068)
#define DP_QSERDES_RX1_AC_JTAG_INITP              (0x2800 + 0x006c)
#define DP_QSERDES_RX1_AC_JTAG_INITN              (0x2800 + 0x0070)
#define DP_QSERDES_RX1_AC_JTAG_LVL                (0x2800 + 0x0074)
#define DP_QSERDES_RX1_AC_JTAG_MODE               (0x2800 + 0x0078)
#define DP_QSERDES_RX1_AC_JTAG_RESET              (0x2800 + 0x007c)
#define DP_QSERDES_RX1_RX_TERM_BW                 (0x2800 + 0x0080)
#define DP_QSERDES_RX1_RX_RCVR_IQ_EN              (0x2800 + 0x0084)
#define DP_QSERDES_RX1_RX_IDAC_I_DC_OFFSETS       (0x2800 + 0x0088)
#define DP_QSERDES_RX1_RX_IDAC_IBAR_DC_OFFSETS    (0x2800 + 0x008c)
#define DP_QSERDES_RX1_RX_IDAC_Q_DC_OFFSETS       (0x2800 + 0x0090)
#define DP_QSERDES_RX1_RX_IDAC_QBAR_DC_OFFSETS    (0x2800 + 0x0094)
#define DP_QSERDES_RX1_RX_IDAC_A_DC_OFFSETS       (0x2800 + 0x0098)
#define DP_QSERDES_RX1_RX_IDAC_ABAR_DC_OFFSETS    (0x2800 + 0x009c)
#define DP_QSERDES_RX1_RX_IDAC_EN                 (0x2800 + 0x00a0)
#define DP_QSERDES_RX1_RX_IDAC_ENABLES            (0x2800 + 0x00a4)
#define DP_QSERDES_RX1_RX_IDAC_SIGN               (0x2800 + 0x00a8)
#define DP_QSERDES_RX1_RX_HIGHZ_HIGHRATE          (0x2800 + 0x00ac)
#define DP_QSERDES_RX1_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x2800 + 0x00b0)
#define DP_QSERDES_RX1_DFE_1                      (0x2800 + 0x00b4)
#define DP_QSERDES_RX1_DFE_2                      (0x2800 + 0x00b8)
#define DP_QSERDES_RX1_DFE_3                      (0x2800 + 0x00bc)
#define DP_QSERDES_RX1_DFE_4                      (0x2800 + 0x00c0)
#define DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH1       (0x2800 + 0x00c4)
#define DP_QSERDES_RX1_TX_ADAPT_PRE_THRESH2       (0x2800 + 0x00c8)
#define DP_QSERDES_RX1_TX_ADAPT_POST_THRESH       (0x2800 + 0x00cc)
#define DP_QSERDES_RX1_TX_ADAPT_MAIN_THRESH       (0x2800 + 0x00d0)
#define DP_QSERDES_RX1_VGA_CAL_CNTRL1             (0x2800 + 0x00d4)
#define DP_QSERDES_RX1_VGA_CAL_CNTRL2             (0x2800 + 0x00d8)
#define DP_QSERDES_RX1_GM_CAL                     (0x2800 + 0x00dc)
#define DP_QSERDES_RX1_RX_VGA_GAIN2_LSB           (0x2800 + 0x00e0)
#define DP_QSERDES_RX1_RX_VGA_GAIN2_MSB           (0x2800 + 0x00e4)
#define DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL1      (0x2800 + 0x00e8)
#define DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL2      (0x2800 + 0x00ec)
#define DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL3      (0x2800 + 0x00f0)
#define DP_QSERDES_RX1_RX_EQU_ADAPTOR_CNTRL4      (0x2800 + 0x00f4)
#define DP_QSERDES_RX1_RX_IDAC_TSETTLE_LOW        (0x2800 + 0x00f8)
#define DP_QSERDES_RX1_RX_IDAC_TSETTLE_HIGH       (0x2800 + 0x00fc)
#define DP_QSERDES_RX1_RX_IDAC_MEASURE_TIME       (0x2800 + 0x0100)
#define DP_QSERDES_RX1_RX_IDAC_ACCUMULATOR        (0x2800 + 0x0104)
#define DP_QSERDES_RX1_RX_EQ_OFFSET_LSB           (0x2800 + 0x0108)
#define DP_QSERDES_RX1_RX_EQ_OFFSET_MSB           (0x2800 + 0x010c)
#define DP_QSERDES_RX1_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2800 + 0x0110)
#define DP_QSERDES_RX1_RX_OFFSET_ADAPTOR_CNTRL2   (0x2800 + 0x0114)
#define DP_QSERDES_RX1_SIGDET_ENABLES             (0x2800 + 0x0118)
#define DP_QSERDES_RX1_SIGDET_CNTRL               (0x2800 + 0x011c)
#define DP_QSERDES_RX1_SIGDET_LVL                 (0x2800 + 0x0120)
#define DP_QSERDES_RX1_SIGDET_DEGLITCH_CNTRL      (0x2800 + 0x0124)
#define DP_QSERDES_RX1_RX_BAND                    (0x2800 + 0x0128)
#define DP_QSERDES_RX1_CDR_FREEZE_UP_DN           (0x2800 + 0x012c)
#define DP_QSERDES_RX1_CDR_RESET_OVERRIDE         (0x2800 + 0x0130)
#define DP_QSERDES_RX1_RX_INTERFACE_MODE          (0x2800 + 0x0134)
#define DP_QSERDES_RX1_JITTER_GEN_MODE            (0x2800 + 0x0138)
#define DP_QSERDES_RX1_SJ_AMP1                    (0x2800 + 0x013c)
#define DP_QSERDES_RX1_SJ_AMP2                    (0x2800 + 0x0140)
#define DP_QSERDES_RX1_SJ_PER1                    (0x2800 + 0x0144)
#define DP_QSERDES_RX1_SJ_PER2                    (0x2800 + 0x0148)
#define DP_QSERDES_RX1_PPM_OFFSET1                (0x2800 + 0x014c)
#define DP_QSERDES_RX1_PPM_OFFSET2                (0x2800 + 0x0150)
#define DP_QSERDES_RX1_SIGN_PPM_PERIOD1           (0x2800 + 0x0154)
#define DP_QSERDES_RX1_SIGN_PPM_PERIOD2           (0x2800 + 0x0158)
#define DP_QSERDES_RX1_RX_MODE_00_LOW             (0x2800 + 0x015c)
#define DP_QSERDES_RX1_RX_MODE_00_HIGH            (0x2800 + 0x0160)
#define DP_QSERDES_RX1_RX_MODE_00_HIGH2           (0x2800 + 0x0164)
#define DP_QSERDES_RX1_RX_MODE_00_HIGH3           (0x2800 + 0x0168)
#define DP_QSERDES_RX1_RX_MODE_00_HIGH4           (0x2800 + 0x016c)
#define DP_QSERDES_RX1_RX_MODE_01_LOW             (0x2800 + 0x0170)
#define DP_QSERDES_RX1_RX_MODE_01_HIGH            (0x2800 + 0x0174)
#define DP_QSERDES_RX1_RX_MODE_01_HIGH2           (0x2800 + 0x0178)
#define DP_QSERDES_RX1_RX_MODE_01_HIGH3           (0x2800 + 0x017c)
#define DP_QSERDES_RX1_RX_MODE_01_HIGH4           (0x2800 + 0x0180)
#define DP_QSERDES_RX1_RX_MODE_10_LOW             (0x2800 + 0x0184)
#define DP_QSERDES_RX1_RX_MODE_10_HIGH            (0x2800 + 0x0188)
#define DP_QSERDES_RX1_RX_MODE_10_HIGH2           (0x2800 + 0x018c)
#define DP_QSERDES_RX1_RX_MODE_10_HIGH3           (0x2800 + 0x0190)
#define DP_QSERDES_RX1_RX_MODE_10_HIGH4           (0x2800 + 0x0194)
#define DP_QSERDES_RX1_PHPRE_CTRL                 (0x2800 + 0x0198)
#define DP_QSERDES_RX1_PHPRE_INITVAL              (0x2800 + 0x019c)
#define DP_QSERDES_RX1_DFE_EN_TIMER               (0x2800 + 0x01a0)
#define DP_QSERDES_RX1_DFE_CTLE_POST_CAL_OFFSET   (0x2800 + 0x01a4)
#define DP_QSERDES_RX1_DCC_CTRL1                  (0x2800 + 0x01a8)
#define DP_QSERDES_RX1_DCC_CTRL2                  (0x2800 + 0x01ac)
#define DP_QSERDES_RX1_VTH_CODE                   (0x2800 + 0x01b0)
#define DP_QSERDES_RX1_VTH_MIN_THRESH             (0x2800 + 0x01b4)
#define DP_QSERDES_RX1_VTH_MAX_THRESH             (0x2800 + 0x01b8)
#define DP_QSERDES_RX1_ALOG_OBSV_BUS_CTRL_1       (0x2800 + 0x01bc)
#define DP_QSERDES_RX1_PI_CTRL1                   (0x2800 + 0x01c0)
#define DP_QSERDES_RX1_PI_CTRL2                   (0x2800 + 0x01c4)
#define DP_QSERDES_RX1_PI_QUAD                    (0x2800 + 0x01c8)
#define DP_QSERDES_RX1_IDATA1                     (0x2800 + 0x01cc)
#define DP_QSERDES_RX1_IDATA2                     (0x2800 + 0x01d0)
#define DP_QSERDES_RX1_AUX_DATA1                  (0x2800 + 0x01d4)
#define DP_QSERDES_RX1_AUX_DATA2                  (0x2800 + 0x01d8)
#define DP_QSERDES_RX1_AC_JTAG_OUTP               (0x2800 + 0x01dc)
#define DP_QSERDES_RX1_AC_JTAG_OUTN               (0x2800 + 0x01e0)
#define DP_QSERDES_RX1_RX_SIGDET                  (0x2800 + 0x01e4)
#define DP_QSERDES_RX1_ALOG_OBSV_BUS_STATUS_1     (0x2800 + 0x01e8)

/* Module: USB3_DP_PHY_DP_DP_DP_PHY */
#define DP_DP_PHY_REVISION_ID0                    (0x2a00 + 0x0000)
#define DP_DP_PHY_REVISION_ID1                    (0x2a00 + 0x0004)
#define DP_DP_PHY_REVISION_ID2                    (0x2a00 + 0x0008)
#define DP_DP_PHY_REVISION_ID3                    (0x2a00 + 0x000c)
#define DP_DP_PHY_CFG                             (0x2a00 + 0x0010)
#define DP_DP_PHY_CFG_1                           (0x2a00 + 0x0014)
#define DP_DP_PHY_PD_CTL                          (0x2a00 + 0x0018)
#define DP_DP_PHY_MODE                            (0x2a00 + 0x001c)
#define DP_DP_PHY_AUX_CFG0                        (0x2a00 + 0x0020)
#define DP_DP_PHY_AUX_CFG1                        (0x2a00 + 0x0024)
#define DP_DP_PHY_AUX_CFG2                        (0x2a00 + 0x0028)
#define DP_DP_PHY_AUX_CFG3                        (0x2a00 + 0x002c)
#define DP_DP_PHY_AUX_CFG4                        (0x2a00 + 0x0030)
#define DP_DP_PHY_AUX_CFG5                        (0x2a00 + 0x0034)
#define DP_DP_PHY_AUX_CFG6                        (0x2a00 + 0x0038)
#define DP_DP_PHY_AUX_CFG7                        (0x2a00 + 0x003c)
#define DP_DP_PHY_AUX_CFG8                        (0x2a00 + 0x0040)
#define DP_DP_PHY_AUX_CFG9                        (0x2a00 + 0x0044)
#define DP_DP_PHY_AUX_CFG10                       (0x2a00 + 0x0048)
#define DP_DP_PHY_AUX_CFG11                       (0x2a00 + 0x004c)
#define DP_DP_PHY_AUX_CFG12                       (0x2a00 + 0x0050)
#define DP_DP_PHY_AUX_INTERRUPT_MASK              (0x2a00 + 0x0054)
#define DP_DP_PHY_AUX_INTERRUPT_CLEAR             (0x2a00 + 0x0058)
#define DP_DP_PHY_AUX_BIST_CFG                    (0x2a00 + 0x005c)
#define DP_DP_PHY_AUX_BIST_PRBS_SEED              (0x2a00 + 0x0060)
#define DP_DP_PHY_AUX_BIST_PRBS_POLY              (0x2a00 + 0x0064)
#define DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB         (0x2a00 + 0x0068)
#define DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB         (0x2a00 + 0x006c)
#define DP_DP_PHY_VCO_DIV                         (0x2a00 + 0x0070)
#define DP_DP_PHY_TSYNC_OVRD                      (0x2a00 + 0x0074)
#define DP_DP_PHY_TX0_TX1_LANE_CTL                (0x2a00 + 0x0078)
#define DP_DP_PHY_TX0_TX1_BIST_CFG0               (0x2a00 + 0x007c)
#define DP_DP_PHY_TX0_TX1_BIST_CFG1               (0x2a00 + 0x0080)
#define DP_DP_PHY_TX0_TX1_BIST_CFG2               (0x2a00 + 0x0084)
#define DP_DP_PHY_TX0_TX1_BIST_CFG3               (0x2a00 + 0x0088)
#define DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0         (0x2a00 + 0x008c)
#define DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1         (0x2a00 + 0x0090)
#define DP_DP_PHY_TX0_TX1_BIST_PATTERN0           (0x2a00 + 0x0094)
#define DP_DP_PHY_TX0_TX1_BIST_PATTERN1           (0x2a00 + 0x0098)
#define DP_DP_PHY_TX2_TX3_LANE_CTL                (0x2a00 + 0x009c)
#define DP_DP_PHY_TX2_TX3_BIST_CFG0               (0x2a00 + 0x00a0)
#define DP_DP_PHY_TX2_TX3_BIST_CFG1               (0x2a00 + 0x00a4)
#define DP_DP_PHY_TX2_TX3_BIST_CFG2               (0x2a00 + 0x00a8)
#define DP_DP_PHY_TX2_TX3_BIST_CFG3               (0x2a00 + 0x00ac)
#define DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0         (0x2a00 + 0x00b0)
#define DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1         (0x2a00 + 0x00b4)
#define DP_DP_PHY_TX2_TX3_BIST_PATTERN0           (0x2a00 + 0x00b8)
#define DP_DP_PHY_TX2_TX3_BIST_PATTERN1           (0x2a00 + 0x00bc)
#define DP_DP_PHY_MISR_CTRL                       (0x2a00 + 0x00c0)
#define DP_DP_PHY_DEBUG_BUS_SEL                   (0x2a00 + 0x00c4)
#define DP_DP_PHY_SPARE0                          (0x2a00 + 0x00c8)
#define DP_DP_PHY_SPARE1                          (0x2a00 + 0x00cc)
#define DP_DP_PHY_SPARE2                          (0x2a00 + 0x00d0)
#define DP_DP_PHY_SPARE3                          (0x2a00 + 0x00d4)
#define DP_DP_PHY_AUX_INTERRUPT_STATUS            (0x2a00 + 0x00d8)
#define DP_DP_PHY_STATUS                          (0x2a00 + 0x00dc)
#define DP_DP_PHY_AUX_BIST_STATUS0                (0x2a00 + 0x00e0)
#define DP_DP_PHY_AUX_BIST_STATUS1                (0x2a00 + 0x00e4)
#define DP_DP_PHY_AUX_BIST_STATUS2                (0x2a00 + 0x00e8)
#define DP_DP_PHY_TX0_TX1_BIST_STATUS0            (0x2a00 + 0x00ec)
#define DP_DP_PHY_TX0_TX1_BIST_STATUS1            (0x2a00 + 0x00f0)
#define DP_DP_PHY_TX0_TX1_BIST_STATUS2            (0x2a00 + 0x00f4)
#define DP_DP_PHY_TX2_TX3_BIST_STATUS0            (0x2a00 + 0x00f8)
#define DP_DP_PHY_TX2_TX3_BIST_STATUS1            (0x2a00 + 0x00fc)
#define DP_DP_PHY_TX2_TX3_BIST_STATUS2            (0x2a00 + 0x0100)
#define DP_DP_PHY_MISR_STATUS                     (0x2a00 + 0x0104)
#define DP_DP_PHY_TX0_MISR_STATUS000              (0x2a00 + 0x0108)
#define DP_DP_PHY_TX0_MISR_STATUS001              (0x2a00 + 0x010c)
#define DP_DP_PHY_TX0_MISR_STATUS010              (0x2a00 + 0x0110)
#define DP_DP_PHY_TX0_MISR_STATUS011              (0x2a00 + 0x0114)
#define DP_DP_PHY_TX0_MISR_STATUS100              (0x2a00 + 0x0118)
#define DP_DP_PHY_TX0_MISR_STATUS101              (0x2a00 + 0x011c)
#define DP_DP_PHY_TX0_MISR_STATUS110              (0x2a00 + 0x0120)
#define DP_DP_PHY_TX0_MISR_STATUS111              (0x2a00 + 0x0124)
#define DP_DP_PHY_TX1_MISR_STATUS000              (0x2a00 + 0x0128)
#define DP_DP_PHY_TX1_MISR_STATUS001              (0x2a00 + 0x012c)
#define DP_DP_PHY_TX1_MISR_STATUS010              (0x2a00 + 0x0130)
#define DP_DP_PHY_TX1_MISR_STATUS011              (0x2a00 + 0x0134)
#define DP_DP_PHY_TX1_MISR_STATUS100              (0x2a00 + 0x0138)
#define DP_DP_PHY_TX1_MISR_STATUS101              (0x2a00 + 0x013c)
#define DP_DP_PHY_TX1_MISR_STATUS110              (0x2a00 + 0x0140)
#define DP_DP_PHY_TX1_MISR_STATUS111              (0x2a00 + 0x0144)
#define DP_DP_PHY_TX2_MISR_STATUS000              (0x2a00 + 0x0148)
#define DP_DP_PHY_TX2_MISR_STATUS001              (0x2a00 + 0x014c)
#define DP_DP_PHY_TX2_MISR_STATUS010              (0x2a00 + 0x0150)
#define DP_DP_PHY_TX2_MISR_STATUS011              (0x2a00 + 0x0154)
#define DP_DP_PHY_TX2_MISR_STATUS100              (0x2a00 + 0x0158)
#define DP_DP_PHY_TX2_MISR_STATUS101              (0x2a00 + 0x015c)
#define DP_DP_PHY_TX2_MISR_STATUS110              (0x2a00 + 0x0160)
#define DP_DP_PHY_TX2_MISR_STATUS111              (0x2a00 + 0x0164)
#define DP_DP_PHY_TX3_MISR_STATUS000              (0x2a00 + 0x0168)
#define DP_DP_PHY_TX3_MISR_STATUS001              (0x2a00 + 0x016c)
#define DP_DP_PHY_TX3_MISR_STATUS010              (0x2a00 + 0x0170)
#define DP_DP_PHY_TX3_MISR_STATUS011              (0x2a00 + 0x0174)
#define DP_DP_PHY_TX3_MISR_STATUS100              (0x2a00 + 0x0178)
#define DP_DP_PHY_TX3_MISR_STATUS101              (0x2a00 + 0x017c)
#define DP_DP_PHY_TX3_MISR_STATUS110              (0x2a00 + 0x0180)
#define DP_DP_PHY_TX3_MISR_STATUS111              (0x2a00 + 0x0184)
#define DP_DP_PHY_DEBUG_BUS0                      (0x2a00 + 0x0188)
#define DP_DP_PHY_DEBUG_BUS1                      (0x2a00 + 0x018c)
#define DP_DP_PHY_DEBUG_BUS2                      (0x2a00 + 0x0190)
#define DP_DP_PHY_DEBUG_BUS3                      (0x2a00 + 0x0194)

#endif /* _DT_BINDINGS_PHY_QCOM_4LPX_QMP_COMBO_USB_H */