123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152 |
- /* SPDX-License-Identifier: GPL-2.0-only */
- /*
- * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
- */
- #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_NIOBE_H
- #define __DT_BINDINGS_INTERCONNECT_QCOM_NIOBE_H
- #define MASTER_GPU_TCU 0
- #define MASTER_SYS_TCU 1
- #define MASTER_APPSS_PROC 2
- #define MASTER_LLCC 3
- #define MASTER_DDR_RT 4
- #define MASTER_CNOC_LPASS_AG_NOC 5
- #define MASTER_GIC_AHB 6
- #define MASTER_QDSS_BAM 7
- #define MASTER_QUP_1 8
- #define MASTER_QUP_2 9
- #define MASTER_QUP_3 10
- #define MASTER_A1NOC_SNOC 11
- #define MASTER_A2NOC_SNOC 12
- #define MASTER_CAMNOC_HF 13
- #define MASTER_CAMNOC_ICP 14
- #define MASTER_CAMNOC_SF 15
- #define MASTER_CNOC_SNOC 16
- #define MASTER_GEM_NOC_CNOC 17
- #define MASTER_GEM_NOC_PCIE_SNOC 18
- #define MASTER_GFX3D 19
- #define MASTER_LPASS_GEM_NOC 20
- #define MASTER_MDP0 21
- #define MASTER_MDP1 22
- #define MASTER_MNOC_HF_MEM_NOC 23
- #define MASTER_MNOC_SF_MEM_NOC 24
- #define MASTER_CDSP_PROC 25
- #define MASTER_COMPUTE_NOC 26
- #define MASTER_ANOC_PCIE_GEM_NOC 27
- #define MASTER_SNOC_SF_MEM_NOC 28
- #define MASTER_VIDEO 29
- #define MASTER_VIDEO_CV_PROC 30
- #define MASTER_VIDEO_PROC 31
- #define MASTER_VIDEO_V_PROC 32
- #define MASTER_CNOC_CFG 33
- #define MASTER_CNOC_MNOC_HF_CFG 34
- #define MASTER_PCIE_ANOC_CFG 35
- #define MASTER_CNOC_MNOC_SF_CFG 36
- #define MASTER_QUP_CORE_1 37
- #define MASTER_QUP_CORE_2 38
- #define MASTER_QUP_CORE_3 39
- #define MASTER_CRYPTO 40
- #define MASTER_IPA 41
- #define MASTER_LPASS_PROC 42
- #define MASTER_SOCCP_AGGR_NOC 43
- #define MASTER_SP 44
- #define MASTER_GIC 45
- #define MASTER_PCIE_0 46
- #define MASTER_PCIE_2 47
- #define MASTER_PCIE_1 48
- #define MASTER_QDSS_ETR 49
- #define MASTER_QDSS_ETR_1 50
- #define MASTER_SDCC_2 51
- #define MASTER_UFS_MEM 52
- #define MASTER_USB3_0 53
- #define MASTER_USB3_1 54
- #define SLAVE_EBI1 512
- #define SLAVE_AHB2PHY_SOUTH 513
- #define SLAVE_AHB2PHY_CENTER 514
- #define SLAVE_AHB2PHY_WEST 515
- #define SLAVE_AOSS 516
- #define SLAVE_APPSS 517
- #define SLAVE_CAMERA_CFG 518
- #define SLAVE_CLK_CTL 519
- #define SLAVE_CRYPTO_0_CFG 520
- #define SLAVE_DISPLAY1_CFG 521
- #define SLAVE_DISPLAY_CFG 522
- #define SLAVE_GFX3D_CFG 523
- #define SLAVE_IMEM_CFG 524
- #define SLAVE_IPA_CFG 525
- #define SLAVE_IPC_ROUTER_CFG 526
- #define SLAVE_LPASS 527
- #define SLAVE_LPASS_CORE_CFG 528
- #define SLAVE_LPASS_LPI_CFG 529
- #define SLAVE_LPASS_MPU_CFG 530
- #define SLAVE_LPASS_TOP_CFG 531
- #define SLAVE_PCIE_0_CFG 532
- #define SLAVE_PCIE_2_CFG 533
- #define SLAVE_PCIE_1_CFG 534
- #define SLAVE_PRNG 535
- #define SLAVE_QDSS_CFG 536
- #define SLAVE_QUP_1 537
- #define SLAVE_QUP_2 538
- #define SLAVE_QUP_3 539
- #define SLAVE_SDCC_2 540
- #define SLAVE_SOCCP 541
- #define SLAVE_SPSS_CFG 542
- #define SLAVE_TCSR 543
- #define SLAVE_TLMM 544
- #define SLAVE_TME_CFG 545
- #define SLAVE_UFS_MEM_CFG 546
- #define SLAVE_USB3_0 547
- #define SLAVE_USB3_1 548
- #define SLAVE_VENUS_CFG 549
- #define SLAVE_VSENSE_CTRL_CFG 550
- #define SLAVE_A1NOC_SNOC 551
- #define SLAVE_A2NOC_SNOC 552
- #define SLAVE_GEM_NOC_CNOC 553
- #define SLAVE_SNOC_GEM_NOC_SF 554
- #define SLAVE_LLCC 555
- #define SLAVE_LPASS_GEM_NOC 556
- #define SLAVE_MNOC_HF_MEM_NOC 557
- #define SLAVE_MNOC_SF_MEM_NOC 558
- #define SLAVE_CDSP_MEM_NOC 559
- #define SLAVE_MEM_NOC_PCIE_SNOC 560
- #define SLAVE_ANOC_PCIE_GEM_NOC 561
- #define SLAVE_CNOC_CFG 562
- #define SLAVE_DDRSS_CFG 563
- #define SLAVE_CNOC_MNOC_HF_CFG 564
- #define SLAVE_CNOC_MNOC_SF_CFG 565
- #define SLAVE_PCIE_ANOC_CFG 566
- #define SLAVE_QUP_CORE_1 567
- #define SLAVE_QUP_CORE_2 568
- #define SLAVE_QUP_CORE_3 569
- #define SLAVE_BOOT_IMEM 570
- #define SLAVE_BOOT_IMEM_2 571
- #define SLAVE_IMEM 572
- #define SLAVE_DDR_RT 573
- #define SLAVE_SERVICE_CNOC 574
- #define SLAVE_SERVICE_MNOC_HF 575
- #define SLAVE_SERVICE_MNOC_SF 576
- #define SLAVE_SERVICES_LPASS_AML_NOC 577
- #define SLAVE_SERVICE_LPASS_AG_NOC 578
- #define SLAVE_SERVICE_PCIE_ANOC 579
- #define SLAVE_PCIE_0 580
- #define SLAVE_PCIE_2 581
- #define SLAVE_PCIE_1 582
- #define SLAVE_QDSS_STM 583
- #define SLAVE_TCU 584
- #define MASTER_LLCC_DISP 1000
- #define MASTER_MDP0_DISP 1001
- #define MASTER_MNOC_HF_MEM_NOC_DISP 1002
- #define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
- #define SLAVE_EBI1_DISP 1512
- #define SLAVE_LLCC_DISP 1513
- #define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
- #define MASTER_LLCC_DISP2 2000
- #define MASTER_MDP1_DISP2 2001
- #define MASTER_MNOC_HF_MEM_NOC_DISP2 2002
- #define MASTER_ANOC_PCIE_GEM_NOC_DISP2 2003
- #define SLAVE_EBI1_DISP2 2512
- #define SLAVE_LLCC_DISP2 2513
- #define SLAVE_MNOC_HF_MEM_NOC_DISP2 2514
- #endif
|