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qcom,spmi-adc5-gen3-pmx75.h

qcom,spmi-adc5-gen3-pmx75.h 2.1 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H
    7. 

  7. #define _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H
    8. 

  8. 

  9. #ifndef PMX75_SID
    10. 

  10. #define PMX75_SID       1
    11. 

  11. #endif
    12. 

  12. 

  13. /* ADC channels for PMX75_ADC for PMIC5 Gen3 */
    14. 

  14. #define PMX75_ADC5_GEN3_OFFSET_REF		(PMX75_SID << 8 | 0x00)
    15. 

  15. #define PMX75_ADC5_GEN3_1P25VREF		(PMX75_SID << 8 | 0X01)
    16. 

  16. #define PMX75_ADC5_GEN3_VREF_VADC		(PMX75_SID << 8 | 0x02)
    17. 

  17. #define PMX75_ADC5_GEN3_DIE_TEMP		(PMX75_SID << 8 | 0x03)
    18. 

  18. 

  19. #define PMX75_ADC5_GEN3_AMUX_THM1		(PMX75_SID << 8 | 0x04)
    20. 

  20. #define PMX75_ADC5_GEN3_AMUX_THM2		(PMX75_SID << 8 | 0x05)
    21. 

  21. #define PMX75_ADC5_GEN3_AMUX_THM3		(PMX75_SID << 8 | 0x06)
    22. 

  22. #define PMX75_ADC5_GEN3_AMUX_THM4		(PMX75_SID << 8 | 0x07)
    23. 

  23. #define PMX75_ADC5_GEN3_AMUX_THM5		(PMX75_SID << 8 | 0x08)
    24. 

  24. #define PMX75_ADC5_GEN3_AMUX_THM6		(PMX75_SID << 8 | 0x09)
    25. 

  25. #define PMX75_ADC5_GEN3_AMUX1_GPIO5		(PMX75_SID << 8 | 0x0a)
    26. 

  26. #define PMX75_ADC5_GEN3_AMUX2_GPIO12		(PMX75_SID << 8 | 0x0b)
    27. 

  27. #define PMX75_ADC5_GEN3_AMUX3_GPIO15		(PMX75_SID << 8 | 0x0c)
    28. 

  28. #define PMX75_ADC5_GEN3_AMUX4_GPIO1		(PMX75_SID << 8 | 0x0d)
    29. 

  29. 

  30. /* 100K pull-up */
    31. 

  31. #define PMX75_ADC5_GEN3_AMUX_THM1_100K_PU	(PMX75_SID << 8 | 0x44)
    32. 

  32. #define PMX75_ADC5_GEN3_AMUX_THM2_100K_PU	(PMX75_SID << 8 | 0x45)
    33. 

  33. #define PMX75_ADC5_GEN3_AMUX_THM3_100K_PU	(PMX75_SID << 8 | 0x46)
    34. 

  34. #define PMX75_ADC5_GEN3_AMUX_THM4_100K_PU	(PMX75_SID << 8 | 0x47)
    35. 

  35. #define PMX75_ADC5_GEN3_AMUX_THM5_100K_PU	(PMX75_SID << 8 | 0x48)
    36. 

  36. #define PMX75_ADC5_GEN3_AMUX_THM6_100K_PU	(PMX75_SID << 8 | 0x49)
    37. 

  37. #define PMX75_ADC5_GEN3_AMUX1_GPIO5_100K_PU	(PMX75_SID << 8 | 0x4a)
    38. 

  38. #define PMX75_ADC5_GEN3_AMUX2_GPIO12_100K_PU	(PMX75_SID << 8 | 0x4b)
    39. 

  39. #define PMX75_ADC5_GEN3_AMUX3_GPIO15_100K_PU	(PMX75_SID << 8 | 0x4c)
    40. 

  40. #define PMX75_ADC5_GEN3_AMUX4_GPIO1_100K_PU	(PMX75_SID << 8 | 0x4d)
    41. 

  41. 

  42. /* 1/3 Divider */
    43. 

  43. #define PMX75_ADC5_GEN3_AMUX2_GPIO12_DIV3	(PMX75_SID << 8 | 0x8b)
    44. 

  44. #define PMX75_ADC5_GEN3_AMUX3_GPIO15_DIV3	(PMX75_SID << 8 | 0x8c)
    45. 

  45. 

  46. #define PMX75_ADC5_GEN3_VPH_PWR		(PMX75_SID << 8 | 0x8e)
    47. 

  47. 

  48. #endif /* __DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H */
    49.