123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354 |
- /* SPDX-License-Identifier: GPL-2.0-only */
- /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
- */
- #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
- #define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
- #ifndef PMK8550_SID
- #define PMK8550_SID 0
- #endif
- /* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
- #define PMK8550_ADC5_GEN3_OFFSET_REF (PMK8550_SID << 8 | 0x00)
- #define PMK8550_ADC5_GEN3_1P25VREF (PMK8550_SID << 8 | 0x01)
- #define PMK8550_ADC5_GEN3_VREF_VADC (PMK8550_SID << 8 | 0x02)
- #define PMK8550_ADC5_GEN3_DIE_TEMP (PMK8550_SID << 8 | 0x03)
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM (PMK8550_SID << 8 | 0x04)
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1 (PMK8550_SID << 8 | 0x05)
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2 (PMK8550_SID << 8 | 0x06)
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3 (PMK8550_SID << 8 | 0x07)
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4 (PMK8550_SID << 8 | 0x08)
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5 (PMK8550_SID << 8 | 0x09)
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6 (PMK8550_SID << 8 | 0x0a)
- /* 30k pull-up */
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU (PMK8550_SID << 8 | 0x24)
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU (PMK8550_SID << 8 | 0x25)
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU (PMK8550_SID << 8 | 0x26)
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU (PMK8550_SID << 8 | 0x27)
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU (PMK8550_SID << 8 | 0x28)
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU (PMK8550_SID << 8 | 0x29)
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU (PMK8550_SID << 8 | 0x2a)
- /* 100k pull-up */
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU (PMK8550_SID << 8 | 0x44)
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU (PMK8550_SID << 8 | 0x45)
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU (PMK8550_SID << 8 | 0x46)
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU (PMK8550_SID << 8 | 0x47)
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU (PMK8550_SID << 8 | 0x48)
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU (PMK8550_SID << 8 | 0x49)
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU (PMK8550_SID << 8 | 0x4a)
- /* 400k pull-up */
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU (PMK8550_SID << 8 | 0x64)
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU (PMK8550_SID << 8 | 0x65)
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU (PMK8550_SID << 8 | 0x66)
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU (PMK8550_SID << 8 | 0x67)
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU (PMK8550_SID << 8 | 0x68)
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU (PMK8550_SID << 8 | 0x69)
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU (PMK8550_SID << 8 | 0x6a)
- #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
|