123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354 |
- #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
- #define _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H
- #ifndef PMK8550_SID
- #define PMK8550_SID 0
- #endif
- /* ADC channels for PMK8550_ADC for PMIC5 Gen3 */
- #define PMK8550_ADC5_GEN3_OFFSET_REF
- #define PMK8550_ADC5_GEN3_1P25VREF
- #define PMK8550_ADC5_GEN3_VREF_VADC
- #define PMK8550_ADC5_GEN3_DIE_TEMP
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_30K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_100K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM1_XO_THERM_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM2_GPIO1_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM3_GPIO2_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM4_GPIO3_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM5_GPIO4_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX_THM6_GPIO5_400K_PU
- #define PMK8550_ADC5_GEN3_AMUX1_GPIO6_400K_PU
- #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8550_H */
|