samsung-sm8650
/
android_kernel_samsung_sm8650_ksu


			
				
					
						
						
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							/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H

#ifndef PMIV0104_SID
#define PMIV0104_SID		7
#endif

/* ADC channels for PMIV0104_ADC for PMIC5 Gen3 */
#define PMIV0104_ADC5_GEN3_OFFSET_REF			(PMIV0104_SID << 8 | 0x00)
#define PMIV0104_ADC5_GEN3_1P25VREF			(PMIV0104_SID << 8 | 0x01)
#define PMIV0104_ADC5_GEN3_VREF_VADC			(PMIV0104_SID << 8 | 0x02)
#define PMIV0104_ADC5_GEN3_DIE_TEMP			(PMIV0104_SID << 8 | 0x03)

#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM		(PMIV0104_SID << 8 | 0x04)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID		(PMIV0104_SID << 8 | 0x05)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V		(PMIV0104_SID << 8 | 0x06)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM		(PMIV0104_SID << 8 | 0x07)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION		(PMIV0104_SID << 8 | 0x08)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6		(PMIV0104_SID << 8 | 0x09)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1			(PMIV0104_SID << 8 | 0x0a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2			(PMIV0104_SID << 8 | 0x0b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7			(PMIV0104_SID << 8 | 0x0c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8			(PMIV0104_SID << 8 | 0x0d)

#define PMIV0104_ADC5_GEN3_CHG_TEMP			(PMIV0104_SID << 8 | 0x10)
#define PMIV0104_ADC5_GEN3_USB_SNS_V_16			(PMIV0104_SID << 8 | 0x11)
#define PMIV0104_ADC5_GEN3_VIN_DIV16_MUX		(PMIV0104_SID << 8 | 0x12)
#define PMIV0104_ADC5_GEN3_USBC_MUX			(PMIV0104_SID << 8 | 0x13)
#define PMIV0104_ADC5_GEN3_VREF_BAT_THERM		(PMIV0104_SID << 8 | 0x15)
#define PMIV0104_ADC5_GEN3_IIN_FB			(PMIV0104_SID << 8 | 0x17)
#define PMIV0104_ADC5_GEN3_SMB_IIN			(PMIV0104_SID << 8 | 0x19)
#define PMIV0104_ADC5_GEN3_SMB_ICHG			(PMIV0104_SID << 8 | 0x1b)
#define PMIV0104_ADC5_GEN3_SMB_TEMP_I			(PMIV0104_SID << 8 | 0x1e)
#define PMIV0104_ADC5_GEN3_CHG_TEMP_I			(PMIV0104_SID << 8 | 0x1f)
#define PMIV0104_ADC5_GEN3_ICHG_FB			(PMIV0104_SID << 8 | 0xa1)

/* 30k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU	(PMIV0104_SID << 8 | 0x24)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU	(PMIV0104_SID << 8 | 0x25)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU	(PMIV0104_SID << 8 | 0x26)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU	(PMIV0104_SID << 8 | 0x27)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU	(PMIV0104_SID << 8 | 0x28)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_30K_PU	(PMIV0104_SID << 8 | 0x29)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_30K_PU		(PMIV0104_SID << 8 | 0x2a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_30K_PU		(PMIV0104_SID << 8 | 0x2b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_30K_PU		(PMIV0104_SID << 8 | 0x2c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_30K_PU		(PMIV0104_SID << 8 | 0x2d)

#define PMIV0104_ADC5_GEN3_USBC_MUX_30K_PU		(PMIV0104_SID << 8 | 0x33)

/* 100k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU	(PMIV0104_SID << 8 | 0x44)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU	(PMIV0104_SID << 8 | 0x45)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU	(PMIV0104_SID << 8 | 0x46)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU	(PMIV0104_SID << 8 | 0x47)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU	(PMIV0104_SID << 8 | 0x48)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU	(PMIV0104_SID << 8 | 0x49)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_100K_PU		(PMIV0104_SID << 8 | 0x4a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_100K_PU		(PMIV0104_SID << 8 | 0x4b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_100K_PU		(PMIV0104_SID << 8 | 0x4c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_100K_PU		(PMIV0104_SID << 8 | 0x4d)

#define PMIV0104_ADC5_GEN3_USBC_MUX_100K_PU		(PMIV0104_SID << 8 | 0x53)

/* 400k pull-up */
#define PMIV0104_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU	(PMIV0104_SID << 8 | 0x64)
#define PMIV0104_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU	(PMIV0104_SID << 8 | 0x65)
#define PMIV0104_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU	(PMIV0104_SID << 8 | 0x66)
#define PMIV0104_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU	(PMIV0104_SID << 8 | 0x67)
#define PMIV0104_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU	(PMIV0104_SID << 8 | 0x68)
#define PMIV0104_ADC5_GEN3_AMUX_THM6_GPIO6_400K_PU	(PMIV0104_SID << 8 | 0x69)
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_400K_PU		(PMIV0104_SID << 8 | 0x6a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_400K_PU		(PMIV0104_SID << 8 | 0x6b)
#define PMIV0104_ADC5_GEN3_AMUX3_GPIO7_400K_PU		(PMIV0104_SID << 8 | 0x6c)
#define PMIV0104_ADC5_GEN3_AMUX4_GPIO8_400K_PU		(PMIV0104_SID << 8 | 0x6d)

#define PMIV0104_ADC5_GEN3_USBC_MUX_400K_PU		(PMIV0104_SID << 8 | 0x73)

/* 1/3 Divider */
#define PMIV0104_ADC5_GEN3_AMUX1_GPIO1_DIV3		(PMIV0104_SID << 8 | 0x8a)
#define PMIV0104_ADC5_GEN3_AMUX2_GPIO2_DIV3		(PMIV0104_SID << 8 | 0x8b)

#define PMIV0104_ADC5_GEN3_VPH_PWR			(PMIV0104_SID << 8 | 0x8e)
#define PMIV0104_ADC5_GEN3_VBAT_SNS_QBG			(PMIV0104_SID << 8 | 0x8f)
#define PMIV0104_ADC5_GEN3_VBAT_SNS_CHGR		(PMIV0104_SID << 8 | 0x94)

#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMIV0104_H */