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qcom,spmi-adc5-gen3-pm8550b.h

qcom,spmi-adc5-gen3-pm8550b.h 6.8 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
    7. 

  7. #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
    8. 

  8. 

  9. #ifndef PM8550B_SID
    10. 

  10. #define PM8550B_SID		7
    11. 

  11. #endif
    12. 

  12. 

  13. #ifndef PM8550B_I_SID
    14. 

  14. #define PM8550B_I_SID		8
    15. 

  15. #endif
    16. 

  16. 

  17. /* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
    18. 

  18. #define PM8550B_ADC5_GEN3_OFFSET_REF			(PM8550B_SID << 8 | 0x00)
    19. 

  19. #define PM8550B_ADC5_GEN3_1P25VREF			(PM8550B_SID << 8 | 0x01)
    20. 

  20. #define PM8550B_ADC5_GEN3_VREF_VADC			(PM8550B_SID << 8 | 0x02)
    21. 

  21. #define PM8550B_ADC5_GEN3_DIE_TEMP			(PM8550B_SID << 8 | 0x03)
    22. 

  22. 

  23. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM		(PM8550B_SID << 8 | 0x04)
    24. 

  24. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID		(PM8550B_SID << 8 | 0x05)
    25. 

  25. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V		(PM8550B_SID << 8 | 0x06)
    26. 

  26. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM		(PM8550B_SID << 8 | 0x07)
    27. 

  27. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION		(PM8550B_SID << 8 | 0x08)
    28. 

  28. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10		(PM8550B_SID << 8 | 0x09)
    29. 

  29. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1			(PM8550B_SID << 8 | 0x0a)
    30. 

  30. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5			(PM8550B_SID << 8 | 0x0b)
    31. 

  31. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6			(PM8550B_SID << 8 | 0x0c)
    32. 

  32. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12			(PM8550B_SID << 8 | 0x0d)
    33. 

  33. 

  34. #define PM8550B_ADC5_GEN3_CHG_TEMP			(PM8550B_SID << 8 | 0x10)
    35. 

  35. #define PM8550B_ADC5_GEN3_USB_SNS_V_16			(PM8550B_SID << 8 | 0x11)
    36. 

  36. #define PM8550B_ADC5_GEN3_VIN_DIV16_MUX			(PM8550B_SID << 8 | 0x12)
    37. 

  37. #define PM8550B_ADC5_GEN3_USBC_MUX			(PM8550B_SID << 8 | 0x13)
    38. 

  38. #define PM8550B_ADC5_GEN3_VREF_BAT_THERM		(PM8550B_SID << 8 | 0x15)
    39. 

  39. #define PM8550B_ADC5_GEN3_IIN_FB			(PM8550B_SID << 8 | 0x17)
    40. 

  40. #define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE		(PM8550B_SID << 8 | 0x18)
    41. 

  41. #define PM8550B_ADC5_GEN3_SMB_IIN			(PM8550B_SID << 8 | 0x19)
    42. 

  42. #define PM8550B_ADC5_GEN3_VREF_BAT2_THERM		(PM8550B_SID << 8 | 0x1a)
    43. 

  43. #define PM8550B_ADC5_GEN3_SMB_ICHG			(PM8550B_SID << 8 | 0x1b)
    44. 

  44. #define PM8550B_ADC5_GEN3_SMB_TEMP_I			(PM8550B_SID << 8 | 0x1e)
    45. 

  45. #define PM8550B_ADC5_GEN3_CHG_TEMP_I			(PM8550B_SID << 8 | 0x1f)
    46. 

  46. #define PM8550B_ADC5_GEN3_ICHG_FB			(PM8550B_SID << 8 | 0xa1)
    47. 

  47. 

  48. /* 30k pull-up */
    49. 

  49. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU	(PM8550B_SID << 8 | 0x24)
    50. 

  50. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU	(PM8550B_SID << 8 | 0x25)
    51. 

  51. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU	(PM8550B_SID << 8 | 0x26)
    52. 

  52. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU	(PM8550B_SID << 8 | 0x27)
    53. 

  53. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU	(PM8550B_SID << 8 | 0x28)
    54. 

  54. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU	(PM8550B_SID << 8 | 0x29)
    55. 

  55. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU		(PM8550B_SID << 8 | 0x2a)
    56. 

  56. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU		(PM8550B_SID << 8 | 0x2b)
    57. 

  57. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU		(PM8550B_SID << 8 | 0x2c)
    58. 

  58. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU		(PM8550B_SID << 8 | 0x2d)
    59. 

  59. 

  60. #define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU		(PM8550B_SID << 8 | 0x33)
    61. 

  61. 

  62. /* 100k pull-up */
    63. 

  63. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU	(PM8550B_SID << 8 | 0x44)
    64. 

  64. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU	(PM8550B_SID << 8 | 0x45)
    65. 

  65. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU	(PM8550B_SID << 8 | 0x46)
    66. 

  66. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU	(PM8550B_SID << 8 | 0x47)
    67. 

  67. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU	(PM8550B_SID << 8 | 0x48)
    68. 

  68. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU	(PM8550B_SID << 8 | 0x49)
    69. 

  69. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU		(PM8550B_SID << 8 | 0x4a)
    70. 

  70. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU		(PM8550B_SID << 8 | 0x4b)
    71. 

  71. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU		(PM8550B_SID << 8 | 0x4c)
    72. 

  72. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8550B_SID << 8 | 0x4d)
    73. 

  73. 

  74. #define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU		(PM8550B_SID << 8 | 0x53)
    75. 

  75. 

  76. /* 400k pull-up */
    77. 

  77. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU	(PM8550B_SID << 8 | 0x64)
    78. 

  78. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU	(PM8550B_SID << 8 | 0x65)
    79. 

  79. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU	(PM8550B_SID << 8 | 0x66)
    80. 

  80. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU	(PM8550B_SID << 8 | 0x67)
    81. 

  81. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU	(PM8550B_SID << 8 | 0x68)
    82. 

  82. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU	(PM8550B_SID << 8 | 0x69)
    83. 

  83. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU		(PM8550B_SID << 8 | 0x6a)
    84. 

  84. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU		(PM8550B_SID << 8 | 0x6b)
    85. 

  85. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU		(PM8550B_SID << 8 | 0x6c)
    86. 

  86. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU		(PM8550B_SID << 8 | 0x6d)
    87. 

  87. 

  88. #define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU		(PM8550B_SID << 8 | 0x73)
    89. 

  89. 

  90. /* 1/3 Divider */
    91. 

  91. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3		(PM8550B_SID << 8 | 0x8a)
    92. 

  92. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3		(PM8550B_SID << 8 | 0x8b)
    93. 

  93. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3		(PM8550B_SID << 8 | 0x8c)
    94. 

  94. 

  95. #define PM8550B_ADC5_GEN3_VPH_PWR			(PM8550B_SID << 8 | 0x8e)
    96. 

  96. #define PM8550B_ADC5_GEN3_VBAT_SNS_QBG			(PM8550B_SID << 8 | 0x8f)
    97. 

  97. #define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR			(PM8550B_SID << 8 | 0x94)
    98. 

  98. #define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG		(PM8550B_SID << 8 | 0x96)
    99. 

  99. #define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR		(PM8550B_SID << 8 | 0x9d)
    100. 

  100. 

  101. /* Channels for second instance of PM8550B */
    102. 

  102. #define PM8550B_I_ADC5_GEN3_OFFSET_REF			(PM8550B_I_SID << 8 | 0x00)
    103. 

  103. #define PM8550B_I_ADC5_GEN3_1P25VREF			(PM8550B_I_SID << 8 | 0x01)
    104. 

  104. #define PM8550B_I_ADC5_GEN3_VREF_VADC			(PM8550B_I_SID << 8 | 0x02)
    105. 

  105. #define PM8550B_I_ADC5_GEN3_DIE_TEMP			(PM8550B_I_SID << 8 | 0x03)
    106. 

  106. #define PM8550B_I_ADC5_GEN3_TEMP_ALARM_LITE		(PM8550B_I_SID << 8 | 0x18)
    107. 

  107. 

  108. #define PM8550B_I_ADC5_GEN3_CHG_TEMP			(PM8550B_I_SID << 8 | 0x10)
    109. 

  109. #define PM8550B_I_ADC5_GEN3_IIN_FB			(PM8550B_I_SID << 8 | 0x17)
    110. 

  110. #define PM8550B_I_ADC5_GEN3_ICHG_FB			(PM8550B_I_SID << 8 | 0xa1)
    111. 

  111. 

  112. /* 100k pull-up */
    113. 

  113. #define PM8550B_I_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU	(PM8550B_I_SID << 8 | 0x44)
    114. 

  114. #define PM8550B_I_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU		(PM8550B_I_SID << 8 | 0x45)
    115. 

  115. #define PM8550B_I_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU	(PM8550B_I_SID << 8 | 0x46)
    116. 

  116. #define PM8550B_I_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU		(PM8550B_I_SID << 8 | 0x47)
    117. 

  117. #define PM8550B_I_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU		(PM8550B_I_SID << 8 | 0x48)
    118. 

  118. #define PM8550B_I_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU		(PM8550B_I_SID << 8 | 0x49)
    119. 

  119. #define PM8550B_I_ADC5_GEN3_AMUX1_GPIO1_100K_PU			(PM8550B_I_SID << 8 | 0x4a)
    120. 

  120. #define PM8550B_I_ADC5_GEN3_AMUX2_GPIO5_100K_PU			(PM8550B_I_SID << 8 | 0x4b)
    121. 

  121. #define PM8550B_I_ADC5_GEN3_AMUX3_GPIO6_100K_PU			(PM8550B_I_SID << 8 | 0x4c)
    122. 

  122. #define PM8550B_I_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8550B_I_SID << 8 | 0x4d)
    123. 

  123. 

  124. #define PM8550B_I_ADC5_GEN3_VPH_PWR			(PM8550B_I_SID << 8 | 0x8e)
    125. 

  125. #define PM8550B_I_ADC5_GEN3_VBAT_SNS_QBG		(PM8550B_I_SID << 8 | 0x8f)
    126. 

  126. 

  127. #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */
    128.