qcom,spmi-adc5-gen3-pm8550b.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
  6. #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H
  7. #ifndef PM8550B_SID
  8. #define PM8550B_SID 7
  9. #endif
  10. #ifndef PM8550B_I_SID
  11. #define PM8550B_I_SID 8
  12. #endif
  13. /* ADC channels for PM8550B_ADC for PMIC5 Gen3 */
  14. #define PM8550B_ADC5_GEN3_OFFSET_REF (PM8550B_SID << 8 | 0x00)
  15. #define PM8550B_ADC5_GEN3_1P25VREF (PM8550B_SID << 8 | 0x01)
  16. #define PM8550B_ADC5_GEN3_VREF_VADC (PM8550B_SID << 8 | 0x02)
  17. #define PM8550B_ADC5_GEN3_DIE_TEMP (PM8550B_SID << 8 | 0x03)
  18. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM (PM8550B_SID << 8 | 0x04)
  19. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID (PM8550B_SID << 8 | 0x05)
  20. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V (PM8550B_SID << 8 | 0x06)
  21. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM (PM8550B_SID << 8 | 0x07)
  22. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION (PM8550B_SID << 8 | 0x08)
  23. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10 (PM8550B_SID << 8 | 0x09)
  24. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1 (PM8550B_SID << 8 | 0x0a)
  25. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5 (PM8550B_SID << 8 | 0x0b)
  26. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6 (PM8550B_SID << 8 | 0x0c)
  27. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12 (PM8550B_SID << 8 | 0x0d)
  28. #define PM8550B_ADC5_GEN3_CHG_TEMP (PM8550B_SID << 8 | 0x10)
  29. #define PM8550B_ADC5_GEN3_USB_SNS_V_16 (PM8550B_SID << 8 | 0x11)
  30. #define PM8550B_ADC5_GEN3_VIN_DIV16_MUX (PM8550B_SID << 8 | 0x12)
  31. #define PM8550B_ADC5_GEN3_USBC_MUX (PM8550B_SID << 8 | 0x13)
  32. #define PM8550B_ADC5_GEN3_VREF_BAT_THERM (PM8550B_SID << 8 | 0x15)
  33. #define PM8550B_ADC5_GEN3_IIN_FB (PM8550B_SID << 8 | 0x17)
  34. #define PM8550B_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_SID << 8 | 0x18)
  35. #define PM8550B_ADC5_GEN3_SMB_IIN (PM8550B_SID << 8 | 0x19)
  36. #define PM8550B_ADC5_GEN3_VREF_BAT2_THERM (PM8550B_SID << 8 | 0x1a)
  37. #define PM8550B_ADC5_GEN3_SMB_ICHG (PM8550B_SID << 8 | 0x1b)
  38. #define PM8550B_ADC5_GEN3_SMB_TEMP_I (PM8550B_SID << 8 | 0x1e)
  39. #define PM8550B_ADC5_GEN3_CHG_TEMP_I (PM8550B_SID << 8 | 0x1f)
  40. #define PM8550B_ADC5_GEN3_ICHG_FB (PM8550B_SID << 8 | 0xa1)
  41. /* 30k pull-up */
  42. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU (PM8550B_SID << 8 | 0x24)
  43. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU (PM8550B_SID << 8 | 0x25)
  44. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU (PM8550B_SID << 8 | 0x26)
  45. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU (PM8550B_SID << 8 | 0x27)
  46. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU (PM8550B_SID << 8 | 0x28)
  47. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_30K_PU (PM8550B_SID << 8 | 0x29)
  48. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_30K_PU (PM8550B_SID << 8 | 0x2a)
  49. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PM8550B_SID << 8 | 0x2b)
  50. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PM8550B_SID << 8 | 0x2c)
  51. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_30K_PU (PM8550B_SID << 8 | 0x2d)
  52. #define PM8550B_ADC5_GEN3_USBC_MUX_30K_PU (PM8550B_SID << 8 | 0x33)
  53. /* 100k pull-up */
  54. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_SID << 8 | 0x44)
  55. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_SID << 8 | 0x45)
  56. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_SID << 8 | 0x46)
  57. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_SID << 8 | 0x47)
  58. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_SID << 8 | 0x48)
  59. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_SID << 8 | 0x49)
  60. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_SID << 8 | 0x4a)
  61. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_SID << 8 | 0x4b)
  62. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_SID << 8 | 0x4c)
  63. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_SID << 8 | 0x4d)
  64. #define PM8550B_ADC5_GEN3_USBC_MUX_100K_PU (PM8550B_SID << 8 | 0x53)
  65. /* 400k pull-up */
  66. #define PM8550B_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU (PM8550B_SID << 8 | 0x64)
  67. #define PM8550B_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU (PM8550B_SID << 8 | 0x65)
  68. #define PM8550B_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU (PM8550B_SID << 8 | 0x66)
  69. #define PM8550B_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU (PM8550B_SID << 8 | 0x67)
  70. #define PM8550B_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU (PM8550B_SID << 8 | 0x68)
  71. #define PM8550B_ADC5_GEN3_AMUX_THM6_GPIO10_400K_PU (PM8550B_SID << 8 | 0x69)
  72. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_400K_PU (PM8550B_SID << 8 | 0x6a)
  73. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PM8550B_SID << 8 | 0x6b)
  74. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PM8550B_SID << 8 | 0x6c)
  75. #define PM8550B_ADC5_GEN3_AMUX4_GPIO12_400K_PU (PM8550B_SID << 8 | 0x6d)
  76. #define PM8550B_ADC5_GEN3_USBC_MUX_400K_PU (PM8550B_SID << 8 | 0x73)
  77. /* 1/3 Divider */
  78. #define PM8550B_ADC5_GEN3_AMUX1_GPIO1_DIV3 (PM8550B_SID << 8 | 0x8a)
  79. #define PM8550B_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PM8550B_SID << 8 | 0x8b)
  80. #define PM8550B_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PM8550B_SID << 8 | 0x8c)
  81. #define PM8550B_ADC5_GEN3_VPH_PWR (PM8550B_SID << 8 | 0x8e)
  82. #define PM8550B_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_SID << 8 | 0x8f)
  83. #define PM8550B_ADC5_GEN3_VBAT_SNS_CHGR (PM8550B_SID << 8 | 0x94)
  84. #define PM8550B_ADC5_GEN3_VBAT_2S_MID_QBG (PM8550B_SID << 8 | 0x96)
  85. #define PM8550B_ADC5_GEN3_VBAT_2S_MID_CHGR (PM8550B_SID << 8 | 0x9d)
  86. /* Channels for second instance of PM8550B */
  87. #define PM8550B_I_ADC5_GEN3_OFFSET_REF (PM8550B_I_SID << 8 | 0x00)
  88. #define PM8550B_I_ADC5_GEN3_1P25VREF (PM8550B_I_SID << 8 | 0x01)
  89. #define PM8550B_I_ADC5_GEN3_VREF_VADC (PM8550B_I_SID << 8 | 0x02)
  90. #define PM8550B_I_ADC5_GEN3_DIE_TEMP (PM8550B_I_SID << 8 | 0x03)
  91. #define PM8550B_I_ADC5_GEN3_TEMP_ALARM_LITE (PM8550B_I_SID << 8 | 0x18)
  92. #define PM8550B_I_ADC5_GEN3_CHG_TEMP (PM8550B_I_SID << 8 | 0x10)
  93. #define PM8550B_I_ADC5_GEN3_IIN_FB (PM8550B_I_SID << 8 | 0x17)
  94. #define PM8550B_I_ADC5_GEN3_ICHG_FB (PM8550B_I_SID << 8 | 0xa1)
  95. /* 100k pull-up */
  96. #define PM8550B_I_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU (PM8550B_I_SID << 8 | 0x44)
  97. #define PM8550B_I_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU (PM8550B_I_SID << 8 | 0x45)
  98. #define PM8550B_I_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_100K_PU (PM8550B_I_SID << 8 | 0x46)
  99. #define PM8550B_I_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU (PM8550B_I_SID << 8 | 0x47)
  100. #define PM8550B_I_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU (PM8550B_I_SID << 8 | 0x48)
  101. #define PM8550B_I_ADC5_GEN3_AMUX_THM6_GPIO10_100K_PU (PM8550B_I_SID << 8 | 0x49)
  102. #define PM8550B_I_ADC5_GEN3_AMUX1_GPIO1_100K_PU (PM8550B_I_SID << 8 | 0x4a)
  103. #define PM8550B_I_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PM8550B_I_SID << 8 | 0x4b)
  104. #define PM8550B_I_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PM8550B_I_SID << 8 | 0x4c)
  105. #define PM8550B_I_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8550B_I_SID << 8 | 0x4d)
  106. #define PM8550B_I_ADC5_GEN3_VPH_PWR (PM8550B_I_SID << 8 | 0x8e)
  107. #define PM8550B_I_ADC5_GEN3_VBAT_SNS_QBG (PM8550B_I_SID << 8 | 0x8f)
  108. #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550B_H */