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dt-bindings
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iio
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qcom,spmi-adc5-gen3-pm8550.h

qcom,spmi-adc5-gen3-pm8550.h 2.1 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
    7. 

  7. #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H
    8. 

  8. 

  9. #ifndef PM8550_SID
    10. 

  10. #define PM8550_SID		1
    11. 

  11. #endif
    12. 

  12. 

  13. /* ADC channels for PM8550_ADC for PMIC5 Gen3 */
    14. 

  14. #define PM8550_ADC5_GEN3_OFFSET_REF			(PM8550_SID << 8 | 0x00)
    15. 

  15. #define PM8550_ADC5_GEN3_1P25VREF			(PM8550_SID << 8 | 0x01)
    16. 

  16. #define PM8550_ADC5_GEN3_VREF_VADC			(PM8550_SID << 8 | 0x02)
    17. 

  17. #define PM8550_ADC5_GEN3_DIE_TEMP			(PM8550_SID << 8 | 0x03)
    18. 

  18. 

  19. #define PM8550_ADC5_GEN3_AMUX_THM1			(PM8550_SID << 8 | 0x04)
    20. 

  20. #define PM8550_ADC5_GEN3_AMUX_THM2			(PM8550_SID << 8 | 0x05)
    21. 

  21. #define PM8550_ADC5_GEN3_AMUX_THM3			(PM8550_SID << 8 | 0x06)
    22. 

  22. #define PM8550_ADC5_GEN3_AMUX_THM4			(PM8550_SID << 8 | 0x07)
    23. 

  23. #define PM8550_ADC5_GEN3_AMUX_THM5			(PM8550_SID << 8 | 0x08)
    24. 

  24. #define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2		(PM8550_SID << 8 | 0x09)
    25. 

  25. #define PM8550_ADC5_GEN3_AMUX1_GPIO3			(PM8550_SID << 8 | 0x0a)
    26. 

  26. #define PM8550_ADC5_GEN3_AMUX2_GPIO4			(PM8550_SID << 8 | 0x0b)
    27. 

  27. #define PM8550_ADC5_GEN3_AMUX3_GPIO7			(PM8550_SID << 8 | 0x0c)
    28. 

  28. #define PM8550_ADC5_GEN3_AMUX4_GPIO12			(PM8550_SID << 8 | 0x0d)
    29. 

  29. 

  30. /* 100k pull-up */
    31. 

  31. #define PM8550_ADC5_GEN3_AMUX_THM1_100K_PU		(PM8550_SID << 8 | 0x44)
    32. 

  32. #define PM8550_ADC5_GEN3_AMUX_THM2_100K_PU		(PM8550_SID << 8 | 0x45)
    33. 

  33. #define PM8550_ADC5_GEN3_AMUX_THM3_100K_PU		(PM8550_SID << 8 | 0x46)
    34. 

  34. #define PM8550_ADC5_GEN3_AMUX_THM4_100K_PU		(PM8550_SID << 8 | 0x47)
    35. 

  35. #define PM8550_ADC5_GEN3_AMUX_THM5_100K_PU		(PM8550_SID << 8 | 0x48)
    36. 

  36. #define PM8550_ADC5_GEN3_AMUX_THM6_GPIO2_100K_PU	(PM8550_SID << 8 | 0x49)
    37. 

  37. #define PM8550_ADC5_GEN3_AMUX1_GPIO3_100K_PU		(PM8550_SID << 8 | 0x4a)
    38. 

  38. #define PM8550_ADC5_GEN3_AMUX2_GPIO4_100K_PU		(PM8550_SID << 8 | 0x4b)
    39. 

  39. #define PM8550_ADC5_GEN3_AMUX3_GPIO7_100K_PU		(PM8550_SID << 8 | 0x4c)
    40. 

  40. #define PM8550_ADC5_GEN3_AMUX4_GPIO12_100K_PU		(PM8550_SID << 8 | 0x4d)
    41. 

  41. 

  42. /* 1/3 Divider */
    43. 

  43. #define PM8550_ADC5_GEN3_AMUX3_GPIO7_DIV3		(PM8550_SID << 8 | 0x8c)
    44. 

  44. #define PM8550_ADC5_GEN3_AMUX4_GPIO12_DIV3		(PM8550_SID << 8 | 0x8d)
    45. 

  45. 

  46. #define PM8550_ADC5_GEN3_VPH_PWR			(PM8550_SID << 8 | 0x8e)
    47. 

  47. 

  48. #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550_H */
    49.