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dt-bindings
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qcom,spmi-adc5-gen3-pm5100.h

qcom,spmi-adc5-gen3-pm5100.h 3.9 KB
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
    4. 

  4.  */
    5. 

  5. 

  6. #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
    7. 

  7. #define _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H
    8. 

  8. 

  9. #ifndef PM5100_SID
    10. 

  10. #define PM5100_SID					0
    11. 

  11. #endif
    12. 

  12. 

  13. /* ADC channels for PM5100_ADC for PMIC5 Gen3 */
    14. 

  14. #define PM5100_ADC5_GEN3_OFFSET_REF			(PM5100_SID << 8 | 0x0)
    15. 

  15. #define PM5100_ADC5_GEN3_1P25VREF			(PM5100_SID << 8 | 0x01)
    16. 

  16. #define PM5100_ADC5_GEN3_VREF_VADC			(PM5100_SID << 8 | 0x02)
    17. 

  17. #define PM5100_ADC5_GEN3_DIE_TEMP			(PM5100_SID << 8 | 0x03)
    18. 

  18. 

  19. #define PM5100_ADC5_GEN3_AMUX1_THM			(PM5100_SID << 8 | 0x04)
    20. 

  20. #define PM5100_ADC5_GEN3_BAT_ID				(PM5100_SID << 8 | 0x05)
    21. 

  21. #define PM5100_ADC5_GEN3_BATT_THM			(PM5100_SID << 8 | 0x06)
    22. 

  22. #define PM5100_ADC5_GEN3_AMUX4_THM			(PM5100_SID << 8 | 0x07)
    23. 

  23. #define PM5100_ADC5_GEN3_AMUX5_THM			(PM5100_SID << 8 | 0x08)
    24. 

  24. #define PM5100_ADC5_GEN3_AMUX6_THM			(PM5100_SID << 8 | 0x09)
    25. 

  25. #define PM5100_ADC5_GEN3_AMUX1_GPIO10			(PM5100_SID << 8 | 0x0a)
    26. 

  26. #define PM5100_ADC5_GEN3_AMUX2_GPIO11			(PM5100_SID << 8 | 0x0b)
    27. 

  27. #define PM5100_ADC5_GEN3_AMUX3_GPIO			(PM5100_SID << 8 | 0x0c)
    28. 

  28. #define PM5100_ADC5_GEN3_AMUX4_GPIO			(PM5100_SID << 8 | 0x0d)
    29. 

  29. 

  30. #define PM5100_ADC5_GEN3_CHG_TEMP			(PM5100_SID << 8 | 0x10)
    31. 

  31. #define PM5100_ADC5_GEN3_USB_SNS_V_16			(PM5100_SID << 8 | 0x11)
    32. 

  32. #define PM5100_ADC5_GEN3_VIN_DIV16_MUX			(PM5100_SID << 8 | 0x12)
    33. 

  33. #define PM5100_ADC5_GEN3_USB_IN_I			(PM5100_SID << 8 | 0x17)
    34. 

  34. #define PM5100_ADC5_GEN3_ICHG_FB			(PM5100_SID << 8 | 0xa1)
    35. 

  35. 

  36. /* 30k pull-up1 */
    37. 

  37. #define PM5100_ADC5_GEN3_AMUX1_THM_30K_PU		(PM5100_SID << 8 | 0x24)
    38. 

  38. #define PM5100_ADC5_GEN3_BAT_ID_30K_PU			(PM5100_SID << 8 | 0x25)
    39. 

  39. #define PM5100_ADC5_GEN3_BATT_THM_30K_PU		(PM5100_SID << 8 | 0x26)
    40. 

  40. #define PM5100_ADC5_GEN3_AMUX4_THM_30K_PU		(PM5100_SID << 8 | 0x27)
    41. 

  41. #define PM5100_ADC5_GEN3_AMUX5_THM_30K_PU		(PM5100_SID << 8 | 0x28)
    42. 

  42. #define PM5100_ADC5_GEN3_AMUX6_THM_30K_PU		(PM5100_SID << 8 | 0x29)
    43. 

  43. #define PM5100_ADC5_GEN3_AMUX1_GPIO10_30K_PU		(PM5100_SID << 8 | 0x2a)
    44. 

  44. #define PM5100_ADC5_GEN3_AMUX2_GPIO11_30K_PU		(PM5100_SID << 8 | 0x2b)
    45. 

  45. #define PM5100_ADC5_GEN3_AMUX3_GPIO_30K_PU		(PM5100_SID << 8 | 0x2c)
    46. 

  46. #define PM5100_ADC5_GEN3_AMUX4_GPIO_30K_PU		(PM5100_SID << 8 | 0x2d)
    47. 

  47. 

  48. /* 100k pull-up2 */
    49. 

  49. #define PM5100_ADC5_GEN3_AMUX1_THM_100K_PU		(PM5100_SID << 8 | 0x44)
    50. 

  50. #define PM5100_ADC5_GEN3_BAT_ID_100K_PU			(PM5100_SID << 8 | 0x45)
    51. 

  51. #define PM5100_ADC5_GEN3_BATT_THM_100K_PU		(PM5100_SID << 8 | 0x46)
    52. 

  52. #define PM5100_ADC5_GEN3_AMUX4_THM_100K_PU		(PM5100_SID << 8 | 0x47)
    53. 

  53. #define PM5100_ADC5_GEN3_AMUX5_THM_100K_PU		(PM5100_SID << 8 | 0x48)
    54. 

  54. #define PM5100_ADC5_GEN3_AMUX6_THM_100K_PU		(PM5100_SID << 8 | 0x49)
    55. 

  55. #define PM5100_ADC5_GEN3_AMUX1_GPIO10_100K_PU		(PM5100_SID << 8 | 0x4a)
    56. 

  56. #define PM5100_ADC5_GEN3_AMUX2_GPIO11_100K_PU		(PM5100_SID << 8 | 0x4b)
    57. 

  57. #define PM5100_ADC5_GEN3_AMUX3_GPIO_100K_PU		(PM5100_SID << 8 | 0x4c)
    58. 

  58. #define PM5100_ADC5_GEN3_AMUX4_GPIO_100K_PU		(PM5100_SID << 8 | 0x4d)
    59. 

  59. 

  60. /* 400k pull-up3 */
    61. 

  61. #define PM5100_ADC5_GEN3_AMUX1_THM_400K_PU		(PM5100_SID << 8 | 0x64)
    62. 

  62. #define PM5100_ADC5_GEN3_BAT_ID_400K_PU			(PM5100_SID << 8 | 0x65)
    63. 

  63. #define PM5100_ADC5_GEN3_BATT_THM_400K_PU		(PM5100_SID << 8 | 0x66)
    64. 

  64. #define PM5100_ADC5_GEN3_AMUX4_THM_400K_PU		(PM5100_SID << 8 | 0x67)
    65. 

  65. #define PM5100_ADC5_GEN3_AMUX5_THM_400K_PU		(PM5100_SID << 8 | 0x68)
    66. 

  66. #define PM5100_ADC5_GEN3_AMUX6_THM_400K_PU		(PM5100_SID << 8 | 0x69)
    67. 

  67. #define PM5100_ADC5_GEN3_AMUX1_GPIO10_400K_PU		(PM5100_SID << 8 | 0x6a)
    68. 

  68. #define PM5100_ADC5_GEN3_AMUX2_GPIO11_400K_PU		(PM5100_SID << 8 | 0x6b)
    69. 

  69. #define PM5100_ADC5_GEN3_AMUX3_GPIO_400K_PU		(PM5100_SID << 8 | 0x6c)
    70. 

  70. #define PM5100_ADC5_GEN3_AMUX4_GPIO_400K_PU		(PM5100_SID << 8 | 0x6d)
    71. 

  71. 

  72. /* 1/3 Divider */
    73. 

  73. #define PM5100_ADC5_GEN3_GPIO10_DIV3			(PM5100_SID << 8 | 0x8a)
    74. 

  74. #define PM5100_ADC5_GEN3_GPIO11_DIV3			(PM5100_SID << 8 | 0x8b)
    75. 

  75. 

  76. #define PM5100_ADC5_GEN3_VPH_PWR			(PM5100_SID << 8 | 0x8e)
    77. 

  77. #define PM5100_ADC5_GEN3_VBAT_SNS_QBG			(PM5100_SID << 8 | 0x8f)
    78. 

  78. 

  79. #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM5100_H */
    80.