mt6779-gce.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: Dennis-YC Hsieh <[email protected]>
  5. */
  6. #ifndef _DT_BINDINGS_GCE_MT6779_H
  7. #define _DT_BINDINGS_GCE_MT6779_H
  8. #define CMDQ_NO_TIMEOUT 0xffffffff
  9. /* GCE HW thread priority */
  10. #define CMDQ_THR_PRIO_LOWEST 0
  11. #define CMDQ_THR_PRIO_1 1
  12. #define CMDQ_THR_PRIO_2 2
  13. #define CMDQ_THR_PRIO_3 3
  14. #define CMDQ_THR_PRIO_4 4
  15. #define CMDQ_THR_PRIO_5 5
  16. #define CMDQ_THR_PRIO_6 6
  17. #define CMDQ_THR_PRIO_HIGHEST 7
  18. /* GCE subsys table */
  19. #define SUBSYS_1300XXXX 0
  20. #define SUBSYS_1400XXXX 1
  21. #define SUBSYS_1401XXXX 2
  22. #define SUBSYS_1402XXXX 3
  23. #define SUBSYS_1502XXXX 4
  24. #define SUBSYS_1880XXXX 5
  25. #define SUBSYS_1881XXXX 6
  26. #define SUBSYS_1882XXXX 7
  27. #define SUBSYS_1883XXXX 8
  28. #define SUBSYS_1884XXXX 9
  29. #define SUBSYS_1000XXXX 10
  30. #define SUBSYS_1001XXXX 11
  31. #define SUBSYS_1002XXXX 12
  32. #define SUBSYS_1003XXXX 13
  33. #define SUBSYS_1004XXXX 14
  34. #define SUBSYS_1005XXXX 15
  35. #define SUBSYS_1020XXXX 16
  36. #define SUBSYS_1028XXXX 17
  37. #define SUBSYS_1700XXXX 18
  38. #define SUBSYS_1701XXXX 19
  39. #define SUBSYS_1702XXXX 20
  40. #define SUBSYS_1703XXXX 21
  41. #define SUBSYS_1800XXXX 22
  42. #define SUBSYS_1801XXXX 23
  43. #define SUBSYS_1802XXXX 24
  44. #define SUBSYS_1804XXXX 25
  45. #define SUBSYS_1805XXXX 26
  46. #define SUBSYS_1808XXXX 27
  47. #define SUBSYS_180aXXXX 28
  48. #define SUBSYS_180bXXXX 29
  49. #define CMDQ_SUBSYS_OFF 32
  50. /* GCE hardware events */
  51. #define CMDQ_EVENT_DISP_RDMA0_SOF 0
  52. #define CMDQ_EVENT_DISP_RDMA1_SOF 1
  53. #define CMDQ_EVENT_MDP_RDMA0_SOF 2
  54. #define CMDQ_EVENT_MDP_RDMA1_SOF 3
  55. #define CMDQ_EVENT_MDP_RSZ0_SOF 4
  56. #define CMDQ_EVENT_MDP_RSZ1_SOF 5
  57. #define CMDQ_EVENT_MDP_TDSHP_SOF 6
  58. #define CMDQ_EVENT_MDP_WROT0_SOF 7
  59. #define CMDQ_EVENT_MDP_WROT1_SOF 8
  60. #define CMDQ_EVENT_DISP_OVL0_SOF 9
  61. #define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
  62. #define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
  63. #define CMDQ_EVENT_DISP_WDMA0_SOF 12
  64. #define CMDQ_EVENT_DISP_COLOR0_SOF 13
  65. #define CMDQ_EVENT_DISP_CCORR0_SOF 14
  66. #define CMDQ_EVENT_DISP_AAL0_SOF 15
  67. #define CMDQ_EVENT_DISP_GAMMA0_SOF 16
  68. #define CMDQ_EVENT_DISP_DITHER0_SOF 17
  69. #define CMDQ_EVENT_DISP_PWM0_SOF 18
  70. #define CMDQ_EVENT_DISP_DSI0_SOF 19
  71. #define CMDQ_EVENT_DISP_DPI0_SOF 20
  72. #define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
  73. #define CMDQ_EVENT_DISP_RSZ0_SOF 22
  74. #define CMDQ_EVENT_MDP_AAL_SOF 23
  75. #define CMDQ_EVENT_MDP_CCORR_SOF 24
  76. #define CMDQ_EVENT_DISP_DBI0_SOF 25
  77. #define CMDQ_EVENT_ISP_RELAY_SOF 26
  78. #define CMDQ_EVENT_IPU_RELAY_SOF 27
  79. #define CMDQ_EVENT_DISP_RDMA0_EOF 28
  80. #define CMDQ_EVENT_DISP_RDMA1_EOF 29
  81. #define CMDQ_EVENT_MDP_RDMA0_EOF 30
  82. #define CMDQ_EVENT_MDP_RDMA1_EOF 31
  83. #define CMDQ_EVENT_MDP_RSZ0_EOF 32
  84. #define CMDQ_EVENT_MDP_RSZ1_EOF 33
  85. #define CMDQ_EVENT_MDP_TDSHP_EOF 34
  86. #define CMDQ_EVENT_MDP_WROT0_W_EOF 35
  87. #define CMDQ_EVENT_MDP_WROT1_W_EOF 36
  88. #define CMDQ_EVENT_DISP_OVL0_EOF 37
  89. #define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
  90. #define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
  91. #define CMDQ_EVENT_DISP_WDMA0_EOF 40
  92. #define CMDQ_EVENT_DISP_COLOR0_EOF 41
  93. #define CMDQ_EVENT_DISP_CCORR0_EOF 42
  94. #define CMDQ_EVENT_DISP_AAL0_EOF 43
  95. #define CMDQ_EVENT_DISP_GAMMA0_EOF 44
  96. #define CMDQ_EVENT_DISP_DITHER0_EOF 45
  97. #define CMDQ_EVENT_DISP_DSI0_EOF 46
  98. #define CMDQ_EVENT_DISP_DPI0_EOF 47
  99. #define CMDQ_EVENT_DISP_RSZ0_EOF 49
  100. #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
  101. #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
  102. #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
  103. #define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
  104. #define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
  105. #define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
  106. #define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
  107. #define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
  108. #define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
  109. #define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
  110. #define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
  111. #define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
  112. #define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
  113. #define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
  114. #define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
  115. #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
  116. #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
  117. #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
  118. #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
  119. #define CMDQ_EVENT_DSI0_TE 146
  120. #define CMDQ_EVENT_DSI0_IRQ_EVENT 147
  121. #define CMDQ_EVENT_DSI0_DONE_EVENT 148
  122. #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
  123. #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
  124. #define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
  125. #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
  126. #define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
  127. #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
  128. #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
  129. #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
  130. #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
  131. #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
  132. #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
  133. #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
  134. #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
  135. #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
  136. #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
  137. #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
  138. #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
  139. #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
  140. #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
  141. #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
  142. #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
  143. #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
  144. #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
  145. #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
  146. #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
  147. #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
  148. #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
  149. #define CMDQ_EVENT_AMD_FRAME_DONE 277
  150. #define CMDQ_EVENT_MFB_DONE 278
  151. #define CMDQ_EVENT_WPE_A_EOF 279
  152. #define CMDQ_EVENT_VENC_EOF 289
  153. #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
  154. #define CMDQ_EVENT_JPEG_ENC_EOF 291
  155. #define CMDQ_EVENT_VENC_MB_DONE 292
  156. #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
  157. #define CMDQ_EVENT_ISP_FRAME_DONE_A 321
  158. #define CMDQ_EVENT_ISP_FRAME_DONE_B 322
  159. #define CMDQ_EVENT_ISP_FRAME_DONE_C 323
  160. #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
  161. #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
  162. #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
  163. #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
  164. #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
  165. #define CMDQ_EVENT_ISP_TSF_DONE 329
  166. #define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
  167. #define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
  168. #define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
  169. #define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
  170. #define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
  171. #define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
  172. #define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
  173. #define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
  174. #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
  175. #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
  176. #define CMDQ_EVENT_TG_OVRUN_C_INT 340
  177. #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
  178. #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
  179. #define CMDQ_EVENT_TG_GRABERR_C_INT 343
  180. #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
  181. #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
  182. #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
  183. #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
  184. #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
  185. #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
  186. #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
  187. #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
  188. #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
  189. #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
  190. #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
  191. #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
  192. #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
  193. #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
  194. #define CMDQ_EVENT_VDEC_EVENT_0 416
  195. #define CMDQ_EVENT_VDEC_EVENT_1 417
  196. #define CMDQ_EVENT_VDEC_EVENT_2 418
  197. #define CMDQ_EVENT_VDEC_EVENT_3 419
  198. #define CMDQ_EVENT_VDEC_EVENT_4 420
  199. #define CMDQ_EVENT_VDEC_EVENT_5 421
  200. #define CMDQ_EVENT_VDEC_EVENT_6 422
  201. #define CMDQ_EVENT_VDEC_EVENT_7 423
  202. #define CMDQ_EVENT_VDEC_EVENT_8 424
  203. #define CMDQ_EVENT_VDEC_EVENT_9 425
  204. #define CMDQ_EVENT_VDEC_EVENT_10 426
  205. #define CMDQ_EVENT_VDEC_EVENT_11 427
  206. #define CMDQ_EVENT_VDEC_EVENT_12 428
  207. #define CMDQ_EVENT_VDEC_EVENT_13 429
  208. #define CMDQ_EVENT_VDEC_EVENT_14 430
  209. #define CMDQ_EVENT_VDEC_EVENT_15 431
  210. #define CMDQ_EVENT_FDVT_DONE 449
  211. #define CMDQ_EVENT_FE_DONE 450
  212. #define CMDQ_EVENT_RSC_EOF 451
  213. #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
  214. #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
  215. #define CMDQ_EVENT_DSI0_TE_INFRA 898
  216. #endif