qcom,gcc-sm6125.h 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2. /*
  3. * Copyright (c) 2021, Konrad Dybcio <[email protected]>
  4. */
  5. #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
  6. #define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
  7. #define GPLL0_OUT_AUX2 0
  8. #define GPLL0_OUT_MAIN 1
  9. #define GPLL6_OUT_MAIN 2
  10. #define GPLL7_OUT_MAIN 3
  11. #define GPLL8_OUT_MAIN 4
  12. #define GPLL9_OUT_MAIN 5
  13. #define GPLL0_OUT_EARLY 6
  14. #define GPLL3_OUT_EARLY 7
  15. #define GPLL4_OUT_MAIN 8
  16. #define GPLL5_OUT_MAIN 9
  17. #define GPLL6_OUT_EARLY 10
  18. #define GPLL7_OUT_EARLY 11
  19. #define GPLL8_OUT_EARLY 12
  20. #define GPLL9_OUT_EARLY 13
  21. #define GCC_AHB2PHY_CSI_CLK 14
  22. #define GCC_AHB2PHY_USB_CLK 15
  23. #define GCC_APC_VS_CLK 16
  24. #define GCC_BOOT_ROM_AHB_CLK 17
  25. #define GCC_CAMERA_AHB_CLK 18
  26. #define GCC_CAMERA_XO_CLK 19
  27. #define GCC_CAMSS_AHB_CLK_SRC 20
  28. #define GCC_CAMSS_CCI_AHB_CLK 21
  29. #define GCC_CAMSS_CCI_CLK 22
  30. #define GCC_CAMSS_CCI_CLK_SRC 23
  31. #define GCC_CAMSS_CPHY_CSID0_CLK 24
  32. #define GCC_CAMSS_CPHY_CSID1_CLK 25
  33. #define GCC_CAMSS_CPHY_CSID2_CLK 26
  34. #define GCC_CAMSS_CPHY_CSID3_CLK 27
  35. #define GCC_CAMSS_CPP_AHB_CLK 28
  36. #define GCC_CAMSS_CPP_AXI_CLK 29
  37. #define GCC_CAMSS_CPP_CLK 30
  38. #define GCC_CAMSS_CPP_CLK_SRC 31
  39. #define GCC_CAMSS_CPP_VBIF_AHB_CLK 32
  40. #define GCC_CAMSS_CSI0_AHB_CLK 33
  41. #define GCC_CAMSS_CSI0_CLK 34
  42. #define GCC_CAMSS_CSI0_CLK_SRC 35
  43. #define GCC_CAMSS_CSI0PHYTIMER_CLK 36
  44. #define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37
  45. #define GCC_CAMSS_CSI0PIX_CLK 38
  46. #define GCC_CAMSS_CSI0RDI_CLK 39
  47. #define GCC_CAMSS_CSI1_AHB_CLK 40
  48. #define GCC_CAMSS_CSI1_CLK 41
  49. #define GCC_CAMSS_CSI1_CLK_SRC 42
  50. #define GCC_CAMSS_CSI1PHYTIMER_CLK 43
  51. #define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44
  52. #define GCC_CAMSS_CSI1PIX_CLK 45
  53. #define GCC_CAMSS_CSI1RDI_CLK 46
  54. #define GCC_CAMSS_CSI2_AHB_CLK 47
  55. #define GCC_CAMSS_CSI2_CLK 48
  56. #define GCC_CAMSS_CSI2_CLK_SRC 49
  57. #define GCC_CAMSS_CSI2PHYTIMER_CLK 50
  58. #define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51
  59. #define GCC_CAMSS_CSI2PIX_CLK 52
  60. #define GCC_CAMSS_CSI2RDI_CLK 53
  61. #define GCC_CAMSS_CSI3_AHB_CLK 54
  62. #define GCC_CAMSS_CSI3_CLK 55
  63. #define GCC_CAMSS_CSI3_CLK_SRC 56
  64. #define GCC_CAMSS_CSI3PIX_CLK 57
  65. #define GCC_CAMSS_CSI3RDI_CLK 58
  66. #define GCC_CAMSS_CSI_VFE0_CLK 59
  67. #define GCC_CAMSS_CSI_VFE1_CLK 60
  68. #define GCC_CAMSS_CSIPHY0_CLK 61
  69. #define GCC_CAMSS_CSIPHY1_CLK 62
  70. #define GCC_CAMSS_CSIPHY2_CLK 63
  71. #define GCC_CAMSS_CSIPHY_CLK_SRC 64
  72. #define GCC_CAMSS_GP0_CLK 65
  73. #define GCC_CAMSS_GP0_CLK_SRC 66
  74. #define GCC_CAMSS_GP1_CLK 67
  75. #define GCC_CAMSS_GP1_CLK_SRC 68
  76. #define GCC_CAMSS_ISPIF_AHB_CLK 69
  77. #define GCC_CAMSS_JPEG_AHB_CLK 70
  78. #define GCC_CAMSS_JPEG_AXI_CLK 71
  79. #define GCC_CAMSS_JPEG_CLK 72
  80. #define GCC_CAMSS_JPEG_CLK_SRC 73
  81. #define GCC_CAMSS_MCLK0_CLK 74
  82. #define GCC_CAMSS_MCLK0_CLK_SRC 75
  83. #define GCC_CAMSS_MCLK1_CLK 76
  84. #define GCC_CAMSS_MCLK1_CLK_SRC 77
  85. #define GCC_CAMSS_MCLK2_CLK 78
  86. #define GCC_CAMSS_MCLK2_CLK_SRC 79
  87. #define GCC_CAMSS_MCLK3_CLK 80
  88. #define GCC_CAMSS_MCLK3_CLK_SRC 81
  89. #define GCC_CAMSS_MICRO_AHB_CLK 82
  90. #define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83
  91. #define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84
  92. #define GCC_CAMSS_TOP_AHB_CLK 85
  93. #define GCC_CAMSS_VFE0_AHB_CLK 86
  94. #define GCC_CAMSS_VFE0_CLK 87
  95. #define GCC_CAMSS_VFE0_CLK_SRC 88
  96. #define GCC_CAMSS_VFE0_STREAM_CLK 89
  97. #define GCC_CAMSS_VFE1_AHB_CLK 90
  98. #define GCC_CAMSS_VFE1_CLK 91
  99. #define GCC_CAMSS_VFE1_CLK_SRC 92
  100. #define GCC_CAMSS_VFE1_STREAM_CLK 93
  101. #define GCC_CAMSS_VFE_TSCTR_CLK 94
  102. #define GCC_CAMSS_VFE_VBIF_AHB_CLK 95
  103. #define GCC_CAMSS_VFE_VBIF_AXI_CLK 96
  104. #define GCC_CE1_AHB_CLK 97
  105. #define GCC_CE1_AXI_CLK 98
  106. #define GCC_CE1_CLK 99
  107. #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100
  108. #define GCC_CPUSS_GNOC_CLK 101
  109. #define GCC_DISP_AHB_CLK 102
  110. #define GCC_DISP_GPLL0_DIV_CLK_SRC 103
  111. #define GCC_DISP_HF_AXI_CLK 104
  112. #define GCC_DISP_THROTTLE_CORE_CLK 105
  113. #define GCC_DISP_XO_CLK 106
  114. #define GCC_GP1_CLK 107
  115. #define GCC_GP1_CLK_SRC 108
  116. #define GCC_GP2_CLK 109
  117. #define GCC_GP2_CLK_SRC 110
  118. #define GCC_GP3_CLK 111
  119. #define GCC_GP3_CLK_SRC 112
  120. #define GCC_GPU_CFG_AHB_CLK 113
  121. #define GCC_GPU_GPLL0_CLK_SRC 114
  122. #define GCC_GPU_GPLL0_DIV_CLK_SRC 115
  123. #define GCC_GPU_MEMNOC_GFX_CLK 116
  124. #define GCC_GPU_SNOC_DVM_GFX_CLK 117
  125. #define GCC_GPU_THROTTLE_CORE_CLK 118
  126. #define GCC_GPU_THROTTLE_XO_CLK 119
  127. #define GCC_MSS_VS_CLK 120
  128. #define GCC_PDM2_CLK 121
  129. #define GCC_PDM2_CLK_SRC 122
  130. #define GCC_PDM_AHB_CLK 123
  131. #define GCC_PDM_XO4_CLK 124
  132. #define GCC_PRNG_AHB_CLK 125
  133. #define GCC_QMIP_CAMERA_NRT_AHB_CLK 126
  134. #define GCC_QMIP_CAMERA_RT_AHB_CLK 127
  135. #define GCC_QMIP_DISP_AHB_CLK 128
  136. #define GCC_QMIP_GPU_CFG_AHB_CLK 129
  137. #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 130
  138. #define GCC_QUPV3_WRAP0_CORE_2X_CLK 131
  139. #define GCC_QUPV3_WRAP0_CORE_CLK 132
  140. #define GCC_QUPV3_WRAP0_S0_CLK 133
  141. #define GCC_QUPV3_WRAP0_S0_CLK_SRC 134
  142. #define GCC_QUPV3_WRAP0_S1_CLK 135
  143. #define GCC_QUPV3_WRAP0_S1_CLK_SRC 136
  144. #define GCC_QUPV3_WRAP0_S2_CLK 137
  145. #define GCC_QUPV3_WRAP0_S2_CLK_SRC 138
  146. #define GCC_QUPV3_WRAP0_S3_CLK 139
  147. #define GCC_QUPV3_WRAP0_S3_CLK_SRC 140
  148. #define GCC_QUPV3_WRAP0_S4_CLK 141
  149. #define GCC_QUPV3_WRAP0_S4_CLK_SRC 142
  150. #define GCC_QUPV3_WRAP0_S5_CLK 143
  151. #define GCC_QUPV3_WRAP0_S5_CLK_SRC 144
  152. #define GCC_QUPV3_WRAP1_CORE_2X_CLK 145
  153. #define GCC_QUPV3_WRAP1_CORE_CLK 146
  154. #define GCC_QUPV3_WRAP1_S0_CLK 147
  155. #define GCC_QUPV3_WRAP1_S0_CLK_SRC 148
  156. #define GCC_QUPV3_WRAP1_S1_CLK 149
  157. #define GCC_QUPV3_WRAP1_S1_CLK_SRC 150
  158. #define GCC_QUPV3_WRAP1_S2_CLK 151
  159. #define GCC_QUPV3_WRAP1_S2_CLK_SRC 152
  160. #define GCC_QUPV3_WRAP1_S3_CLK 153
  161. #define GCC_QUPV3_WRAP1_S3_CLK_SRC 154
  162. #define GCC_QUPV3_WRAP1_S4_CLK 155
  163. #define GCC_QUPV3_WRAP1_S4_CLK_SRC 156
  164. #define GCC_QUPV3_WRAP1_S5_CLK 157
  165. #define GCC_QUPV3_WRAP1_S5_CLK_SRC 158
  166. #define GCC_QUPV3_WRAP_0_M_AHB_CLK 159
  167. #define GCC_QUPV3_WRAP_0_S_AHB_CLK 160
  168. #define GCC_QUPV3_WRAP_1_M_AHB_CLK 161
  169. #define GCC_QUPV3_WRAP_1_S_AHB_CLK 162
  170. #define GCC_SDCC1_AHB_CLK 163
  171. #define GCC_SDCC1_APPS_CLK 164
  172. #define GCC_SDCC1_APPS_CLK_SRC 165
  173. #define GCC_SDCC1_ICE_CORE_CLK 166
  174. #define GCC_SDCC1_ICE_CORE_CLK_SRC 167
  175. #define GCC_SDCC2_AHB_CLK 168
  176. #define GCC_SDCC2_APPS_CLK 169
  177. #define GCC_SDCC2_APPS_CLK_SRC 170
  178. #define GCC_SYS_NOC_CPUSS_AHB_CLK 171
  179. #define GCC_SYS_NOC_UFS_PHY_AXI_CLK 172
  180. #define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 173
  181. #define GCC_UFS_PHY_AHB_CLK 174
  182. #define GCC_UFS_PHY_AXI_CLK 175
  183. #define GCC_UFS_PHY_AXI_CLK_SRC 176
  184. #define GCC_UFS_PHY_ICE_CORE_CLK 177
  185. #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 178
  186. #define GCC_UFS_PHY_PHY_AUX_CLK 179
  187. #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 180
  188. #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181
  189. #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 182
  190. #define GCC_UFS_PHY_UNIPRO_CORE_CLK 183
  191. #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184
  192. #define GCC_USB30_PRIM_MASTER_CLK 185
  193. #define GCC_USB30_PRIM_MASTER_CLK_SRC 186
  194. #define GCC_USB30_PRIM_MOCK_UTMI_CLK 187
  195. #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 188
  196. #define GCC_USB30_PRIM_SLEEP_CLK 189
  197. #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 190
  198. #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 191
  199. #define GCC_USB3_PRIM_PHY_PIPE_CLK 192
  200. #define GCC_VDDA_VS_CLK 193
  201. #define GCC_VDDCX_VS_CLK 194
  202. #define GCC_VDDMX_VS_CLK 195
  203. #define GCC_VIDEO_AHB_CLK 196
  204. #define GCC_VIDEO_AXI0_CLK 197
  205. #define GCC_VIDEO_THROTTLE_CORE_CLK 198
  206. #define GCC_VIDEO_XO_CLK 199
  207. #define GCC_VS_CTRL_AHB_CLK 200
  208. #define GCC_VS_CTRL_CLK 201
  209. #define GCC_VS_CTRL_CLK_SRC 202
  210. #define GCC_VSENSOR_CLK_SRC 203
  211. #define GCC_WCSS_VS_CLK 204
  212. #define GCC_USB3_PRIM_CLKREF_CLK 205
  213. #define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 206
  214. #define GCC_BIMC_GPU_AXI_CLK 207
  215. #define GCC_UFS_MEM_CLKREF_CLK 208
  216. /* GDSCs */
  217. #define USB30_PRIM_GDSC 0
  218. #define UFS_PHY_GDSC 1
  219. #define CAMSS_VFE0_GDSC 2
  220. #define CAMSS_VFE1_GDSC 3
  221. #define CAMSS_TOP_GDSC 4
  222. #define CAM_CPP_GDSC 5
  223. #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 6
  224. #define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7
  225. #define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8
  226. #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 9
  227. #define GCC_QUSB2PHY_PRIM_BCR 0
  228. #define GCC_QUSB2PHY_SEC_BCR 1
  229. #define GCC_UFS_PHY_BCR 2
  230. #define GCC_USB30_PRIM_BCR 3
  231. #define GCC_USB_PHY_CFG_AHB2PHY_BCR 4
  232. #define GCC_USB3_PHY_PRIM_SP0_BCR 5
  233. #define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6
  234. #define GCC_CAMSS_MICRO_BCR 7
  235. #endif